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https://github.com/torvalds/linux.git
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54bdf8a399
Pull phy updates from Vinod Koul: "New support: - UFS PHY for Qualcomm SA8775p, SM7150 - PCIe 2 lane phy support for sc8180x and PCIe PHY for SDX65 - Mediatke hdmi phy support for mt8195 - rockchip naneng combo phy support for RK358 Updates: - Drop Thunder Bay eMMC PHY driver - RC support for PCIe phy for Qualcomm SDX55 - SGMII support in WIZ driver for J721E - PCIe and multilink SGMII PHY support in cadence driver - Big pile of platform remove callback returning void conversions" * tag 'phy-for-6.4' of git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy: (77 commits) phy: cadence: cdns-dphy-rx: Add common module reset support phy: ti: j721e-wiz: Add SGMII support in WIZ driver for J721E dt-bindings: phy: ti: phy-gmii-sel: Add support for J784S4 CPSW9G phy: ti: j721e-wiz: Fix unreachable code in wiz_mode_select() phy: cadence: Sierra: Add PCIe + SGMII PHY multilink configuration phy: mediatek: add support for phy-mtk-hdmi-mt8195 phy: phy-mtk-hdmi: Add generic phy configure callback dt-bindings: phy: mediatek: hdmi-phy: Add mt8195 compatible phy: tegra: xusb: Add missing tegra_xusb_port_unregister for usb2_port and ulpi_port dt-bindings: phy: ti,phy-j721e-wiz: document clock-output-names dt-bindings: phy: ti,phy-j721e-wiz: drop assigned-clocks dt-bindings: phy: ti,phy-am654-serdes: drop assigned-clocks type dt-bindings: phy: cadence-torrent: drop assigned-clocks dt-bindings: phy: cadence-sierra: drop assigned-clocks phy: rockchip: remove unused hw_to_inno function phy: qualcomm: phy-qcom-qmp-ufs: add definitions for sa8775p dt-bindings: phy: qmp-ufs: describe the UFS PHY for sa8775p phy: qcom-qmp-pcie: drop sdm845_qhp_pcie_rx_tbl phy: qcom-qmp-pcie: sc8180x PCIe PHY has 2 lanes phy: qcom-qmp-ufs: Add SM7150 support ...
110 lines
2.4 KiB
YAML
110 lines
2.4 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/phy/marvell,armada-cp110-utmi-phy.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Marvell Armada CP110/CP115 UTMI PHY
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maintainers:
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- Konstantin Porotchkin <kostap@marvell.com>
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description:
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On Armada 7k/8k and CN913x, there are two host and one device USB controllers.
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Each of two exiting UTMI PHYs could be connected to either USB host or USB device
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controller.
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The USB device controller can only be connected to a single UTMI PHY port
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0.H----- USB HOST0
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UTMI PHY0 --------/
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0.D-----0
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\------ USB DEVICE
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1.D-----1
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UTMI PHY1 --------\
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1.H----- USB HOST1
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properties:
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compatible:
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const: marvell,cp110-utmi-phy
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reg:
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maxItems: 1
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"#address-cells":
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const: 1
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"#size-cells":
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const: 0
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marvell,system-controller:
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description:
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Phandle to the system controller node
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$ref: /schemas/types.yaml#/definitions/phandle
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# Required child nodes:
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patternProperties:
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"^usb-phy@[0|1]$":
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type: object
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description:
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Each UTMI PHY port must be represented as a sub-node.
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properties:
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reg:
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description: phy port index.
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maxItems: 1
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"#phy-cells":
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const: 0
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required:
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- reg
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- "#phy-cells"
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additionalProperties: false
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required:
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- compatible
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- reg
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- "#address-cells"
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- "#size-cells"
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- marvell,system-controller
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additionalProperties: false
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examples:
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- |
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cp0_utmi: utmi@580000 {
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compatible = "marvell,cp110-utmi-phy";
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reg = <0x580000 0x2000>;
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marvell,system-controller = <&cp0_syscon0>;
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#address-cells = <1>;
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#size-cells = <0>;
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cp0_utmi0: usb-phy@0 {
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reg = <0>;
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#phy-cells = <0>;
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};
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cp0_utmi1: usb-phy@1 {
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reg = <1>;
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#phy-cells = <0>;
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};
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};
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cp0_usb3_0 {
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usb-phy = <&cp0_usb3_0_phy0>;
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phys = <&cp0_utmi0>;
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phy-names = "utmi";
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/* UTMI0 is connected to USB host controller (default mode) */
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dr_mode = "host";
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};
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cp0_usb3_1 {
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usb-phy = <&cp0_usb3_0_phy1>;
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phys = <&cp0_utmi1>;
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phy-names = "utmi";
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/* UTMI1 is connected to USB device controller */
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dr_mode = "peripheral";
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};
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