Hal Feng 1558209533 riscv: dts: starfive: visionfive 2: Fix uart0 pins sort order ...

Node uart0_pins should be sorted alphabetically.

Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>

2023-09-13 14:24:56 +01:00

..

allwinner

riscv: dts: allwinner: d1: Add CAN controller nodes

2023-08-13 14:12:35 +08:00

canaan

riscv: dts: canaan: drop invalid spi-max-frequency

2023-03-26 23:58:27 +01:00

microchip

riscv: dts: microchip: fix the mpfs' mailbox regs

2023-03-15 14:43:48 +00:00

renesas

riscv: dts: renesas: Clean up dtbs_check W=1 warning due to empty phy node

2023-07-25 11:41:09 +02:00

sifive

Merge tag 'soc-dt-6.3' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc

2023-02-20 15:49:56 -08:00

starfive

riscv: dts: starfive: visionfive 2: Fix uart0 pins sort order

2023-09-13 14:24:56 +01:00

thead

riscv: dts: change TH1520 files to dual license

2023-08-16 18:59:30 +01:00

Makefile

riscv: dts: sort makefile entries by directory

2023-06-19 07:59:36 +01:00