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This patch adds driver for MediaTek's Media Data Path ver.3 (MDP3).
It provides the following functions:
color transform, format conversion, resize, crop, rotate, flip
and additional image quality enhancement.
The MDP3 driver is mainly used for Google Chromebook products to
import the new architecture to set the HW settings as shown below:
User -> V4L2 framework
-> MDP3 driver -> SCP (setting calculations)
-> MDP3 driver -> CMDQ (GCE driver) -> HW
Each modules' related operation control is sited in mtk-mdp3-comp.c
Each modules' register table is defined in file with "mdp_reg_" prefix
GCE related API, operation control sited in mtk-mdp3-cmdq.c
V4L2 m2m device functions are implemented in mtk-mdp3-m2m.c
Probe, power, suspend/resume, system level functions are defined in
mtk-mdp3-core.c
[hverkuil: add 'depends on REMOTEPROC']
Signed-off-by: Ping-Hsun Wu <ping-hsun.wu@mediatek.com>
Signed-off-by: daoyuan huang <daoyuan.huang@mediatek.com>
Signed-off-by: Moudy Ho <moudy.ho@mediatek.com>
Tested-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Signed-off-by: Hans Verkuil <hverkuil-cisco@xs4all.nl>
Signed-off-by: Mauro Carvalho Chehab <mchehab@kernel.org>
66 lines
2.8 KiB
C
66 lines
2.8 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (c) 2022 MediaTek Inc.
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* Author: Ping-Hsun Wu <ping-hsun.wu@mediatek.com>
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*/
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#ifndef __MDP_REG_RDMA_H__
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#define __MDP_REG_RDMA_H__
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#define MDP_RDMA_EN 0x000
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#define MDP_RDMA_RESET 0x008
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#define MDP_RDMA_CON 0x020
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#define MDP_RDMA_GMCIF_CON 0x028
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#define MDP_RDMA_SRC_CON 0x030
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#define MDP_RDMA_MF_BKGD_SIZE_IN_BYTE 0x060
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#define MDP_RDMA_MF_BKGD_SIZE_IN_PXL 0x068
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#define MDP_RDMA_MF_SRC_SIZE 0x070
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#define MDP_RDMA_MF_CLIP_SIZE 0x078
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#define MDP_RDMA_MF_OFFSET_1 0x080
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#define MDP_RDMA_SF_BKGD_SIZE_IN_BYTE 0x090
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#define MDP_RDMA_SRC_END_0 0x100
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#define MDP_RDMA_SRC_END_1 0x108
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#define MDP_RDMA_SRC_END_2 0x110
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#define MDP_RDMA_SRC_OFFSET_0 0x118
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#define MDP_RDMA_SRC_OFFSET_1 0x120
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#define MDP_RDMA_SRC_OFFSET_2 0x128
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#define MDP_RDMA_SRC_OFFSET_0_P 0x148
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#define MDP_RDMA_TRANSFORM_0 0x200
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#define MDP_RDMA_RESV_DUMMY_0 0x2a0
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#define MDP_RDMA_MON_STA_1 0x408
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#define MDP_RDMA_SRC_BASE_0 0xf00
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#define MDP_RDMA_SRC_BASE_1 0xf08
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#define MDP_RDMA_SRC_BASE_2 0xf10
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#define MDP_RDMA_UFO_DEC_LENGTH_BASE_Y 0xf20
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#define MDP_RDMA_UFO_DEC_LENGTH_BASE_C 0xf28
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/* MASK */
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#define MDP_RDMA_EN_MASK 0x00000001
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#define MDP_RDMA_RESET_MASK 0x00000001
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#define MDP_RDMA_CON_MASK 0x00001110
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#define MDP_RDMA_GMCIF_CON_MASK 0xfffb3771
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#define MDP_RDMA_SRC_CON_MASK 0xf3ffffff
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#define MDP_RDMA_MF_BKGD_SIZE_IN_BYTE_MASK 0x001fffff
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#define MDP_RDMA_MF_BKGD_SIZE_IN_PXL_MASK 0x001fffff
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#define MDP_RDMA_MF_SRC_SIZE_MASK 0x1fff1fff
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#define MDP_RDMA_MF_CLIP_SIZE_MASK 0x1fff1fff
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#define MDP_RDMA_MF_OFFSET_1_MASK 0x003f001f
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#define MDP_RDMA_SF_BKGD_SIZE_IN_BYTE_MASK 0x001fffff
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#define MDP_RDMA_SRC_END_0_MASK 0xffffffff
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#define MDP_RDMA_SRC_END_1_MASK 0xffffffff
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#define MDP_RDMA_SRC_END_2_MASK 0xffffffff
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#define MDP_RDMA_SRC_OFFSET_0_MASK 0xffffffff
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#define MDP_RDMA_SRC_OFFSET_1_MASK 0xffffffff
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#define MDP_RDMA_SRC_OFFSET_2_MASK 0xffffffff
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#define MDP_RDMA_SRC_OFFSET_0_P_MASK 0xffffffff
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#define MDP_RDMA_TRANSFORM_0_MASK 0xff110777
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#define MDP_RDMA_RESV_DUMMY_0_MASK 0xffffffff
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#define MDP_RDMA_MON_STA_1_MASK 0xffffffff
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#define MDP_RDMA_SRC_BASE_0_MASK 0xffffffff
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#define MDP_RDMA_SRC_BASE_1_MASK 0xffffffff
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#define MDP_RDMA_SRC_BASE_2_MASK 0xffffffff
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#define MDP_RDMA_UFO_DEC_LENGTH_BASE_Y_MASK 0xffffffff
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#define MDP_RDMA_UFO_DEC_LENGTH_BASE_C_MASK 0xffffffff
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#endif // __MDP_REG_RDMA_H__
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