mirror of
https://github.com/torvalds/linux.git
synced 2026-04-19 23:34:00 -04:00
e4c8d01865
Pull ARM SoC driver updates from Arnd Bergmann:
"Nothing surprising in the SoC specific drivers, with the usual
updates:
- Added or improved SoC driver support for Tegra234, Exynos4121,
RK3588, as well as multiple Mediatek and Qualcomm chips
- SCMI firmware gains support for multiple SMC/HVC transport and
version 3.2 of the protocol
- Cleanups amd minor changes for the reset controller, memory
controller, firmware and sram drivers
- Minor changes to amd/xilinx, samsung, tegra, nxp, ti, qualcomm,
amlogic and renesas SoC specific drivers"
* tag 'soc-drivers-6.5' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (118 commits)
dt-bindings: interrupt-controller: Convert Amlogic Meson GPIO interrupt controller binding
MAINTAINERS: add PHY-related files to Amlogic SoC file list
drivers: meson: secure-pwrc: always enable DMA domain
tee: optee: Use kmemdup() to replace kmalloc + memcpy
soc: qcom: geni-se: Do not bother about enable/disable of interrupts in secondary sequencer
dt-bindings: sram: qcom,imem: document qdu1000
soc: qcom: icc-bwmon: Fix MSM8998 count unit
dt-bindings: soc: qcom,rpmh-rsc: Require power-domains
soc: qcom: socinfo: Add Soc ID for IPQ5300
dt-bindings: arm: qcom,ids: add SoC ID for IPQ5300
soc: qcom: Fix a IS_ERR() vs NULL bug in probe
soc: qcom: socinfo: Add support for new fields in revision 19
soc: qcom: socinfo: Add support for new fields in revision 18
dt-bindings: firmware: scm: Add compatible for SDX75
soc: qcom: mdt_loader: Fix split image detection
dt-bindings: memory-controllers: drop unneeded quotes
soc: rockchip: dtpm: use C99 array init syntax
firmware: tegra: bpmp: Add support for DRAM MRQ GSCs
soc/tegra: pmc: Use devm_clk_notifier_register()
soc/tegra: pmc: Simplify debugfs initialization
...
69 lines
1.5 KiB
Plaintext
69 lines
1.5 KiB
Plaintext
# SPDX-License-Identifier: GPL-2.0-only
|
|
#
|
|
# QE Communication options
|
|
#
|
|
|
|
config QUICC_ENGINE
|
|
bool "QUICC Engine (QE) framework support"
|
|
depends on OF && HAS_IOMEM
|
|
depends on PPC || ARM || ARM64 || COMPILE_TEST
|
|
select GENERIC_ALLOCATOR
|
|
select CRC32
|
|
help
|
|
The QUICC Engine (QE) is a new generation of communications
|
|
coprocessors on Freescale embedded CPUs (akin to CPM in older chips).
|
|
Selecting this option means that you wish to build a kernel
|
|
for a machine with a QE coprocessor.
|
|
|
|
config UCC_SLOW
|
|
bool
|
|
default y if SERIAL_QE
|
|
help
|
|
This option provides qe_lib support to UCC slow
|
|
protocols: UART, BISYNC, QMC
|
|
|
|
config UCC_FAST
|
|
bool
|
|
default y if UCC_GETH || QE_TDM
|
|
help
|
|
This option provides qe_lib support to UCC fast
|
|
protocols: HDLC, Ethernet, ATM, transparent
|
|
|
|
config UCC
|
|
bool
|
|
default y if UCC_FAST || UCC_SLOW
|
|
|
|
config CPM_TSA
|
|
tristate "CPM TSA support"
|
|
depends on OF && HAS_IOMEM
|
|
depends on CPM1 || (CPM && COMPILE_TEST)
|
|
help
|
|
Freescale CPM Time Slot Assigner (TSA)
|
|
controller.
|
|
|
|
This option enables support for this
|
|
controller
|
|
|
|
config CPM_QMC
|
|
tristate "CPM QMC support"
|
|
depends on OF && HAS_IOMEM
|
|
depends on CPM1 || (FSL_SOC && CPM && COMPILE_TEST)
|
|
depends on CPM_TSA
|
|
help
|
|
Freescale CPM QUICC Multichannel Controller
|
|
(QMC)
|
|
|
|
This option enables support for this
|
|
controller
|
|
|
|
config QE_TDM
|
|
bool
|
|
default y if FSL_UCC_HDLC
|
|
|
|
config QE_USB
|
|
bool
|
|
depends on QUICC_ENGINE
|
|
default y if USB_FSL_QE
|
|
help
|
|
QE USB Controller support
|