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ac41ac81e3
Add a schema validator to nxp,sja1105.yaml and to dsa.yaml for explicit MAC-level RGMII delays. These properties must be per port and must be present only for a phy-mode that represents RGMII. We tell dsa.yaml that these port properties might be present, we also define their valid values for SJA1105. We create a common definition for the RX and TX valid range, since it's quite a mouthful. We also modify the example to include the explicit RGMII delay properties. On the fixed-link ports (in the example, port 4), having these explicit delays is actually mandatory, since with the new behavior, the driver shouts that it is interpreting what delays to apply based on phy-mode. Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com> Reviewed-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net>
176 lines
5.3 KiB
YAML
176 lines
5.3 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/net/dsa/nxp,sja1105.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: NXP SJA1105 Automotive Ethernet Switch Family Device Tree Bindings
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description:
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The SJA1105 SPI interface requires a CS-to-CLK time (t2 in UM10944.pdf) of at
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least one half of t_CLK. At an SPI frequency of 1MHz, this means a minimum
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cs_sck_delay of 500ns. Ensuring that this SPI timing requirement is observed
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depends on the SPI bus master driver.
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allOf:
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- $ref: "dsa.yaml#"
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maintainers:
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- Vladimir Oltean <vladimir.oltean@nxp.com>
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properties:
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compatible:
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enum:
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- nxp,sja1105e
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- nxp,sja1105t
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- nxp,sja1105p
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- nxp,sja1105q
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- nxp,sja1105r
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- nxp,sja1105s
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- nxp,sja1110a
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- nxp,sja1110b
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- nxp,sja1110c
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- nxp,sja1110d
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reg:
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maxItems: 1
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# Optional container node for the 2 internal MDIO buses of the SJA1110
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# (one for the internal 100base-T1 PHYs and the other for the single
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# 100base-TX PHY). The "reg" property does not have physical significance.
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# The PHY addresses to port correspondence is as follows: for 100base-T1,
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# port 5 has PHY 1, port 6 has PHY 2 etc, while for 100base-TX, port 1 has
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# PHY 1.
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mdios:
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type: object
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properties:
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'#address-cells':
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const: 1
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'#size-cells':
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const: 0
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patternProperties:
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"^mdio@[0-1]$":
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type: object
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allOf:
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- $ref: "http://devicetree.org/schemas/net/mdio.yaml#"
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properties:
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compatible:
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oneOf:
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- enum:
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- nxp,sja1110-base-t1-mdio
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- nxp,sja1110-base-tx-mdio
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reg:
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oneOf:
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- enum:
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- 0
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- 1
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required:
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- compatible
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- reg
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patternProperties:
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"^(ethernet-)?ports$":
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patternProperties:
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"^(ethernet-)?port@[0-9]+$":
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allOf:
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- if:
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properties:
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phy-mode:
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contains:
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enum:
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- rgmii
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- rgmii-rxid
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- rgmii-txid
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- rgmii-id
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then:
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properties:
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rx-internal-delay-ps:
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$ref: "#/$defs/internal-delay-ps"
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tx-internal-delay-ps:
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$ref: "#/$defs/internal-delay-ps"
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required:
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- compatible
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- reg
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$defs:
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internal-delay-ps:
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description:
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Disable tunable delay lines using 0 ps, or enable them and select
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the phase between 1640 ps (73.8 degree shift at 1Gbps) and 2260 ps
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(101.7 degree shift) in increments of 0.9 degrees (20 ps).
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enum:
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[0, 1640, 1660, 1680, 1700, 1720, 1740, 1760, 1780, 1800, 1820, 1840,
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1860, 1880, 1900, 1920, 1940, 1960, 1980, 2000, 2020, 2040, 2060, 2080,
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2100, 2120, 2140, 2160, 2180, 2200, 2220, 2240, 2260]
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unevaluatedProperties: false
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examples:
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- |
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spi {
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#address-cells = <1>;
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#size-cells = <0>;
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ethernet-switch@1 {
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reg = <0x1>;
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compatible = "nxp,sja1105t";
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ethernet-ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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phy-handle = <&rgmii_phy6>;
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phy-mode = "rgmii-id";
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rx-internal-delay-ps = <0>;
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tx-internal-delay-ps = <0>;
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reg = <0>;
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};
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port@1 {
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phy-handle = <&rgmii_phy3>;
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phy-mode = "rgmii-id";
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rx-internal-delay-ps = <0>;
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tx-internal-delay-ps = <0>;
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reg = <1>;
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};
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port@2 {
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phy-handle = <&rgmii_phy4>;
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phy-mode = "rgmii-id";
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rx-internal-delay-ps = <0>;
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tx-internal-delay-ps = <0>;
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reg = <2>;
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};
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port@3 {
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phy-handle = <&rgmii_phy4>;
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phy-mode = "rgmii-id";
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rx-internal-delay-ps = <0>;
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tx-internal-delay-ps = <0>;
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reg = <3>;
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};
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port@4 {
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ethernet = <&enet2>;
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phy-mode = "rgmii";
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rx-internal-delay-ps = <0>;
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tx-internal-delay-ps = <0>;
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reg = <4>;
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fixed-link {
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speed = <1000>;
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full-duplex;
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};
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};
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};
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};
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};
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