mirror of
https://github.com/torvalds/linux.git
synced 2026-05-04 06:22:40 -04:00
All QAT GEN2 devices share the same register offset for masking interrupts, so they don't need any complex device specific infrastructure. Remove this function in favor of a constant in order to simplify the code. Also, future generations may require a more complex device specific handling, making the current approach obsolete anyway. Signed-off-by: Marco Chiappero <marco.chiappero@intel.com> Co-developed-by: Giovanni Cabiddu <giovanni.cabiddu@intel.com> Signed-off-by: Giovanni Cabiddu <giovanni.cabiddu@intel.com> Reviewed-by: Fiona Trahe <fiona.trahe@intel.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
20 lines
691 B
C
20 lines
691 B
C
/* SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0-only) */
|
|
/* Copyright(c) 2015 - 2020 Intel Corporation */
|
|
#ifndef ADF_C62XVF_HW_DATA_H_
|
|
#define ADF_C62XVF_HW_DATA_H_
|
|
|
|
#define ADF_C62XIOV_PMISC_BAR 1
|
|
#define ADF_C62XIOV_ACCELERATORS_MASK 0x1
|
|
#define ADF_C62XIOV_ACCELENGINES_MASK 0x1
|
|
#define ADF_C62XIOV_MAX_ACCELERATORS 1
|
|
#define ADF_C62XIOV_MAX_ACCELENGINES 1
|
|
#define ADF_C62XIOV_RX_RINGS_OFFSET 8
|
|
#define ADF_C62XIOV_TX_RINGS_MASK 0xFF
|
|
#define ADF_C62XIOV_ETR_BAR 0
|
|
#define ADF_C62XIOV_ETR_MAX_BANKS 1
|
|
#define ADF_C62XIOV_PF2VF_OFFSET 0x200
|
|
|
|
void adf_init_hw_data_c62xiov(struct adf_hw_device_data *hw_data);
|
|
void adf_clean_hw_data_c62xiov(struct adf_hw_device_data *hw_data);
|
|
#endif
|