mirror of
https://github.com/torvalds/linux.git
synced 2026-04-18 23:03:57 -04:00
208eed95fc
Pull SoC driver updates from Arnd Bergmann:
"This is the first half of the driver changes:
- A treewide interface change to the "syscore" operations for power
management, as a preparation for future Tegra specific changes
- Reset controller updates with added drivers for LAN969x, eic770 and
RZ/G3S SoCs
- Protection of system controller registers on Renesas and Google
SoCs, to prevent trivially triggering a system crash from e.g.
debugfs access
- soc_device identification updates on Nvidia, Exynos and Mediatek
- debugfs support in the ST STM32 firewall driver
- Minor updates for SoC drivers on AMD/Xilinx, Renesas, Allwinner, TI
- Cleanups for memory controller support on Nvidia and Renesas"
* tag 'soc-drivers-6.19' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (114 commits)
memory: tegra186-emc: Fix missing put_bpmp
Documentation: reset: Remove reset_controller_add_lookup()
reset: fix BIT macro reference
reset: rzg2l-usbphy-ctrl: Fix a NULL vs IS_ERR() bug in probe
reset: th1520: Support reset controllers in more subsystems
reset: th1520: Prepare for supporting multiple controllers
dt-bindings: reset: thead,th1520-reset: Add controllers for more subsys
dt-bindings: reset: thead,th1520-reset: Remove non-VO-subsystem resets
reset: remove legacy reset lookup code
clk: davinci: psc: drop unused reset lookup
reset: rzg2l-usbphy-ctrl: Add support for RZ/G3S SoC
reset: rzg2l-usbphy-ctrl: Add support for USB PWRRDY
dt-bindings: reset: renesas,rzg2l-usbphy-ctrl: Document RZ/G3S support
reset: eswin: Add eic7700 reset driver
dt-bindings: reset: eswin: Documentation for eic7700 SoC
reset: sparx5: add LAN969x support
dt-bindings: reset: microchip: Add LAN969x support
soc: rockchip: grf: Add select correct PWM implementation on RK3368
soc/tegra: pmc: Add USB wake events for Tegra234
amba: tegra-ahb: Fix device leak on SMMU enable
...
318 lines
10 KiB
C
318 lines
10 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
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*/
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#include <linux/debugfs.h>
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#include <linux/io.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/platform_device.h>
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#include <linux/soc/qcom/ubwc.h>
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static const struct qcom_ubwc_cfg_data no_ubwc_data = {
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/* no UBWC, no HBB */
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};
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static const struct qcom_ubwc_cfg_data kaanapali_data = {
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.ubwc_enc_version = UBWC_6_0,
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.ubwc_dec_version = UBWC_6_0,
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.ubwc_swizzle = UBWC_SWIZZLE_ENABLE_LVL2 |
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UBWC_SWIZZLE_ENABLE_LVL3,
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.ubwc_bank_spread = true,
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.highest_bank_bit = 16,
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.macrotile_mode = true,
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};
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static const struct qcom_ubwc_cfg_data msm8937_data = {
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.ubwc_enc_version = UBWC_1_0,
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.ubwc_dec_version = UBWC_1_0,
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.ubwc_swizzle = UBWC_SWIZZLE_ENABLE_LVL1 |
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UBWC_SWIZZLE_ENABLE_LVL2 |
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UBWC_SWIZZLE_ENABLE_LVL3,
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.highest_bank_bit = 14,
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};
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static const struct qcom_ubwc_cfg_data msm8998_data = {
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.ubwc_enc_version = UBWC_1_0,
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.ubwc_dec_version = UBWC_1_0,
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.ubwc_swizzle = UBWC_SWIZZLE_ENABLE_LVL1 |
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UBWC_SWIZZLE_ENABLE_LVL2 |
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UBWC_SWIZZLE_ENABLE_LVL3,
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.highest_bank_bit = 15,
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};
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static const struct qcom_ubwc_cfg_data qcm2290_data = {
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/* no UBWC */
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.highest_bank_bit = 15,
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};
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static const struct qcom_ubwc_cfg_data sa8775p_data = {
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.ubwc_enc_version = UBWC_4_0,
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.ubwc_dec_version = UBWC_4_0,
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.ubwc_swizzle = UBWC_SWIZZLE_ENABLE_LVL3,
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.ubwc_bank_spread = true,
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.highest_bank_bit = 13,
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.macrotile_mode = true,
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};
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static const struct qcom_ubwc_cfg_data sar2130p_data = {
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.ubwc_enc_version = UBWC_3_0, /* 4.0.2 in hw */
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.ubwc_dec_version = UBWC_4_3,
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.ubwc_swizzle = UBWC_SWIZZLE_ENABLE_LVL2 |
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UBWC_SWIZZLE_ENABLE_LVL3,
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.ubwc_bank_spread = true,
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.highest_bank_bit = 13,
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.macrotile_mode = true,
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};
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static const struct qcom_ubwc_cfg_data sc7180_data = {
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.ubwc_enc_version = UBWC_2_0,
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.ubwc_dec_version = UBWC_2_0,
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.ubwc_swizzle = UBWC_SWIZZLE_ENABLE_LVL2 |
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UBWC_SWIZZLE_ENABLE_LVL3,
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.ubwc_bank_spread = true,
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.highest_bank_bit = 14,
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};
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static const struct qcom_ubwc_cfg_data sc7280_data = {
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.ubwc_enc_version = UBWC_3_0,
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.ubwc_dec_version = UBWC_4_0,
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.ubwc_swizzle = UBWC_SWIZZLE_ENABLE_LVL2 |
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UBWC_SWIZZLE_ENABLE_LVL3,
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.ubwc_bank_spread = true,
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.highest_bank_bit = 14,
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.macrotile_mode = true,
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};
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static const struct qcom_ubwc_cfg_data sc8180x_data = {
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.ubwc_enc_version = UBWC_3_0,
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.ubwc_dec_version = UBWC_3_0,
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.ubwc_swizzle = UBWC_SWIZZLE_ENABLE_LVL2 |
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UBWC_SWIZZLE_ENABLE_LVL3,
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.highest_bank_bit = 16,
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.macrotile_mode = true,
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};
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static const struct qcom_ubwc_cfg_data sc8280xp_data = {
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.ubwc_enc_version = UBWC_4_0,
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.ubwc_dec_version = UBWC_4_0,
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.ubwc_swizzle = UBWC_SWIZZLE_ENABLE_LVL2 |
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UBWC_SWIZZLE_ENABLE_LVL3,
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.ubwc_bank_spread = true,
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.highest_bank_bit = 16,
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.macrotile_mode = true,
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};
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static const struct qcom_ubwc_cfg_data sdm670_data = {
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.ubwc_enc_version = UBWC_2_0,
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.ubwc_dec_version = UBWC_2_0,
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.ubwc_swizzle = UBWC_SWIZZLE_ENABLE_LVL2 |
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UBWC_SWIZZLE_ENABLE_LVL3,
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.highest_bank_bit = 14,
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};
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static const struct qcom_ubwc_cfg_data sdm845_data = {
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.ubwc_enc_version = UBWC_2_0,
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.ubwc_dec_version = UBWC_2_0,
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.ubwc_swizzle = UBWC_SWIZZLE_ENABLE_LVL2 |
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UBWC_SWIZZLE_ENABLE_LVL3,
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.highest_bank_bit = 15,
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};
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static const struct qcom_ubwc_cfg_data sm6115_data = {
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.ubwc_enc_version = UBWC_1_0,
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.ubwc_dec_version = UBWC_2_0,
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.ubwc_swizzle = UBWC_SWIZZLE_ENABLE_LVL1 |
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UBWC_SWIZZLE_ENABLE_LVL2 |
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UBWC_SWIZZLE_ENABLE_LVL3,
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.ubwc_bank_spread = true,
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.highest_bank_bit = 14,
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};
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static const struct qcom_ubwc_cfg_data sm6125_data = {
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.ubwc_enc_version = UBWC_1_0,
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.ubwc_dec_version = UBWC_3_0,
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.ubwc_swizzle = UBWC_SWIZZLE_ENABLE_LVL1 |
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UBWC_SWIZZLE_ENABLE_LVL2 |
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UBWC_SWIZZLE_ENABLE_LVL3,
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.highest_bank_bit = 14,
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};
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static const struct qcom_ubwc_cfg_data sm6150_data = {
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.ubwc_enc_version = UBWC_2_0,
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.ubwc_dec_version = UBWC_2_0,
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.ubwc_swizzle = UBWC_SWIZZLE_ENABLE_LVL2 |
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UBWC_SWIZZLE_ENABLE_LVL3,
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.highest_bank_bit = 14,
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};
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static const struct qcom_ubwc_cfg_data sm6350_data = {
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.ubwc_enc_version = UBWC_2_0,
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.ubwc_dec_version = UBWC_2_0,
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.ubwc_swizzle = UBWC_SWIZZLE_ENABLE_LVL2 |
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UBWC_SWIZZLE_ENABLE_LVL3,
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.ubwc_bank_spread = true,
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.highest_bank_bit = 14,
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};
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static const struct qcom_ubwc_cfg_data sm7150_data = {
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.ubwc_enc_version = UBWC_2_0,
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.ubwc_dec_version = UBWC_2_0,
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.ubwc_swizzle = UBWC_SWIZZLE_ENABLE_LVL2 |
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UBWC_SWIZZLE_ENABLE_LVL3,
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.highest_bank_bit = 14,
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};
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static const struct qcom_ubwc_cfg_data sm8150_data = {
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.ubwc_enc_version = UBWC_3_0,
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.ubwc_dec_version = UBWC_3_0,
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.ubwc_swizzle = UBWC_SWIZZLE_ENABLE_LVL2 |
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UBWC_SWIZZLE_ENABLE_LVL3,
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.highest_bank_bit = 15,
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};
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static const struct qcom_ubwc_cfg_data sm8250_data = {
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.ubwc_enc_version = UBWC_4_0,
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.ubwc_dec_version = UBWC_4_0,
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.ubwc_swizzle = UBWC_SWIZZLE_ENABLE_LVL2 |
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UBWC_SWIZZLE_ENABLE_LVL3,
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.ubwc_bank_spread = true,
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/* TODO: highest_bank_bit = 15 for LP_DDR4 */
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.highest_bank_bit = 16,
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.macrotile_mode = true,
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};
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static const struct qcom_ubwc_cfg_data sm8350_data = {
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.ubwc_enc_version = UBWC_4_0,
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.ubwc_dec_version = UBWC_4_0,
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.ubwc_swizzle = UBWC_SWIZZLE_ENABLE_LVL2 |
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UBWC_SWIZZLE_ENABLE_LVL3,
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.ubwc_bank_spread = true,
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/* TODO: highest_bank_bit = 15 for LP_DDR4 */
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.highest_bank_bit = 16,
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.macrotile_mode = true,
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};
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static const struct qcom_ubwc_cfg_data sm8550_data = {
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.ubwc_enc_version = UBWC_4_0,
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.ubwc_dec_version = UBWC_4_3,
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.ubwc_swizzle = UBWC_SWIZZLE_ENABLE_LVL2 |
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UBWC_SWIZZLE_ENABLE_LVL3,
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.ubwc_bank_spread = true,
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/* TODO: highest_bank_bit = 15 for LP_DDR4 */
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.highest_bank_bit = 16,
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.macrotile_mode = true,
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};
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static const struct qcom_ubwc_cfg_data sm8750_data = {
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.ubwc_enc_version = UBWC_5_0,
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.ubwc_dec_version = UBWC_5_0,
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.ubwc_swizzle = 6,
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.ubwc_bank_spread = true,
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/* TODO: highest_bank_bit = 15 for LP_DDR4 */
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.highest_bank_bit = 16,
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.macrotile_mode = true,
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};
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static const struct qcom_ubwc_cfg_data x1e80100_data = {
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.ubwc_enc_version = UBWC_4_0,
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.ubwc_dec_version = UBWC_4_3,
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.ubwc_swizzle = UBWC_SWIZZLE_ENABLE_LVL2 |
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UBWC_SWIZZLE_ENABLE_LVL3,
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.ubwc_bank_spread = true,
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/* TODO: highest_bank_bit = 15 for LP_DDR4 */
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.highest_bank_bit = 16,
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.macrotile_mode = true,
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};
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static const struct qcom_ubwc_cfg_data glymur_data = {
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.ubwc_enc_version = UBWC_5_0,
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.ubwc_dec_version = UBWC_5_0,
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.ubwc_swizzle = UBWC_SWIZZLE_ENABLE_LVL2 |
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UBWC_SWIZZLE_ENABLE_LVL3,
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.ubwc_bank_spread = true,
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/* TODO: highest_bank_bit = 15 for LP_DDR4 */
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.highest_bank_bit = 16,
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.macrotile_mode = true,
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};
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static const struct of_device_id qcom_ubwc_configs[] __maybe_unused = {
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{ .compatible = "qcom,apq8016", .data = &no_ubwc_data },
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{ .compatible = "qcom,apq8026", .data = &no_ubwc_data },
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{ .compatible = "qcom,apq8074", .data = &no_ubwc_data },
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{ .compatible = "qcom,apq8096", .data = &msm8998_data },
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{ .compatible = "qcom,kaanapali", .data = &kaanapali_data, },
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{ .compatible = "qcom,glymur", .data = &glymur_data},
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{ .compatible = "qcom,msm8226", .data = &no_ubwc_data },
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{ .compatible = "qcom,msm8916", .data = &no_ubwc_data },
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{ .compatible = "qcom,msm8917", .data = &no_ubwc_data },
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{ .compatible = "qcom,msm8937", .data = &msm8937_data },
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{ .compatible = "qcom,msm8929", .data = &no_ubwc_data },
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{ .compatible = "qcom,msm8939", .data = &no_ubwc_data },
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{ .compatible = "qcom,msm8953", .data = &msm8937_data },
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{ .compatible = "qcom,msm8956", .data = &no_ubwc_data },
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{ .compatible = "qcom,msm8974", .data = &no_ubwc_data },
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{ .compatible = "qcom,msm8976", .data = &no_ubwc_data },
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{ .compatible = "qcom,msm8996", .data = &msm8998_data },
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{ .compatible = "qcom,msm8998", .data = &msm8998_data },
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{ .compatible = "qcom,qcm2290", .data = &qcm2290_data, },
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{ .compatible = "qcom,qcm6490", .data = &sc7280_data, },
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{ .compatible = "qcom,qcs8300", .data = &sc8280xp_data, },
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{ .compatible = "qcom,sa8155p", .data = &sm8150_data, },
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{ .compatible = "qcom,sa8540p", .data = &sc8280xp_data, },
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{ .compatible = "qcom,sa8775p", .data = &sa8775p_data, },
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{ .compatible = "qcom,sar2130p", .data = &sar2130p_data },
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{ .compatible = "qcom,sc7180", .data = &sc7180_data },
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{ .compatible = "qcom,sc7280", .data = &sc7280_data, },
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{ .compatible = "qcom,sc8180x", .data = &sc8180x_data, },
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{ .compatible = "qcom,sc8280xp", .data = &sc8280xp_data, },
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{ .compatible = "qcom,sda660", .data = &msm8937_data },
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{ .compatible = "qcom,sdm450", .data = &msm8937_data },
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{ .compatible = "qcom,sdm630", .data = &msm8937_data },
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{ .compatible = "qcom,sdm632", .data = &msm8937_data },
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{ .compatible = "qcom,sdm636", .data = &msm8937_data },
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{ .compatible = "qcom,sdm660", .data = &msm8937_data },
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{ .compatible = "qcom,sdm670", .data = &sdm670_data, },
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{ .compatible = "qcom,sdm845", .data = &sdm845_data, },
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{ .compatible = "qcom,sm4250", .data = &sm6115_data, },
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{ .compatible = "qcom,sm6115", .data = &sm6115_data, },
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{ .compatible = "qcom,sm6125", .data = &sm6125_data, },
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{ .compatible = "qcom,sm6150", .data = &sm6150_data, },
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{ .compatible = "qcom,sm6350", .data = &sm6350_data, },
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{ .compatible = "qcom,sm6375", .data = &sm6350_data, },
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{ .compatible = "qcom,sm7125", .data = &sc7180_data },
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{ .compatible = "qcom,sm7150", .data = &sm7150_data, },
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{ .compatible = "qcom,sm7225", .data = &sm6350_data, },
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{ .compatible = "qcom,sm7325", .data = &sc7280_data, },
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{ .compatible = "qcom,sm8150", .data = &sm8150_data, },
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{ .compatible = "qcom,sm8250", .data = &sm8250_data, },
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{ .compatible = "qcom,sm8350", .data = &sm8350_data, },
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{ .compatible = "qcom,sm8450", .data = &sm8350_data, },
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{ .compatible = "qcom,sm8550", .data = &sm8550_data, },
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{ .compatible = "qcom,sm8650", .data = &sm8550_data, },
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{ .compatible = "qcom,sm8750", .data = &sm8750_data, },
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{ .compatible = "qcom,x1e80100", .data = &x1e80100_data, },
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{ .compatible = "qcom,x1p42100", .data = &x1e80100_data, },
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{ }
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};
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const struct qcom_ubwc_cfg_data *qcom_ubwc_config_get_data(void)
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{
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const struct qcom_ubwc_cfg_data *data;
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data = of_machine_get_match_data(qcom_ubwc_configs);
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if (!data) {
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pr_err("Couldn't find UBWC config data for this platform!\n");
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return ERR_PTR(-EINVAL);
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}
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return data;
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}
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EXPORT_SYMBOL_GPL(qcom_ubwc_config_get_data);
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MODULE_LICENSE("GPL");
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MODULE_DESCRIPTION("UBWC config database for QTI SoCs");
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