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The rk3576 controller is based on the same newer Synopsis IP as the one found in the rk3588. Its external setting bits in the GRF are different though, so it needs its own distinct compatible. Acked-by: "Rob Herring (Arm)" <robh@kernel.org> Signed-off-by: Heiko Stuebner <heiko@sntech.de> Link: https://lore.kernel.org/r/20250707164906.1445288-9-heiko@sntech.de
122 lines
2.5 KiB
YAML
122 lines
2.5 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/display/rockchip/rockchip,rk3588-mipi-dsi2.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Rockchip specific extensions to the Synopsys Designware MIPI DSI2
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maintainers:
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- Heiko Stuebner <heiko@sntech.de>
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properties:
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compatible:
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enum:
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- rockchip,rk3576-mipi-dsi2
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- rockchip,rk3588-mipi-dsi2
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reg:
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maxItems: 1
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interrupts:
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maxItems: 1
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clocks:
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maxItems: 2
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clock-names:
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items:
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- const: pclk
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- const: sys
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rockchip,grf:
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$ref: /schemas/types.yaml#/definitions/phandle
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description:
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This SoC uses GRF regs to switch between vopl/vopb.
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phys:
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maxItems: 1
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phy-names:
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const: dcphy
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power-domains:
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maxItems: 1
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resets:
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maxItems: 1
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reset-names:
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const: apb
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ports:
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$ref: /schemas/graph.yaml#/properties/ports
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properties:
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port@0:
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$ref: /schemas/graph.yaml#/properties/port
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description: Input node to receive pixel data.
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port@1:
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$ref: /schemas/graph.yaml#/properties/port
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description: DSI output node to panel.
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required:
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- port@0
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- port@1
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required:
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- compatible
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- clocks
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- clock-names
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- rockchip,grf
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- phys
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- phy-names
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- ports
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- reg
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allOf:
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- $ref: /schemas/display/dsi-controller.yaml#
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unevaluatedProperties: false
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examples:
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- |
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#include <dt-bindings/clock/rockchip,rk3588-cru.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/phy/phy.h>
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#include <dt-bindings/power/rk3588-power.h>
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#include <dt-bindings/reset/rockchip,rk3588-cru.h>
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soc {
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#address-cells = <2>;
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#size-cells = <2>;
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dsi@fde20000 {
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compatible = "rockchip,rk3588-mipi-dsi2";
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reg = <0x0 0xfde20000 0x0 0x10000>;
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interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH 0>;
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clocks = <&cru PCLK_DSIHOST0>, <&cru CLK_DSIHOST0>;
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clock-names = "pclk", "sys";
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resets = <&cru SRST_P_DSIHOST0>;
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reset-names = "apb";
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power-domains = <&power RK3588_PD_VOP>;
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phys = <&mipidcphy0 PHY_TYPE_DPHY>;
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phy-names = "dcphy";
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rockchip,grf = <&vop_grf>;
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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dsi0_in: port@0 {
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reg = <0>;
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};
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dsi0_out: port@1 {
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reg = <1>;
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};
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};
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};
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};
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