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4b44521c5d
The SiFive FU740 Power Reset Clock Interrupt Controller is a reset line
provider so add respective reset-cells property to fix:
arch/riscv/boot/dts/sifive/hifive-unmatched-a00.dt.yaml: clock-controller@10000000:
'#reset-cells' does not match any of the regexes: 'pinctrl-[0-9]+'
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
Link: https://lore.kernel.org/r/20210920144944.162431-1-krzysztof.kozlowski@canonical.com
Reviewed-by: Rob Herring <robh@kernel.org>
Acked-by: Palmer Dabbelt <palmerdabbelt@google.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
65 lines
1.5 KiB
YAML
65 lines
1.5 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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# Copyright (C) 2020 SiFive, Inc.
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/clock/sifive/fu740-prci.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: SiFive FU740 Power Reset Clock Interrupt Controller (PRCI)
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maintainers:
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- Zong Li <zong.li@sifive.com>
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- Paul Walmsley <paul.walmsley@sifive.com>
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description:
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On the FU740 family of SoCs, most system-wide clock and reset integration
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is via the PRCI IP block.
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The clock consumer should specify the desired clock via the clock ID
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macros defined in include/dt-bindings/clock/sifive-fu740-prci.h.
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These macros begin with PRCI_CLK_.
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The hfclk and rtcclk nodes are required, and represent physical
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crystals or resonators located on the PCB. These nodes should be present
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underneath /, rather than /soc.
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properties:
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compatible:
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const: sifive,fu740-c000-prci
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reg:
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maxItems: 1
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clocks:
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items:
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- description: high frequency clock.
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- description: RTL clock.
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clock-names:
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items:
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- const: hfclk
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- const: rtcclk
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"#clock-cells":
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const: 1
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"#reset-cells":
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const: 1
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required:
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- compatible
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- reg
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- clocks
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- "#clock-cells"
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additionalProperties: false
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examples:
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- |
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prci: clock-controller@10000000 {
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compatible = "sifive,fu740-c000-prci";
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reg = <0x10000000 0x1000>;
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clocks = <&hfclk>, <&rtcclk>;
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#clock-cells = <1>;
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#reset-cells = <1>;
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};
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