mirror of
https://github.com/torvalds/linux.git
synced 2026-04-19 23:34:00 -04:00
97dcd1ef76
Add a new compatible string to support MP25 SoC. On MP1 SoC, RNB signal (NAND controller signal) and NWAIT signal (PSRAM controller signal) have been integrated together in the SoC. That means that the NAND controller and the PSRAM controller (if the signal is used) can not be used at the same time. On MP25 SoC, the 2 signals can be used outside the SoC, so there is no more restrictions. MP1 SoC also embeds revision 1.1 of the FMC2 IP when MP25 SoC embeds revision 2.0 of the FMC2 IP. MP25 SoC is also using PSCI OS-initiated mode, so allow a single 'power-domains' entry for STM32 FMC2. As MP1 will move on PSCI OS-initiated mode, add this property as optional for all FMC2 variants. Signed-off-by: Christophe Kerello <christophe.kerello@foss.st.com> Link: https://lore.kernel.org/r/20240226101428.37791-2-christophe.kerello@foss.st.com Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
125 lines
3.3 KiB
YAML
125 lines
3.3 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
|
%YAML 1.2
|
|
---
|
|
$id: http://devicetree.org/schemas/memory-controllers/st,stm32-fmc2-ebi.yaml#
|
|
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
|
|
|
title: STMicroelectronics Flexible Memory Controller 2 (FMC2)
|
|
|
|
description: |
|
|
The FMC2 functional block makes the interface with: synchronous and
|
|
asynchronous static devices (such as PSNOR, PSRAM or other memory-mapped
|
|
peripherals) and NAND flash memories.
|
|
Its main purposes are:
|
|
- to translate AXI transactions into the appropriate external device
|
|
protocol
|
|
- to meet the access time requirements of the external devices
|
|
All external devices share the addresses, data and control signals with the
|
|
controller. Each external device is accessed by means of a unique Chip
|
|
Select. The FMC2 performs only one access at a time to an external device.
|
|
|
|
maintainers:
|
|
- Christophe Kerello <christophe.kerello@foss.st.com>
|
|
|
|
properties:
|
|
compatible:
|
|
enum:
|
|
- st,stm32mp1-fmc2-ebi
|
|
- st,stm32mp25-fmc2-ebi
|
|
|
|
reg:
|
|
maxItems: 1
|
|
|
|
clocks:
|
|
maxItems: 1
|
|
|
|
resets:
|
|
maxItems: 1
|
|
|
|
power-domains:
|
|
maxItems: 1
|
|
|
|
"#address-cells":
|
|
const: 2
|
|
|
|
"#size-cells":
|
|
const: 1
|
|
|
|
ranges:
|
|
description: |
|
|
Reflects the memory layout with four integer values per bank. Format:
|
|
<bank-number> 0 <address of the bank> <size>
|
|
|
|
patternProperties:
|
|
"^.*@[0-4],[a-f0-9]+$":
|
|
additionalProperties: true
|
|
type: object
|
|
$ref: mc-peripheral-props.yaml#
|
|
|
|
required:
|
|
- "#address-cells"
|
|
- "#size-cells"
|
|
- compatible
|
|
- reg
|
|
- clocks
|
|
- ranges
|
|
|
|
additionalProperties: false
|
|
|
|
examples:
|
|
- |
|
|
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
|
#include <dt-bindings/clock/stm32mp1-clks.h>
|
|
#include <dt-bindings/reset/stm32mp1-resets.h>
|
|
memory-controller@58002000 {
|
|
#address-cells = <2>;
|
|
#size-cells = <1>;
|
|
compatible = "st,stm32mp1-fmc2-ebi";
|
|
reg = <0x58002000 0x1000>;
|
|
clocks = <&rcc FMC_K>;
|
|
resets = <&rcc FMC_R>;
|
|
|
|
ranges = <0 0 0x60000000 0x04000000>, /* EBI CS 1 */
|
|
<1 0 0x64000000 0x04000000>, /* EBI CS 2 */
|
|
<2 0 0x68000000 0x04000000>, /* EBI CS 3 */
|
|
<3 0 0x6c000000 0x04000000>, /* EBI CS 4 */
|
|
<4 0 0x80000000 0x10000000>; /* NAND */
|
|
|
|
psram@0,0 {
|
|
compatible = "mtd-ram";
|
|
reg = <0 0x00000000 0x100000>;
|
|
bank-width = <2>;
|
|
|
|
st,fmc2-ebi-cs-transaction-type = <1>;
|
|
st,fmc2-ebi-cs-address-setup-ns = <60>;
|
|
st,fmc2-ebi-cs-data-setup-ns = <30>;
|
|
st,fmc2-ebi-cs-bus-turnaround-ns = <5>;
|
|
};
|
|
|
|
nand-controller@4,0 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
compatible = "st,stm32mp1-fmc2-nfc";
|
|
reg = <4 0x00000000 0x1000>,
|
|
<4 0x08010000 0x1000>,
|
|
<4 0x08020000 0x1000>,
|
|
<4 0x01000000 0x1000>,
|
|
<4 0x09010000 0x1000>,
|
|
<4 0x09020000 0x1000>;
|
|
interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
|
|
dmas = <&mdma1 20 0x2 0x12000a02 0x0 0x0>,
|
|
<&mdma1 20 0x2 0x12000a08 0x0 0x0>,
|
|
<&mdma1 21 0x2 0x12000a0a 0x0 0x0>;
|
|
dma-names = "tx", "rx", "ecc";
|
|
|
|
nand@0 {
|
|
reg = <0>;
|
|
nand-on-flash-bbt;
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
};
|
|
};
|
|
};
|
|
|
|
...
|