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fb7c3d8ba0
Allow the power-domains property to the PWM_DISP block as on some SoCs
this does need at most one power domain.
Fixes: b09b179bac ("dt-bindings: pwm: Convert pwm-mtk-disp.txt to mediatek,pwm-disp.yaml format")
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20240404081808.92199-1-angelogioacchino.delregno@collabora.com
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
81 lines
1.7 KiB
YAML
81 lines
1.7 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/pwm/mediatek,pwm-disp.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: MediaTek DISP_PWM Controller
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maintainers:
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- Jitao Shi <jitao.shi@mediatek.com>
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allOf:
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- $ref: pwm.yaml#
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properties:
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compatible:
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oneOf:
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- enum:
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- mediatek,mt2701-disp-pwm
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- mediatek,mt6595-disp-pwm
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- mediatek,mt8173-disp-pwm
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- mediatek,mt8183-disp-pwm
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- items:
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- enum:
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- mediatek,mt6795-disp-pwm
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- mediatek,mt8167-disp-pwm
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- const: mediatek,mt8173-disp-pwm
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- items:
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- enum:
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- mediatek,mt8186-disp-pwm
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- mediatek,mt8188-disp-pwm
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- mediatek,mt8192-disp-pwm
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- mediatek,mt8195-disp-pwm
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- const: mediatek,mt8183-disp-pwm
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reg:
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maxItems: 1
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"#pwm-cells":
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const: 2
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interrupts:
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maxItems: 1
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clocks:
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items:
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- description: Main Clock
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- description: Mm Clock
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clock-names:
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items:
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- const: main
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- const: mm
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power-domains:
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maxItems: 1
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required:
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- compatible
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- reg
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- "#pwm-cells"
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- clocks
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- clock-names
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/clock/mt8173-clk.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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pwm0: pwm@1401e000 {
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compatible = "mediatek,mt8173-disp-pwm";
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reg = <0x1401e000 0x1000>;
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#pwm-cells = <2>;
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clocks = <&mmsys CLK_MM_DISP_PWM026M>,
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<&mmsys CLK_MM_DISP_PWM0MM>;
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clock-names = "main", "mm";
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};
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