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Pull devicetree updates from Rob Herring:
"DT core:
- Add support for generating DT nodes for PCI devices. This is the
groundwork for applying overlays to PCI devices containing
non-discoverable downstream devices.
- DT unittest additions to check reverted changesets, to test for
refcount issues, and to test unresolved symbols. Also, various
clean-ups of the unittest along the way.
- Refactor node and property manipulation functions to better share
code with old API and changeset API
- Refactor changeset print functions to a common implementation
- Move some platform_device specific functions into of_platform.c
Bindings:
- Treewide fixing of typos
- Treewide clean-up of SPDX tags to use 'OR' consistently
- Last chunk of dropping unnecessary quotes. With that, the check for
unnecessary quotes is enabled in yamllint.
- Convert ftgmac100, zynqmp-genpd, pps-gpio, syna,rmi4, and qcom,ssbi
bindings to DT schema format
- Add Allwinner V3s xHCI USB, Saef SF-TC154B display, QCom SM8450
Inline Crypto Engine, QCom SM6115 UFS, QCom SDM670 PDC interrupt
controller, Arm 2022 Cortex cores, and QCom IPQ9574 Crypto bindings
- Fixes for Rockchip DWC PCI binding
- Ensure all properties are evaluated on USB connector schema
- Fix dt-check-compatible script to find of_device_id instances with
compiler annotations"
* tag 'devicetree-for-6.6' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux: (64 commits)
dt-bindings: usb: Add V3s compatible string for OHCI
dt-bindings: usb: Add V3s compatible string for EHCI
dt-bindings: display: panel: mipi-dbi-spi: add Saef SF-TC154B
dt-bindings: vendor-prefixes: document Saef Technology
dt-bindings: thermal: lmh: update maintainer address
of: unittest: Fix of_unittest_pci_node() kconfig dependencies
dt-bindings: crypto: ice: Document sm8450 inline crypto engine
dt-bindings: ufs: qcom: Add ICE to sm8450 example
dt-bindings: ufs: qcom: Add sm6115 binding
dt-bindings: ufs: qcom: Add reg-names property for ICE
dt-bindings: yamllint: Enable quoted string check
dt-bindings: Drop remaining unneeded quotes
of: unittest-data: Fix whitespace - angular brackets
of: unittest-data: Fix whitespace - indentation
of: unittest-data: Fix whitespace - blank lines
of: unittest-data: Convert remaining overlay DTS files to sugar syntax
of: overlay: unittest: Add test for unresolved symbol
of: unittest: Add separators to of_unittest_overlay_high_level()
of: unittest: Cleanup partially-applied overlays
of: unittest: Merge of_unittest_apply{,_revert}_overlay_check()
...
97 lines
2.9 KiB
YAML
97 lines
2.9 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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# Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/soc/ti/k3-ringacc.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Texas Instruments K3 NavigatorSS Ring Accelerator
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maintainers:
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- Santosh Shilimkar <ssantosh@kernel.org>
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- Grygorii Strashko <grygorii.strashko@ti.com>
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description: |
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The Ring Accelerator (RA) is a machine which converts read/write accesses
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from/to a constant address into corresponding read/write accesses from/to a
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circular data structure in memory. The RA eliminates the need for each DMA
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controller which needs to access ring elements from having to know the current
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state of the ring (base address, current offset). The DMA controller
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performs a read or write access to a specific address range (which maps to the
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source interface on the RA) and the RA replaces the address for the transaction
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with a new address which corresponds to the head or tail element of the ring
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(head for reads, tail for writes).
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The Ring Accelerator is a hardware module that is responsible for accelerating
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management of the packet queues. The K3 SoCs can have more than one RA instances
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allOf:
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- $ref: /schemas/arm/keystone/ti,k3-sci-common.yaml#
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properties:
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compatible:
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items:
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- const: ti,am654-navss-ringacc
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reg:
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minItems: 4
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items:
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- description: real time registers regions
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- description: fifos registers regions
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- description: proxy gcfg registers regions
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- description: proxy target registers regions
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- description: configuration registers region
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reg-names:
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minItems: 4
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items:
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- const: rt
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- const: fifos
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- const: proxy_gcfg
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- const: proxy_target
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- const: cfg
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msi-parent: true
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ti,num-rings:
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$ref: /schemas/types.yaml#/definitions/uint32
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description: Number of rings supported by RA
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ti,sci-rm-range-gp-rings:
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$ref: /schemas/types.yaml#/definitions/uint32
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description: TI-SCI RM subtype for GP ring range
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required:
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- compatible
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- reg
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- reg-names
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- msi-parent
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- ti,num-rings
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- ti,sci-rm-range-gp-rings
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- ti,sci
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- ti,sci-dev-id
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unevaluatedProperties: false
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examples:
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- |
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bus {
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#address-cells = <2>;
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#size-cells = <2>;
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ringacc: ringacc@3c000000 {
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compatible = "ti,am654-navss-ringacc";
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reg = <0x0 0x3c000000 0x0 0x400000>,
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<0x0 0x38000000 0x0 0x400000>,
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<0x0 0x31120000 0x0 0x100>,
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<0x0 0x33000000 0x0 0x40000>,
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<0x0 0x31080000 0x0 0x40000>;
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reg-names = "rt", "fifos", "proxy_gcfg", "proxy_target", "cfg";
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ti,num-rings = <818>;
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ti,sci-rm-range-gp-rings = <0x2>; /* GP ring range */
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ti,sci = <&dmsc>;
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ti,sci-dev-id = <187>;
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msi-parent = <&inta_main_udmass>;
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};
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};
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