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67327f1258
On t6002 (M1 Ultra), each die contains a self-contained GPU block.
However, only the coprocessor and global management circuitry of the
first die are used. This is what is represented by the "gpu" PS (the
one in die1 is disabled). Nonetheless, this shared component drives the
processing blocks in both dies, and therefore depends on the AFR fabric
being powered up on both dies.
Add an explicit dependency from the GPU block on die0 to AFR on die1,
next to the existing die0 AFR dependency.
Fixes: fa86294eb355 ("arm64: dts: apple: Add initial t6000/t6001/t6002 DTs")
Signed-off-by: Asahi Lina <lina@asahilina.net>
Reviewed-by: Janne Grunau <j@jannau.net>
Signed-off-by: Hector Martin <marcan@marcan.st>
302 lines
6.8 KiB
Plaintext
302 lines
6.8 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0+ OR MIT
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/*
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* Apple T6002 "M1 Ultra" SoC
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*
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* Other names: H13J, "Jade 2C"
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*
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* Copyright The Asahi Linux Contributors
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*/
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/interrupt-controller/apple-aic.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/pinctrl/apple.h>
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#include "multi-die-cpp.h"
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#include "t600x-common.dtsi"
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/ {
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compatible = "apple,t6002", "apple,arm-platform";
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#address-cells = <2>;
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#size-cells = <2>;
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cpus {
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cpu-map {
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cluster3 {
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core0 {
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cpu = <&cpu_e10>;
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};
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core1 {
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cpu = <&cpu_e11>;
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};
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};
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cluster4 {
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core0 {
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cpu = <&cpu_p20>;
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};
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core1 {
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cpu = <&cpu_p21>;
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};
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core2 {
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cpu = <&cpu_p22>;
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};
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core3 {
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cpu = <&cpu_p23>;
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};
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};
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cluster5 {
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core0 {
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cpu = <&cpu_p30>;
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};
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core1 {
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cpu = <&cpu_p31>;
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};
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core2 {
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cpu = <&cpu_p32>;
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};
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core3 {
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cpu = <&cpu_p33>;
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};
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};
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};
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cpu_e10: cpu@800 {
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compatible = "apple,icestorm";
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device_type = "cpu";
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reg = <0x0 0x800>;
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enable-method = "spin-table";
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cpu-release-addr = <0 0>; /* To be filled by loader */
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next-level-cache = <&l2_cache_3>;
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i-cache-size = <0x20000>;
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d-cache-size = <0x10000>;
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operating-points-v2 = <&icestorm_opp>;
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capacity-dmips-mhz = <714>;
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performance-domains = <&cpufreq_e_die1>;
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};
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cpu_e11: cpu@801 {
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compatible = "apple,icestorm";
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device_type = "cpu";
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reg = <0x0 0x801>;
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enable-method = "spin-table";
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cpu-release-addr = <0 0>; /* To be filled by loader */
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next-level-cache = <&l2_cache_3>;
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i-cache-size = <0x20000>;
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d-cache-size = <0x10000>;
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operating-points-v2 = <&icestorm_opp>;
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capacity-dmips-mhz = <714>;
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performance-domains = <&cpufreq_e_die1>;
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};
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cpu_p20: cpu@10900 {
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compatible = "apple,firestorm";
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device_type = "cpu";
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reg = <0x0 0x10900>;
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enable-method = "spin-table";
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cpu-release-addr = <0 0>; /* To be filled by loader */
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next-level-cache = <&l2_cache_4>;
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i-cache-size = <0x30000>;
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d-cache-size = <0x20000>;
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operating-points-v2 = <&firestorm_opp>;
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capacity-dmips-mhz = <1024>;
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performance-domains = <&cpufreq_p0_die1>;
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};
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cpu_p21: cpu@10901 {
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compatible = "apple,firestorm";
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device_type = "cpu";
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reg = <0x0 0x10901>;
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enable-method = "spin-table";
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cpu-release-addr = <0 0>; /* To be filled by loader */
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next-level-cache = <&l2_cache_4>;
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i-cache-size = <0x30000>;
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d-cache-size = <0x20000>;
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operating-points-v2 = <&firestorm_opp>;
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capacity-dmips-mhz = <1024>;
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performance-domains = <&cpufreq_p0_die1>;
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};
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cpu_p22: cpu@10902 {
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compatible = "apple,firestorm";
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device_type = "cpu";
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reg = <0x0 0x10902>;
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enable-method = "spin-table";
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cpu-release-addr = <0 0>; /* To be filled by loader */
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next-level-cache = <&l2_cache_4>;
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i-cache-size = <0x30000>;
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d-cache-size = <0x20000>;
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operating-points-v2 = <&firestorm_opp>;
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capacity-dmips-mhz = <1024>;
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performance-domains = <&cpufreq_p0_die1>;
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};
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cpu_p23: cpu@10903 {
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compatible = "apple,firestorm";
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device_type = "cpu";
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reg = <0x0 0x10903>;
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enable-method = "spin-table";
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cpu-release-addr = <0 0>; /* To be filled by loader */
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next-level-cache = <&l2_cache_4>;
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i-cache-size = <0x30000>;
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d-cache-size = <0x20000>;
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operating-points-v2 = <&firestorm_opp>;
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capacity-dmips-mhz = <1024>;
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performance-domains = <&cpufreq_p0_die1>;
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};
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cpu_p30: cpu@10a00 {
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compatible = "apple,firestorm";
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device_type = "cpu";
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reg = <0x0 0x10a00>;
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enable-method = "spin-table";
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cpu-release-addr = <0 0>; /* To be filled by loader */
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next-level-cache = <&l2_cache_5>;
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i-cache-size = <0x30000>;
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d-cache-size = <0x20000>;
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operating-points-v2 = <&firestorm_opp>;
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capacity-dmips-mhz = <1024>;
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performance-domains = <&cpufreq_p1_die1>;
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};
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cpu_p31: cpu@10a01 {
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compatible = "apple,firestorm";
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device_type = "cpu";
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reg = <0x0 0x10a01>;
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enable-method = "spin-table";
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cpu-release-addr = <0 0>; /* To be filled by loader */
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next-level-cache = <&l2_cache_5>;
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i-cache-size = <0x30000>;
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d-cache-size = <0x20000>;
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operating-points-v2 = <&firestorm_opp>;
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capacity-dmips-mhz = <1024>;
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performance-domains = <&cpufreq_p1_die1>;
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};
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cpu_p32: cpu@10a02 {
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compatible = "apple,firestorm";
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device_type = "cpu";
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reg = <0x0 0x10a02>;
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enable-method = "spin-table";
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cpu-release-addr = <0 0>; /* To be filled by loader */
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next-level-cache = <&l2_cache_5>;
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i-cache-size = <0x30000>;
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d-cache-size = <0x20000>;
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operating-points-v2 = <&firestorm_opp>;
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capacity-dmips-mhz = <1024>;
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performance-domains = <&cpufreq_p1_die1>;
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};
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cpu_p33: cpu@10a03 {
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compatible = "apple,firestorm";
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device_type = "cpu";
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reg = <0x0 0x10a03>;
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enable-method = "spin-table";
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cpu-release-addr = <0 0>; /* To be filled by loader */
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next-level-cache = <&l2_cache_5>;
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i-cache-size = <0x30000>;
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d-cache-size = <0x20000>;
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operating-points-v2 = <&firestorm_opp>;
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capacity-dmips-mhz = <1024>;
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performance-domains = <&cpufreq_p1_die1>;
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};
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l2_cache_3: l2-cache-3 {
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compatible = "cache";
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cache-level = <2>;
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cache-unified;
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cache-size = <0x400000>;
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};
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l2_cache_4: l2-cache-4 {
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compatible = "cache";
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cache-level = <2>;
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cache-unified;
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cache-size = <0xc00000>;
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};
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l2_cache_5: l2-cache-5 {
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compatible = "cache";
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cache-level = <2>;
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cache-unified;
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cache-size = <0xc00000>;
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};
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};
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die0: soc@200000000 {
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compatible = "simple-bus";
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#address-cells = <2>;
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#size-cells = <2>;
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ranges = <0x2 0x0 0x2 0x0 0x4 0x0>,
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<0x5 0x80000000 0x5 0x80000000 0x1 0x80000000>,
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<0x7 0x0 0x7 0x0 0xf 0x80000000>;
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nonposted-mmio;
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// filled via templated includes at the end of the file
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};
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die1: soc@2200000000 {
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compatible = "simple-bus";
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#address-cells = <2>;
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#size-cells = <2>;
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ranges = <0x2 0x0 0x22 0x0 0x4 0x0>,
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<0x7 0x0 0x27 0x0 0xf 0x80000000>;
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nonposted-mmio;
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// filled via templated includes at the end of the file
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};
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};
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#define DIE
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#define DIE_NO 0
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&die0 {
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#include "t600x-die0.dtsi"
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#include "t600x-dieX.dtsi"
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};
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#include "t600x-pmgr.dtsi"
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#include "t600x-gpio-pins.dtsi"
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#undef DIE
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#undef DIE_NO
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#define DIE _die1
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#define DIE_NO 1
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&die1 {
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#include "t600x-dieX.dtsi"
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#include "t600x-nvme.dtsi"
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};
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#include "t600x-pmgr.dtsi"
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#undef DIE
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#undef DIE_NO
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&aic {
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affinities {
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e-core-pmu-affinity {
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apple,fiq-index = <AIC_CPU_PMU_E>;
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cpus = <&cpu_e00 &cpu_e01
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&cpu_e10 &cpu_e11>;
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};
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p-core-pmu-affinity {
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apple,fiq-index = <AIC_CPU_PMU_P>;
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cpus = <&cpu_p00 &cpu_p01 &cpu_p02 &cpu_p03
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&cpu_p10 &cpu_p11 &cpu_p12 &cpu_p13
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&cpu_p20 &cpu_p21 &cpu_p22 &cpu_p23
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&cpu_p30 &cpu_p31 &cpu_p32 &cpu_p33>;
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};
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};
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};
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&ps_gfx {
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// On t6002, the die0 GPU power domain needs both AFR power domains
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power-domains = <&ps_afr>, <&ps_afr_die1>;
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};
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