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d32c1530c7
Add the missing CPU topology/capacity information and the cpufreq nodes, so we can have CPU frequency scaling and the scheduler has the information it needs to make the correct decisions. As with t8103, boost states are commented out pending PSCI/etc support for deep sleep states. Reviewed-by: Sven Peter <sven@svenpeter.dev> Signed-off-by: Hector Martin <marcan@marcan.st>
375 lines
8.4 KiB
Plaintext
375 lines
8.4 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0+ OR MIT
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/*
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* Common Apple T6000 / T6001 / T6002 "M1 Pro/Max/Ultra" SoC
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*
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* Other names: H13J, "Jade Chop", "Jade", "Jade 2C"
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*
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* Copyright The Asahi Linux Contributors
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*/
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/ {
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#address-cells = <2>;
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#size-cells = <2>;
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cpus {
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#address-cells = <2>;
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#size-cells = <0>;
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cpu-map {
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cluster0 {
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core0 {
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cpu = <&cpu_e00>;
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};
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core1 {
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cpu = <&cpu_e01>;
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};
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};
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cluster1 {
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core0 {
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cpu = <&cpu_p00>;
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};
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core1 {
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cpu = <&cpu_p01>;
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};
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core2 {
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cpu = <&cpu_p02>;
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};
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core3 {
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cpu = <&cpu_p03>;
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};
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};
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cluster2 {
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core0 {
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cpu = <&cpu_p10>;
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};
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core1 {
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cpu = <&cpu_p11>;
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};
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core2 {
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cpu = <&cpu_p12>;
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};
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core3 {
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cpu = <&cpu_p13>;
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};
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};
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};
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cpu_e00: cpu@0 {
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compatible = "apple,icestorm";
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device_type = "cpu";
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reg = <0x0 0x0>;
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enable-method = "spin-table";
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cpu-release-addr = <0 0>; /* To be filled by loader */
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next-level-cache = <&l2_cache_0>;
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i-cache-size = <0x20000>;
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d-cache-size = <0x10000>;
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operating-points-v2 = <&icestorm_opp>;
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capacity-dmips-mhz = <714>;
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performance-domains = <&cpufreq_e>;
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};
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cpu_e01: cpu@1 {
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compatible = "apple,icestorm";
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device_type = "cpu";
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reg = <0x0 0x1>;
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enable-method = "spin-table";
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cpu-release-addr = <0 0>; /* To be filled by loader */
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next-level-cache = <&l2_cache_0>;
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i-cache-size = <0x20000>;
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d-cache-size = <0x10000>;
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operating-points-v2 = <&icestorm_opp>;
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capacity-dmips-mhz = <714>;
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performance-domains = <&cpufreq_e>;
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};
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cpu_p00: cpu@10100 {
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compatible = "apple,firestorm";
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device_type = "cpu";
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reg = <0x0 0x10100>;
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enable-method = "spin-table";
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cpu-release-addr = <0 0>; /* To be filled by loader */
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next-level-cache = <&l2_cache_1>;
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i-cache-size = <0x30000>;
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d-cache-size = <0x20000>;
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operating-points-v2 = <&firestorm_opp>;
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capacity-dmips-mhz = <1024>;
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performance-domains = <&cpufreq_p0>;
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};
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cpu_p01: cpu@10101 {
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compatible = "apple,firestorm";
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device_type = "cpu";
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reg = <0x0 0x10101>;
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enable-method = "spin-table";
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cpu-release-addr = <0 0>; /* To be filled by loader */
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next-level-cache = <&l2_cache_1>;
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i-cache-size = <0x30000>;
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d-cache-size = <0x20000>;
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operating-points-v2 = <&firestorm_opp>;
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capacity-dmips-mhz = <1024>;
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performance-domains = <&cpufreq_p0>;
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};
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cpu_p02: cpu@10102 {
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compatible = "apple,firestorm";
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device_type = "cpu";
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reg = <0x0 0x10102>;
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enable-method = "spin-table";
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cpu-release-addr = <0 0>; /* To be filled by loader */
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next-level-cache = <&l2_cache_1>;
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i-cache-size = <0x30000>;
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d-cache-size = <0x20000>;
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operating-points-v2 = <&firestorm_opp>;
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capacity-dmips-mhz = <1024>;
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performance-domains = <&cpufreq_p0>;
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};
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cpu_p03: cpu@10103 {
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compatible = "apple,firestorm";
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device_type = "cpu";
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reg = <0x0 0x10103>;
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enable-method = "spin-table";
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cpu-release-addr = <0 0>; /* To be filled by loader */
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next-level-cache = <&l2_cache_1>;
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i-cache-size = <0x30000>;
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d-cache-size = <0x20000>;
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operating-points-v2 = <&firestorm_opp>;
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capacity-dmips-mhz = <1024>;
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performance-domains = <&cpufreq_p0>;
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};
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cpu_p10: cpu@10200 {
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compatible = "apple,firestorm";
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device_type = "cpu";
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reg = <0x0 0x10200>;
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enable-method = "spin-table";
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cpu-release-addr = <0 0>; /* To be filled by loader */
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next-level-cache = <&l2_cache_2>;
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i-cache-size = <0x30000>;
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d-cache-size = <0x20000>;
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operating-points-v2 = <&firestorm_opp>;
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capacity-dmips-mhz = <1024>;
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performance-domains = <&cpufreq_p1>;
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};
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cpu_p11: cpu@10201 {
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compatible = "apple,firestorm";
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device_type = "cpu";
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reg = <0x0 0x10201>;
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enable-method = "spin-table";
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cpu-release-addr = <0 0>; /* To be filled by loader */
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next-level-cache = <&l2_cache_2>;
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i-cache-size = <0x30000>;
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d-cache-size = <0x20000>;
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operating-points-v2 = <&firestorm_opp>;
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capacity-dmips-mhz = <1024>;
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performance-domains = <&cpufreq_p1>;
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};
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cpu_p12: cpu@10202 {
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compatible = "apple,firestorm";
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device_type = "cpu";
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reg = <0x0 0x10202>;
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enable-method = "spin-table";
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cpu-release-addr = <0 0>; /* To be filled by loader */
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next-level-cache = <&l2_cache_2>;
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i-cache-size = <0x30000>;
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d-cache-size = <0x20000>;
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operating-points-v2 = <&firestorm_opp>;
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capacity-dmips-mhz = <1024>;
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performance-domains = <&cpufreq_p1>;
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};
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cpu_p13: cpu@10203 {
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compatible = "apple,firestorm";
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device_type = "cpu";
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reg = <0x0 0x10203>;
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enable-method = "spin-table";
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cpu-release-addr = <0 0>; /* To be filled by loader */
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next-level-cache = <&l2_cache_2>;
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i-cache-size = <0x30000>;
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d-cache-size = <0x20000>;
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operating-points-v2 = <&firestorm_opp>;
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capacity-dmips-mhz = <1024>;
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performance-domains = <&cpufreq_p1>;
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};
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l2_cache_0: l2-cache-0 {
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compatible = "cache";
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cache-level = <2>;
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cache-unified;
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cache-size = <0x400000>;
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};
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l2_cache_1: l2-cache-1 {
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compatible = "cache";
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cache-level = <2>;
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cache-unified;
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cache-size = <0xc00000>;
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};
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l2_cache_2: l2-cache-2 {
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compatible = "cache";
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cache-level = <2>;
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cache-unified;
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cache-size = <0xc00000>;
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};
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};
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icestorm_opp: opp-table-0 {
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compatible = "operating-points-v2";
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opp01 {
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opp-hz = /bits/ 64 <600000000>;
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opp-level = <1>;
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clock-latency-ns = <7500>;
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};
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opp02 {
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opp-hz = /bits/ 64 <972000000>;
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opp-level = <2>;
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clock-latency-ns = <23000>;
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};
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opp03 {
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opp-hz = /bits/ 64 <1332000000>;
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opp-level = <3>;
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clock-latency-ns = <29000>;
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};
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opp04 {
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opp-hz = /bits/ 64 <1704000000>;
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opp-level = <4>;
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clock-latency-ns = <40000>;
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};
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opp05 {
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opp-hz = /bits/ 64 <2064000000>;
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opp-level = <5>;
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clock-latency-ns = <50000>;
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};
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};
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firestorm_opp: opp-table-1 {
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compatible = "operating-points-v2";
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opp01 {
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opp-hz = /bits/ 64 <600000000>;
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opp-level = <1>;
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clock-latency-ns = <8000>;
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};
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opp02 {
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opp-hz = /bits/ 64 <828000000>;
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opp-level = <2>;
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clock-latency-ns = <18000>;
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};
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opp03 {
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opp-hz = /bits/ 64 <1056000000>;
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opp-level = <3>;
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clock-latency-ns = <19000>;
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};
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opp04 {
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opp-hz = /bits/ 64 <1296000000>;
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opp-level = <4>;
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clock-latency-ns = <23000>;
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};
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opp05 {
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opp-hz = /bits/ 64 <1524000000>;
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opp-level = <5>;
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clock-latency-ns = <24000>;
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};
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opp06 {
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opp-hz = /bits/ 64 <1752000000>;
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opp-level = <6>;
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clock-latency-ns = <28000>;
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};
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opp07 {
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opp-hz = /bits/ 64 <1980000000>;
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opp-level = <7>;
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clock-latency-ns = <31000>;
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};
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opp08 {
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opp-hz = /bits/ 64 <2208000000>;
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opp-level = <8>;
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clock-latency-ns = <45000>;
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};
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opp09 {
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opp-hz = /bits/ 64 <2448000000>;
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opp-level = <9>;
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clock-latency-ns = <49000>;
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};
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opp10 {
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opp-hz = /bits/ 64 <2676000000>;
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opp-level = <10>;
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clock-latency-ns = <53000>;
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};
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opp11 {
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opp-hz = /bits/ 64 <2904000000>;
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opp-level = <11>;
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clock-latency-ns = <56000>;
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};
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opp12 {
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opp-hz = /bits/ 64 <3036000000>;
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opp-level = <12>;
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clock-latency-ns = <56000>;
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};
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/* Not available until CPU deep sleep is implemented
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opp13 {
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opp-hz = /bits/ 64 <3132000000>;
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opp-level = <13>;
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clock-latency-ns = <56000>;
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turbo-mode;
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};
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opp14 {
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opp-hz = /bits/ 64 <3168000000>;
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opp-level = <14>;
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clock-latency-ns = <56000>;
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turbo-mode;
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};
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opp15 {
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opp-hz = /bits/ 64 <3228000000>;
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opp-level = <15>;
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clock-latency-ns = <56000>;
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turbo-mode;
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};
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*/
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};
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pmu-e {
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compatible = "apple,icestorm-pmu";
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interrupt-parent = <&aic>;
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interrupts = <AIC_FIQ 0 AIC_CPU_PMU_E IRQ_TYPE_LEVEL_HIGH>;
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};
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pmu-p {
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compatible = "apple,firestorm-pmu";
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interrupt-parent = <&aic>;
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interrupts = <AIC_FIQ 0 AIC_CPU_PMU_P IRQ_TYPE_LEVEL_HIGH>;
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};
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timer {
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compatible = "arm,armv8-timer";
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interrupt-parent = <&aic>;
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interrupt-names = "phys", "virt", "hyp-phys", "hyp-virt";
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interrupts = <AIC_FIQ 0 AIC_TMR_GUEST_PHYS IRQ_TYPE_LEVEL_HIGH>,
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<AIC_FIQ 0 AIC_TMR_GUEST_VIRT IRQ_TYPE_LEVEL_HIGH>,
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<AIC_FIQ 0 AIC_TMR_HV_PHYS IRQ_TYPE_LEVEL_HIGH>,
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<AIC_FIQ 0 AIC_TMR_HV_VIRT IRQ_TYPE_LEVEL_HIGH>;
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};
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clkref: clock-ref {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <24000000>;
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clock-output-names = "clkref";
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};
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/*
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* This is a fabulated representation of the input clock
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* to NCO since we don't know the true clock tree.
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*/
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nco_clkref: clock-ref-nco {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-output-names = "nco_ref";
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};
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};
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