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https://github.com/torvalds/linux.git
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e65e175b07
Now that we have a subsystem for compute accelerators, move the habanalabs driver to it. This patch only moves the files and fixes the Makefiles. Future patches will change the existing code to register to the accel subsystem and expose the accel device char files instead of the habanalabs device char files. Update the MAINTAINERS file to reflect this change. Signed-off-by: Oded Gabbay <ogabbay@kernel.org>
4975 lines
296 KiB
C
4975 lines
296 KiB
C
/* SPDX-License-Identifier: GPL-2.0
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*
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* Copyright 2016-2018 HabanaLabs, Ltd.
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* All Rights Reserved.
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*
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*/
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/************************************
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** This is an auto-generated file **
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** DO NOT EDIT BELOW **
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************************************/
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#ifndef GAUDI_BLOCKS_H_
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#define GAUDI_BLOCKS_H_
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#define mmNIC0_PHY0_BASE 0x0ull
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#define NIC0_PHY0_MAX_OFFSET 0x9F13
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#define mmMME0_ACC_BASE 0x7FFC020000ull
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#define MME0_ACC_MAX_OFFSET 0x5C00
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#define MME0_ACC_SECTION 0x20000
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#define mmMME0_SBAB_BASE 0x7FFC040000ull
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#define MME0_SBAB_MAX_OFFSET 0x5800
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#define MME0_SBAB_SECTION 0x1000
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#define mmMME0_PRTN_BASE 0x7FFC041000ull
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#define MME0_PRTN_MAX_OFFSET 0x5000
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#define MME0_PRTN_SECTION 0x1F000
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#define mmMME0_CTRL_BASE 0x7FFC060000ull
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#define MME0_CTRL_MAX_OFFSET 0xDA80
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#define MME0_CTRL_SECTION 0x8000
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#define mmARCH_MME0_CTRL_BASE 0x7FFC060008ull
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#define ARCH_MME0_CTRL_MAX_OFFSET 0x3400
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#define ARCH_MME0_CTRL_SECTION 0x3400
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#define mmARCH_TENSOR_S_MME0_CTRL_BASE 0x7FFC06003Cull
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#define ARCH_TENSOR_S_MME0_CTRL_MAX_OFFSET 0x4C00
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#define ARCH_TENSOR_S_MME0_CTRL_SECTION 0x4C00
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#define mmARCH_AGU_S_MME0_CTRL_BASE 0x7FFC060088ull
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#define ARCH_AGU_S_MME0_CTRL_MAX_OFFSET 0x2400
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#define ARCH_AGU_S_MME0_CTRL_SECTION 0x2400
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#define mmARCH_TENSOR_L_MME0_CTRL_BASE 0x7FFC0600ACull
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#define ARCH_TENSOR_L_MME0_CTRL_MAX_OFFSET 0x4C00
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#define ARCH_TENSOR_L_MME0_CTRL_SECTION 0x4C00
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#define mmARCH_AGU_L_LOCAL_MME0_CTRL_BASE 0x7FFC0600F8ull
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#define ARCH_AGU_L_LOCAL_MME0_CTRL_MAX_OFFSET 0x2400
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#define ARCH_AGU_L_LOCAL_MME0_CTRL_SECTION 0x2400
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#define mmARCH_AGU_L_REMOTE_MME0_CTRL_BASE 0x7FFC06011Cull
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#define ARCH_AGU_L_REMOTE_MME0_CTRL_MAX_OFFSET 0x2400
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#define ARCH_AGU_L_REMOTE_MME0_CTRL_SECTION 0x2400
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#define mmARCH_TENSOR_O_MME0_CTRL_BASE 0x7FFC060140ull
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#define ARCH_TENSOR_O_MME0_CTRL_MAX_OFFSET 0x4C00
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#define ARCH_TENSOR_O_MME0_CTRL_SECTION 0x4C00
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#define mmARCH_AGU_O_LOCAL_MME0_CTRL_BASE 0x7FFC06018Cull
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#define ARCH_AGU_O_LOCAL_MME0_CTRL_MAX_OFFSET 0x2400
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#define ARCH_AGU_O_LOCAL_MME0_CTRL_SECTION 0x2400
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#define mmARCH_AGU_O_REMOTE_MME0_CTRL_BASE 0x7FFC0601B0ull
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#define ARCH_AGU_O_REMOTE_MME0_CTRL_MAX_OFFSET 0x2400
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#define ARCH_AGU_O_REMOTE_MME0_CTRL_SECTION 0x2400
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#define mmARCH_DESC_MME0_CTRL_BASE 0x7FFC0601D4ull
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#define ARCH_DESC_MME0_CTRL_MAX_OFFSET 0x5400
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#define ARCH_DESC_MME0_CTRL_SECTION 0x2340
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#define mmSHADOW_0_MME0_CTRL_BASE 0x7FFC060408ull
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#define SHADOW_0_MME0_CTRL_MAX_OFFSET 0x3400
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#define SHADOW_0_MME0_CTRL_SECTION 0x3400
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#define mmSHADOW_0_TENSOR_S_MME0_CTRL_BASE 0x7FFC06043Cull
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#define SHADOW_0_TENSOR_S_MME0_CTRL_MAX_OFFSET 0x4C00
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#define SHADOW_0_TENSOR_S_MME0_CTRL_SECTION 0x4C00
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#define mmSHADOW_0_AGU_S_MME0_CTRL_BASE 0x7FFC060488ull
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#define SHADOW_0_AGU_S_MME0_CTRL_MAX_OFFSET 0x2400
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#define SHADOW_0_AGU_S_MME0_CTRL_SECTION 0x2400
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#define mmSHADOW_0_TENSOR_L_MME0_CTRL_BASE 0x7FFC0604ACull
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#define SHADOW_0_TENSOR_L_MME0_CTRL_MAX_OFFSET 0x4C00
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#define SHADOW_0_TENSOR_L_MME0_CTRL_SECTION 0x4C00
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#define mmSHADOW_0_AGU_L_LOCAL_MME0_CTRL_BASE 0x7FFC0604F8ull
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#define SHADOW_0_AGU_L_LOCAL_MME0_CTRL_MAX_OFFSET 0x2400
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#define SHADOW_0_AGU_L_LOCAL_MME0_CTRL_SECTION 0x2400
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#define mmSHADOW_0_AGU_L_REMOTE_MME0_CTRL_BASE 0x7FFC06051Cull
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#define SHADOW_0_AGU_L_REMOTE_MME0_CTRL_MAX_OFFSET 0x2400
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#define SHADOW_0_AGU_L_REMOTE_MME0_CTRL_SECTION 0x2400
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#define mmSHADOW_0_TENSOR_O_MME0_CTRL_BASE 0x7FFC060540ull
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#define SHADOW_0_TENSOR_O_MME0_CTRL_MAX_OFFSET 0x4C00
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#define SHADOW_0_TENSOR_O_MME0_CTRL_SECTION 0x4C00
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#define mmSHADOW_0_AGU_O_LOCAL_MME0_CTRL_BASE 0x7FFC06058Cull
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#define SHADOW_0_AGU_O_LOCAL_MME0_CTRL_MAX_OFFSET 0x2400
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#define SHADOW_0_AGU_O_LOCAL_MME0_CTRL_SECTION 0x2400
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#define mmSHADOW_0_AGU_O_REMOTE_MME0_CTRL_BASE 0x7FFC0605B0ull
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#define SHADOW_0_AGU_O_REMOTE_MME0_CTRL_MAX_OFFSET 0x2400
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#define SHADOW_0_AGU_O_REMOTE_MME0_CTRL_SECTION 0x2400
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#define mmSHADOW_0_DESC_MME0_CTRL_BASE 0x7FFC0605D4ull
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#define SHADOW_0_DESC_MME0_CTRL_MAX_OFFSET 0x5400
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#define SHADOW_0_DESC_MME0_CTRL_SECTION 0xB400
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#define mmSHADOW_1_MME0_CTRL_BASE 0x7FFC060688ull
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#define SHADOW_1_MME0_CTRL_MAX_OFFSET 0x3400
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#define SHADOW_1_MME0_CTRL_SECTION 0x3400
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#define mmSHADOW_1_TENSOR_S_MME0_CTRL_BASE 0x7FFC0606BCull
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#define SHADOW_1_TENSOR_S_MME0_CTRL_MAX_OFFSET 0x4C00
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#define SHADOW_1_TENSOR_S_MME0_CTRL_SECTION 0x4C00
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#define mmSHADOW_1_AGU_S_MME0_CTRL_BASE 0x7FFC060708ull
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#define SHADOW_1_AGU_S_MME0_CTRL_MAX_OFFSET 0x2400
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#define SHADOW_1_AGU_S_MME0_CTRL_SECTION 0x2400
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#define mmSHADOW_1_TENSOR_L_MME0_CTRL_BASE 0x7FFC06072Cull
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#define SHADOW_1_TENSOR_L_MME0_CTRL_MAX_OFFSET 0x4C00
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#define SHADOW_1_TENSOR_L_MME0_CTRL_SECTION 0x4C00
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#define mmSHADOW_1_AGU_L_LOCAL_MME0_CTRL_BASE 0x7FFC060778ull
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#define SHADOW_1_AGU_L_LOCAL_MME0_CTRL_MAX_OFFSET 0x2400
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#define SHADOW_1_AGU_L_LOCAL_MME0_CTRL_SECTION 0x2400
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#define mmSHADOW_1_AGU_L_REMOTE_MME0_CTRL_BASE 0x7FFC06079Cull
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#define SHADOW_1_AGU_L_REMOTE_MME0_CTRL_MAX_OFFSET 0x2400
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#define SHADOW_1_AGU_L_REMOTE_MME0_CTRL_SECTION 0x2400
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#define mmSHADOW_1_TENSOR_O_MME0_CTRL_BASE 0x7FFC0607C0ull
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#define SHADOW_1_TENSOR_O_MME0_CTRL_MAX_OFFSET 0x4C00
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#define SHADOW_1_TENSOR_O_MME0_CTRL_SECTION 0x4C00
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#define mmSHADOW_1_AGU_O_LOCAL_MME0_CTRL_BASE 0x7FFC06080Cull
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#define SHADOW_1_AGU_O_LOCAL_MME0_CTRL_MAX_OFFSET 0x2400
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#define SHADOW_1_AGU_O_LOCAL_MME0_CTRL_SECTION 0x2400
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#define mmSHADOW_1_AGU_O_REMOTE_MME0_CTRL_BASE 0x7FFC060830ull
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#define SHADOW_1_AGU_O_REMOTE_MME0_CTRL_MAX_OFFSET 0x2400
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#define SHADOW_1_AGU_O_REMOTE_MME0_CTRL_SECTION 0x2400
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#define mmSHADOW_1_DESC_MME0_CTRL_BASE 0x7FFC060854ull
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#define SHADOW_1_DESC_MME0_CTRL_MAX_OFFSET 0x5400
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#define SHADOW_1_DESC_MME0_CTRL_SECTION 0xB400
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#define mmSHADOW_2_MME0_CTRL_BASE 0x7FFC060908ull
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#define SHADOW_2_MME0_CTRL_MAX_OFFSET 0x3400
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#define SHADOW_2_MME0_CTRL_SECTION 0x3400
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#define mmSHADOW_2_TENSOR_S_MME0_CTRL_BASE 0x7FFC06093Cull
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#define SHADOW_2_TENSOR_S_MME0_CTRL_MAX_OFFSET 0x4C00
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#define SHADOW_2_TENSOR_S_MME0_CTRL_SECTION 0x4C00
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#define mmSHADOW_2_AGU_S_MME0_CTRL_BASE 0x7FFC060988ull
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#define SHADOW_2_AGU_S_MME0_CTRL_MAX_OFFSET 0x2400
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#define SHADOW_2_AGU_S_MME0_CTRL_SECTION 0x2400
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#define mmSHADOW_2_TENSOR_L_MME0_CTRL_BASE 0x7FFC0609ACull
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#define SHADOW_2_TENSOR_L_MME0_CTRL_MAX_OFFSET 0x4C00
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#define SHADOW_2_TENSOR_L_MME0_CTRL_SECTION 0x4C00
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#define mmSHADOW_2_AGU_L_LOCAL_MME0_CTRL_BASE 0x7FFC0609F8ull
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#define SHADOW_2_AGU_L_LOCAL_MME0_CTRL_MAX_OFFSET 0x2400
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#define SHADOW_2_AGU_L_LOCAL_MME0_CTRL_SECTION 0x2400
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#define mmSHADOW_2_AGU_L_REMOTE_MME0_CTRL_BASE 0x7FFC060A1Cull
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#define SHADOW_2_AGU_L_REMOTE_MME0_CTRL_MAX_OFFSET 0x2400
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#define SHADOW_2_AGU_L_REMOTE_MME0_CTRL_SECTION 0x2400
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#define mmSHADOW_2_TENSOR_O_MME0_CTRL_BASE 0x7FFC060A40ull
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#define SHADOW_2_TENSOR_O_MME0_CTRL_MAX_OFFSET 0x4C00
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#define SHADOW_2_TENSOR_O_MME0_CTRL_SECTION 0x4C00
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#define mmSHADOW_2_AGU_O_LOCAL_MME0_CTRL_BASE 0x7FFC060A8Cull
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#define SHADOW_2_AGU_O_LOCAL_MME0_CTRL_MAX_OFFSET 0x2400
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#define SHADOW_2_AGU_O_LOCAL_MME0_CTRL_SECTION 0x2400
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#define mmSHADOW_2_AGU_O_REMOTE_MME0_CTRL_BASE 0x7FFC060AB0ull
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#define SHADOW_2_AGU_O_REMOTE_MME0_CTRL_MAX_OFFSET 0x2400
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#define SHADOW_2_AGU_O_REMOTE_MME0_CTRL_SECTION 0x2400
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#define mmSHADOW_2_DESC_MME0_CTRL_BASE 0x7FFC060AD4ull
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#define SHADOW_2_DESC_MME0_CTRL_MAX_OFFSET 0x5400
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#define SHADOW_2_DESC_MME0_CTRL_SECTION 0xB400
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#define mmSHADOW_3_MME0_CTRL_BASE 0x7FFC060B88ull
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#define SHADOW_3_MME0_CTRL_MAX_OFFSET 0x3400
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#define SHADOW_3_MME0_CTRL_SECTION 0x3400
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#define mmSHADOW_3_TENSOR_S_MME0_CTRL_BASE 0x7FFC060BBCull
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#define SHADOW_3_TENSOR_S_MME0_CTRL_MAX_OFFSET 0x4C00
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#define SHADOW_3_TENSOR_S_MME0_CTRL_SECTION 0x4C00
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#define mmSHADOW_3_AGU_S_MME0_CTRL_BASE 0x7FFC060C08ull
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#define SHADOW_3_AGU_S_MME0_CTRL_MAX_OFFSET 0x2400
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#define SHADOW_3_AGU_S_MME0_CTRL_SECTION 0x2400
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#define mmSHADOW_3_TENSOR_L_MME0_CTRL_BASE 0x7FFC060C2Cull
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#define SHADOW_3_TENSOR_L_MME0_CTRL_MAX_OFFSET 0x4C00
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#define SHADOW_3_TENSOR_L_MME0_CTRL_SECTION 0x4C00
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#define mmSHADOW_3_AGU_L_LOCAL_MME0_CTRL_BASE 0x7FFC060C78ull
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#define SHADOW_3_AGU_L_LOCAL_MME0_CTRL_MAX_OFFSET 0x2400
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#define SHADOW_3_AGU_L_LOCAL_MME0_CTRL_SECTION 0x2400
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#define mmSHADOW_3_AGU_L_REMOTE_MME0_CTRL_BASE 0x7FFC060C9Cull
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#define SHADOW_3_AGU_L_REMOTE_MME0_CTRL_MAX_OFFSET 0x2400
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#define SHADOW_3_AGU_L_REMOTE_MME0_CTRL_SECTION 0x2400
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#define mmSHADOW_3_TENSOR_O_MME0_CTRL_BASE 0x7FFC060CC0ull
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#define SHADOW_3_TENSOR_O_MME0_CTRL_MAX_OFFSET 0x4C00
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#define SHADOW_3_TENSOR_O_MME0_CTRL_SECTION 0x4C00
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#define mmSHADOW_3_AGU_O_LOCAL_MME0_CTRL_BASE 0x7FFC060D0Cull
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#define SHADOW_3_AGU_O_LOCAL_MME0_CTRL_MAX_OFFSET 0x2400
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#define SHADOW_3_AGU_O_LOCAL_MME0_CTRL_SECTION 0x2400
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#define mmSHADOW_3_AGU_O_REMOTE_MME0_CTRL_BASE 0x7FFC060D30ull
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#define SHADOW_3_AGU_O_REMOTE_MME0_CTRL_MAX_OFFSET 0x2400
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#define SHADOW_3_AGU_O_REMOTE_MME0_CTRL_SECTION 0x2400
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#define mmSHADOW_3_DESC_MME0_CTRL_BASE 0x7FFC060D54ull
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#define SHADOW_3_DESC_MME0_CTRL_MAX_OFFSET 0x5400
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#define SHADOW_3_DESC_MME0_CTRL_SECTION 0x72AC
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#define mmMME0_QM_BASE 0x7FFC068000ull
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#define MME0_QM_MAX_OFFSET 0xD040
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#define MME0_QM_SECTION 0x38000
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#define mmMME1_ACC_BASE 0x7FFC0A0000ull
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#define MME1_ACC_MAX_OFFSET 0x5C00
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#define MME1_ACC_SECTION 0x20000
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#define mmMME1_SBAB_BASE 0x7FFC0C0000ull
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#define MME1_SBAB_MAX_OFFSET 0x5800
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#define MME1_SBAB_SECTION 0x1000
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#define mmMME1_PRTN_BASE 0x7FFC0C1000ull
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#define MME1_PRTN_MAX_OFFSET 0x5000
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#define MME1_PRTN_SECTION 0x1F000
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#define mmMME1_CTRL_BASE 0x7FFC0E0000ull
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#define MME1_CTRL_MAX_OFFSET 0xDA80
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#define MME1_CTRL_SECTION 0x8000
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#define mmARCH_MME1_CTRL_BASE 0x7FFC0E0008ull
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#define ARCH_MME1_CTRL_MAX_OFFSET 0x3400
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#define ARCH_MME1_CTRL_SECTION 0x3400
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#define mmARCH_TENSOR_S_MME1_CTRL_BASE 0x7FFC0E003Cull
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#define ARCH_TENSOR_S_MME1_CTRL_MAX_OFFSET 0x4C00
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#define ARCH_TENSOR_S_MME1_CTRL_SECTION 0x4C00
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#define mmARCH_AGU_S_MME1_CTRL_BASE 0x7FFC0E0088ull
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#define ARCH_AGU_S_MME1_CTRL_MAX_OFFSET 0x2400
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#define ARCH_AGU_S_MME1_CTRL_SECTION 0x2400
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#define mmARCH_TENSOR_L_MME1_CTRL_BASE 0x7FFC0E00ACull
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#define ARCH_TENSOR_L_MME1_CTRL_MAX_OFFSET 0x4C00
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#define ARCH_TENSOR_L_MME1_CTRL_SECTION 0x4C00
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#define mmARCH_AGU_L_LOCAL_MME1_CTRL_BASE 0x7FFC0E00F8ull
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#define ARCH_AGU_L_LOCAL_MME1_CTRL_MAX_OFFSET 0x2400
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#define ARCH_AGU_L_LOCAL_MME1_CTRL_SECTION 0x2400
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#define mmARCH_AGU_L_REMOTE_MME1_CTRL_BASE 0x7FFC0E011Cull
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#define ARCH_AGU_L_REMOTE_MME1_CTRL_MAX_OFFSET 0x2400
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#define ARCH_AGU_L_REMOTE_MME1_CTRL_SECTION 0x2400
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#define mmARCH_TENSOR_O_MME1_CTRL_BASE 0x7FFC0E0140ull
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#define ARCH_TENSOR_O_MME1_CTRL_MAX_OFFSET 0x4C00
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#define ARCH_TENSOR_O_MME1_CTRL_SECTION 0x4C00
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#define mmARCH_AGU_O_LOCAL_MME1_CTRL_BASE 0x7FFC0E018Cull
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#define ARCH_AGU_O_LOCAL_MME1_CTRL_MAX_OFFSET 0x2400
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#define ARCH_AGU_O_LOCAL_MME1_CTRL_SECTION 0x2400
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#define mmARCH_AGU_O_REMOTE_MME1_CTRL_BASE 0x7FFC0E01B0ull
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#define ARCH_AGU_O_REMOTE_MME1_CTRL_MAX_OFFSET 0x2400
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#define ARCH_AGU_O_REMOTE_MME1_CTRL_SECTION 0x2400
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#define mmARCH_DESC_MME1_CTRL_BASE 0x7FFC0E01D4ull
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#define ARCH_DESC_MME1_CTRL_MAX_OFFSET 0x5400
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#define ARCH_DESC_MME1_CTRL_SECTION 0x2340
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#define mmSHADOW_0_MME1_CTRL_BASE 0x7FFC0E0408ull
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#define SHADOW_0_MME1_CTRL_MAX_OFFSET 0x3400
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#define SHADOW_0_MME1_CTRL_SECTION 0x3400
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#define mmSHADOW_0_TENSOR_S_MME1_CTRL_BASE 0x7FFC0E043Cull
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#define SHADOW_0_TENSOR_S_MME1_CTRL_MAX_OFFSET 0x4C00
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#define SHADOW_0_TENSOR_S_MME1_CTRL_SECTION 0x4C00
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#define mmSHADOW_0_AGU_S_MME1_CTRL_BASE 0x7FFC0E0488ull
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#define SHADOW_0_AGU_S_MME1_CTRL_MAX_OFFSET 0x2400
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#define SHADOW_0_AGU_S_MME1_CTRL_SECTION 0x2400
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#define mmSHADOW_0_TENSOR_L_MME1_CTRL_BASE 0x7FFC0E04ACull
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#define SHADOW_0_TENSOR_L_MME1_CTRL_MAX_OFFSET 0x4C00
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#define SHADOW_0_TENSOR_L_MME1_CTRL_SECTION 0x4C00
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#define mmSHADOW_0_AGU_L_LOCAL_MME1_CTRL_BASE 0x7FFC0E04F8ull
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#define SHADOW_0_AGU_L_LOCAL_MME1_CTRL_MAX_OFFSET 0x2400
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#define SHADOW_0_AGU_L_LOCAL_MME1_CTRL_SECTION 0x2400
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#define mmSHADOW_0_AGU_L_REMOTE_MME1_CTRL_BASE 0x7FFC0E051Cull
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#define SHADOW_0_AGU_L_REMOTE_MME1_CTRL_MAX_OFFSET 0x2400
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#define SHADOW_0_AGU_L_REMOTE_MME1_CTRL_SECTION 0x2400
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#define mmSHADOW_0_TENSOR_O_MME1_CTRL_BASE 0x7FFC0E0540ull
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#define SHADOW_0_TENSOR_O_MME1_CTRL_MAX_OFFSET 0x4C00
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#define SHADOW_0_TENSOR_O_MME1_CTRL_SECTION 0x4C00
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#define mmSHADOW_0_AGU_O_LOCAL_MME1_CTRL_BASE 0x7FFC0E058Cull
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#define SHADOW_0_AGU_O_LOCAL_MME1_CTRL_MAX_OFFSET 0x2400
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#define SHADOW_0_AGU_O_LOCAL_MME1_CTRL_SECTION 0x2400
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#define mmSHADOW_0_AGU_O_REMOTE_MME1_CTRL_BASE 0x7FFC0E05B0ull
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#define SHADOW_0_AGU_O_REMOTE_MME1_CTRL_MAX_OFFSET 0x2400
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#define SHADOW_0_AGU_O_REMOTE_MME1_CTRL_SECTION 0x2400
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#define mmSHADOW_0_DESC_MME1_CTRL_BASE 0x7FFC0E05D4ull
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#define SHADOW_0_DESC_MME1_CTRL_MAX_OFFSET 0x5400
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#define SHADOW_0_DESC_MME1_CTRL_SECTION 0xB400
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#define mmSHADOW_1_MME1_CTRL_BASE 0x7FFC0E0688ull
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#define SHADOW_1_MME1_CTRL_MAX_OFFSET 0x3400
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#define SHADOW_1_MME1_CTRL_SECTION 0x3400
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#define mmSHADOW_1_TENSOR_S_MME1_CTRL_BASE 0x7FFC0E06BCull
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#define SHADOW_1_TENSOR_S_MME1_CTRL_MAX_OFFSET 0x4C00
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#define SHADOW_1_TENSOR_S_MME1_CTRL_SECTION 0x4C00
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#define mmSHADOW_1_AGU_S_MME1_CTRL_BASE 0x7FFC0E0708ull
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#define SHADOW_1_AGU_S_MME1_CTRL_MAX_OFFSET 0x2400
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#define SHADOW_1_AGU_S_MME1_CTRL_SECTION 0x2400
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#define mmSHADOW_1_TENSOR_L_MME1_CTRL_BASE 0x7FFC0E072Cull
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#define SHADOW_1_TENSOR_L_MME1_CTRL_MAX_OFFSET 0x4C00
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#define SHADOW_1_TENSOR_L_MME1_CTRL_SECTION 0x4C00
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#define mmSHADOW_1_AGU_L_LOCAL_MME1_CTRL_BASE 0x7FFC0E0778ull
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#define SHADOW_1_AGU_L_LOCAL_MME1_CTRL_MAX_OFFSET 0x2400
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#define SHADOW_1_AGU_L_LOCAL_MME1_CTRL_SECTION 0x2400
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#define mmSHADOW_1_AGU_L_REMOTE_MME1_CTRL_BASE 0x7FFC0E079Cull
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#define SHADOW_1_AGU_L_REMOTE_MME1_CTRL_MAX_OFFSET 0x2400
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#define SHADOW_1_AGU_L_REMOTE_MME1_CTRL_SECTION 0x2400
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#define mmSHADOW_1_TENSOR_O_MME1_CTRL_BASE 0x7FFC0E07C0ull
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#define SHADOW_1_TENSOR_O_MME1_CTRL_MAX_OFFSET 0x4C00
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#define SHADOW_1_TENSOR_O_MME1_CTRL_SECTION 0x4C00
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#define mmSHADOW_1_AGU_O_LOCAL_MME1_CTRL_BASE 0x7FFC0E080Cull
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#define SHADOW_1_AGU_O_LOCAL_MME1_CTRL_MAX_OFFSET 0x2400
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#define SHADOW_1_AGU_O_LOCAL_MME1_CTRL_SECTION 0x2400
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#define mmSHADOW_1_AGU_O_REMOTE_MME1_CTRL_BASE 0x7FFC0E0830ull
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#define SHADOW_1_AGU_O_REMOTE_MME1_CTRL_MAX_OFFSET 0x2400
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#define SHADOW_1_AGU_O_REMOTE_MME1_CTRL_SECTION 0x2400
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#define mmSHADOW_1_DESC_MME1_CTRL_BASE 0x7FFC0E0854ull
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#define SHADOW_1_DESC_MME1_CTRL_MAX_OFFSET 0x5400
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#define SHADOW_1_DESC_MME1_CTRL_SECTION 0xB400
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#define mmSHADOW_2_MME1_CTRL_BASE 0x7FFC0E0908ull
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#define SHADOW_2_MME1_CTRL_MAX_OFFSET 0x3400
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#define SHADOW_2_MME1_CTRL_SECTION 0x3400
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#define mmSHADOW_2_TENSOR_S_MME1_CTRL_BASE 0x7FFC0E093Cull
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#define SHADOW_2_TENSOR_S_MME1_CTRL_MAX_OFFSET 0x4C00
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#define SHADOW_2_TENSOR_S_MME1_CTRL_SECTION 0x4C00
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#define mmSHADOW_2_AGU_S_MME1_CTRL_BASE 0x7FFC0E0988ull
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#define SHADOW_2_AGU_S_MME1_CTRL_MAX_OFFSET 0x2400
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#define SHADOW_2_AGU_S_MME1_CTRL_SECTION 0x2400
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#define mmSHADOW_2_TENSOR_L_MME1_CTRL_BASE 0x7FFC0E09ACull
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#define SHADOW_2_TENSOR_L_MME1_CTRL_MAX_OFFSET 0x4C00
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#define SHADOW_2_TENSOR_L_MME1_CTRL_SECTION 0x4C00
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#define mmSHADOW_2_AGU_L_LOCAL_MME1_CTRL_BASE 0x7FFC0E09F8ull
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#define SHADOW_2_AGU_L_LOCAL_MME1_CTRL_MAX_OFFSET 0x2400
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#define SHADOW_2_AGU_L_LOCAL_MME1_CTRL_SECTION 0x2400
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#define mmSHADOW_2_AGU_L_REMOTE_MME1_CTRL_BASE 0x7FFC0E0A1Cull
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#define SHADOW_2_AGU_L_REMOTE_MME1_CTRL_MAX_OFFSET 0x2400
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#define SHADOW_2_AGU_L_REMOTE_MME1_CTRL_SECTION 0x2400
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#define mmSHADOW_2_TENSOR_O_MME1_CTRL_BASE 0x7FFC0E0A40ull
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#define SHADOW_2_TENSOR_O_MME1_CTRL_MAX_OFFSET 0x4C00
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#define SHADOW_2_TENSOR_O_MME1_CTRL_SECTION 0x4C00
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#define mmSHADOW_2_AGU_O_LOCAL_MME1_CTRL_BASE 0x7FFC0E0A8Cull
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#define SHADOW_2_AGU_O_LOCAL_MME1_CTRL_MAX_OFFSET 0x2400
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#define SHADOW_2_AGU_O_LOCAL_MME1_CTRL_SECTION 0x2400
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#define mmSHADOW_2_AGU_O_REMOTE_MME1_CTRL_BASE 0x7FFC0E0AB0ull
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#define SHADOW_2_AGU_O_REMOTE_MME1_CTRL_MAX_OFFSET 0x2400
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#define SHADOW_2_AGU_O_REMOTE_MME1_CTRL_SECTION 0x2400
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#define mmSHADOW_2_DESC_MME1_CTRL_BASE 0x7FFC0E0AD4ull
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#define SHADOW_2_DESC_MME1_CTRL_MAX_OFFSET 0x5400
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#define SHADOW_2_DESC_MME1_CTRL_SECTION 0xB400
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#define mmSHADOW_3_MME1_CTRL_BASE 0x7FFC0E0B88ull
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#define SHADOW_3_MME1_CTRL_MAX_OFFSET 0x3400
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#define SHADOW_3_MME1_CTRL_SECTION 0x3400
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#define mmSHADOW_3_TENSOR_S_MME1_CTRL_BASE 0x7FFC0E0BBCull
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#define SHADOW_3_TENSOR_S_MME1_CTRL_MAX_OFFSET 0x4C00
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#define SHADOW_3_TENSOR_S_MME1_CTRL_SECTION 0x4C00
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#define mmSHADOW_3_AGU_S_MME1_CTRL_BASE 0x7FFC0E0C08ull
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#define SHADOW_3_AGU_S_MME1_CTRL_MAX_OFFSET 0x2400
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#define SHADOW_3_AGU_S_MME1_CTRL_SECTION 0x2400
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#define mmSHADOW_3_TENSOR_L_MME1_CTRL_BASE 0x7FFC0E0C2Cull
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#define SHADOW_3_TENSOR_L_MME1_CTRL_MAX_OFFSET 0x4C00
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#define SHADOW_3_TENSOR_L_MME1_CTRL_SECTION 0x4C00
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#define mmSHADOW_3_AGU_L_LOCAL_MME1_CTRL_BASE 0x7FFC0E0C78ull
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#define SHADOW_3_AGU_L_LOCAL_MME1_CTRL_MAX_OFFSET 0x2400
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#define SHADOW_3_AGU_L_LOCAL_MME1_CTRL_SECTION 0x2400
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#define mmSHADOW_3_AGU_L_REMOTE_MME1_CTRL_BASE 0x7FFC0E0C9Cull
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#define SHADOW_3_AGU_L_REMOTE_MME1_CTRL_MAX_OFFSET 0x2400
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#define SHADOW_3_AGU_L_REMOTE_MME1_CTRL_SECTION 0x2400
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#define mmSHADOW_3_TENSOR_O_MME1_CTRL_BASE 0x7FFC0E0CC0ull
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#define SHADOW_3_TENSOR_O_MME1_CTRL_MAX_OFFSET 0x4C00
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#define SHADOW_3_TENSOR_O_MME1_CTRL_SECTION 0x4C00
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#define mmSHADOW_3_AGU_O_LOCAL_MME1_CTRL_BASE 0x7FFC0E0D0Cull
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#define SHADOW_3_AGU_O_LOCAL_MME1_CTRL_MAX_OFFSET 0x2400
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#define SHADOW_3_AGU_O_LOCAL_MME1_CTRL_SECTION 0x2400
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#define mmSHADOW_3_AGU_O_REMOTE_MME1_CTRL_BASE 0x7FFC0E0D30ull
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#define SHADOW_3_AGU_O_REMOTE_MME1_CTRL_MAX_OFFSET 0x2400
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#define SHADOW_3_AGU_O_REMOTE_MME1_CTRL_SECTION 0x2400
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#define mmSHADOW_3_DESC_MME1_CTRL_BASE 0x7FFC0E0D54ull
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#define SHADOW_3_DESC_MME1_CTRL_MAX_OFFSET 0x5400
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#define SHADOW_3_DESC_MME1_CTRL_SECTION 0x72AC
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#define mmMME1_QM_BASE 0x7FFC0E8000ull
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#define MME1_QM_MAX_OFFSET 0xD040
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#define MME1_QM_SECTION 0x38000
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#define mmMME2_ACC_BASE 0x7FFC120000ull
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#define MME2_ACC_MAX_OFFSET 0x5C00
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#define MME2_ACC_SECTION 0x20000
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#define mmMME2_SBAB_BASE 0x7FFC140000ull
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#define MME2_SBAB_MAX_OFFSET 0x5800
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#define MME2_SBAB_SECTION 0x1000
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#define mmMME2_PRTN_BASE 0x7FFC141000ull
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#define MME2_PRTN_MAX_OFFSET 0x5000
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#define MME2_PRTN_SECTION 0x1F000
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#define mmMME2_CTRL_BASE 0x7FFC160000ull
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#define MME2_CTRL_MAX_OFFSET 0xDA80
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#define MME2_CTRL_SECTION 0x8000
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#define mmARCH_MME2_CTRL_BASE 0x7FFC160008ull
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#define ARCH_MME2_CTRL_MAX_OFFSET 0x3400
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#define ARCH_MME2_CTRL_SECTION 0x3400
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#define mmARCH_TENSOR_S_MME2_CTRL_BASE 0x7FFC16003Cull
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#define ARCH_TENSOR_S_MME2_CTRL_MAX_OFFSET 0x4C00
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#define ARCH_TENSOR_S_MME2_CTRL_SECTION 0x4C00
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#define mmARCH_AGU_S_MME2_CTRL_BASE 0x7FFC160088ull
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#define ARCH_AGU_S_MME2_CTRL_MAX_OFFSET 0x2400
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#define ARCH_AGU_S_MME2_CTRL_SECTION 0x2400
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#define mmARCH_TENSOR_L_MME2_CTRL_BASE 0x7FFC1600ACull
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#define ARCH_TENSOR_L_MME2_CTRL_MAX_OFFSET 0x4C00
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#define ARCH_TENSOR_L_MME2_CTRL_SECTION 0x4C00
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#define mmARCH_AGU_L_LOCAL_MME2_CTRL_BASE 0x7FFC1600F8ull
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#define ARCH_AGU_L_LOCAL_MME2_CTRL_MAX_OFFSET 0x2400
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#define ARCH_AGU_L_LOCAL_MME2_CTRL_SECTION 0x2400
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#define mmARCH_AGU_L_REMOTE_MME2_CTRL_BASE 0x7FFC16011Cull
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#define ARCH_AGU_L_REMOTE_MME2_CTRL_MAX_OFFSET 0x2400
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#define ARCH_AGU_L_REMOTE_MME2_CTRL_SECTION 0x2400
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#define mmARCH_TENSOR_O_MME2_CTRL_BASE 0x7FFC160140ull
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#define ARCH_TENSOR_O_MME2_CTRL_MAX_OFFSET 0x4C00
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#define ARCH_TENSOR_O_MME2_CTRL_SECTION 0x4C00
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#define mmARCH_AGU_O_LOCAL_MME2_CTRL_BASE 0x7FFC16018Cull
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#define ARCH_AGU_O_LOCAL_MME2_CTRL_MAX_OFFSET 0x2400
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#define ARCH_AGU_O_LOCAL_MME2_CTRL_SECTION 0x2400
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#define mmARCH_AGU_O_REMOTE_MME2_CTRL_BASE 0x7FFC1601B0ull
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#define ARCH_AGU_O_REMOTE_MME2_CTRL_MAX_OFFSET 0x2400
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#define ARCH_AGU_O_REMOTE_MME2_CTRL_SECTION 0x2400
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#define mmARCH_DESC_MME2_CTRL_BASE 0x7FFC1601D4ull
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#define ARCH_DESC_MME2_CTRL_MAX_OFFSET 0x5400
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#define ARCH_DESC_MME2_CTRL_SECTION 0x2340
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#define mmSHADOW_0_MME2_CTRL_BASE 0x7FFC160408ull
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#define SHADOW_0_MME2_CTRL_MAX_OFFSET 0x3400
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#define SHADOW_0_MME2_CTRL_SECTION 0x3400
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#define mmSHADOW_0_TENSOR_S_MME2_CTRL_BASE 0x7FFC16043Cull
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#define SHADOW_0_TENSOR_S_MME2_CTRL_MAX_OFFSET 0x4C00
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#define SHADOW_0_TENSOR_S_MME2_CTRL_SECTION 0x4C00
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#define mmSHADOW_0_AGU_S_MME2_CTRL_BASE 0x7FFC160488ull
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#define SHADOW_0_AGU_S_MME2_CTRL_MAX_OFFSET 0x2400
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#define SHADOW_0_AGU_S_MME2_CTRL_SECTION 0x2400
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#define mmSHADOW_0_TENSOR_L_MME2_CTRL_BASE 0x7FFC1604ACull
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#define SHADOW_0_TENSOR_L_MME2_CTRL_MAX_OFFSET 0x4C00
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#define SHADOW_0_TENSOR_L_MME2_CTRL_SECTION 0x4C00
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#define mmSHADOW_0_AGU_L_LOCAL_MME2_CTRL_BASE 0x7FFC1604F8ull
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#define SHADOW_0_AGU_L_LOCAL_MME2_CTRL_MAX_OFFSET 0x2400
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#define SHADOW_0_AGU_L_LOCAL_MME2_CTRL_SECTION 0x2400
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#define mmSHADOW_0_AGU_L_REMOTE_MME2_CTRL_BASE 0x7FFC16051Cull
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#define SHADOW_0_AGU_L_REMOTE_MME2_CTRL_MAX_OFFSET 0x2400
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#define SHADOW_0_AGU_L_REMOTE_MME2_CTRL_SECTION 0x2400
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#define mmSHADOW_0_TENSOR_O_MME2_CTRL_BASE 0x7FFC160540ull
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#define SHADOW_0_TENSOR_O_MME2_CTRL_MAX_OFFSET 0x4C00
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#define SHADOW_0_TENSOR_O_MME2_CTRL_SECTION 0x4C00
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#define mmSHADOW_0_AGU_O_LOCAL_MME2_CTRL_BASE 0x7FFC16058Cull
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#define SHADOW_0_AGU_O_LOCAL_MME2_CTRL_MAX_OFFSET 0x2400
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#define SHADOW_0_AGU_O_LOCAL_MME2_CTRL_SECTION 0x2400
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#define mmSHADOW_0_AGU_O_REMOTE_MME2_CTRL_BASE 0x7FFC1605B0ull
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#define SHADOW_0_AGU_O_REMOTE_MME2_CTRL_MAX_OFFSET 0x2400
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#define SHADOW_0_AGU_O_REMOTE_MME2_CTRL_SECTION 0x2400
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#define mmSHADOW_0_DESC_MME2_CTRL_BASE 0x7FFC1605D4ull
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#define SHADOW_0_DESC_MME2_CTRL_MAX_OFFSET 0x5400
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#define SHADOW_0_DESC_MME2_CTRL_SECTION 0xB400
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#define mmSHADOW_1_MME2_CTRL_BASE 0x7FFC160688ull
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#define SHADOW_1_MME2_CTRL_MAX_OFFSET 0x3400
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#define SHADOW_1_MME2_CTRL_SECTION 0x3400
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#define mmSHADOW_1_TENSOR_S_MME2_CTRL_BASE 0x7FFC1606BCull
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#define SHADOW_1_TENSOR_S_MME2_CTRL_MAX_OFFSET 0x4C00
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#define SHADOW_1_TENSOR_S_MME2_CTRL_SECTION 0x4C00
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#define mmSHADOW_1_AGU_S_MME2_CTRL_BASE 0x7FFC160708ull
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#define SHADOW_1_AGU_S_MME2_CTRL_MAX_OFFSET 0x2400
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#define SHADOW_1_AGU_S_MME2_CTRL_SECTION 0x2400
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#define mmSHADOW_1_TENSOR_L_MME2_CTRL_BASE 0x7FFC16072Cull
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#define SHADOW_1_TENSOR_L_MME2_CTRL_MAX_OFFSET 0x4C00
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#define SHADOW_1_TENSOR_L_MME2_CTRL_SECTION 0x4C00
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#define mmSHADOW_1_AGU_L_LOCAL_MME2_CTRL_BASE 0x7FFC160778ull
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#define SHADOW_1_AGU_L_LOCAL_MME2_CTRL_MAX_OFFSET 0x2400
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#define SHADOW_1_AGU_L_LOCAL_MME2_CTRL_SECTION 0x2400
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#define mmSHADOW_1_AGU_L_REMOTE_MME2_CTRL_BASE 0x7FFC16079Cull
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#define SHADOW_1_AGU_L_REMOTE_MME2_CTRL_MAX_OFFSET 0x2400
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#define SHADOW_1_AGU_L_REMOTE_MME2_CTRL_SECTION 0x2400
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#define mmSHADOW_1_TENSOR_O_MME2_CTRL_BASE 0x7FFC1607C0ull
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#define SHADOW_1_TENSOR_O_MME2_CTRL_MAX_OFFSET 0x4C00
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#define SHADOW_1_TENSOR_O_MME2_CTRL_SECTION 0x4C00
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#define mmSHADOW_1_AGU_O_LOCAL_MME2_CTRL_BASE 0x7FFC16080Cull
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#define SHADOW_1_AGU_O_LOCAL_MME2_CTRL_MAX_OFFSET 0x2400
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#define SHADOW_1_AGU_O_LOCAL_MME2_CTRL_SECTION 0x2400
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#define mmSHADOW_1_AGU_O_REMOTE_MME2_CTRL_BASE 0x7FFC160830ull
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#define SHADOW_1_AGU_O_REMOTE_MME2_CTRL_MAX_OFFSET 0x2400
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#define SHADOW_1_AGU_O_REMOTE_MME2_CTRL_SECTION 0x2400
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#define mmSHADOW_1_DESC_MME2_CTRL_BASE 0x7FFC160854ull
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#define SHADOW_1_DESC_MME2_CTRL_MAX_OFFSET 0x5400
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#define SHADOW_1_DESC_MME2_CTRL_SECTION 0xB400
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#define mmSHADOW_2_MME2_CTRL_BASE 0x7FFC160908ull
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#define SHADOW_2_MME2_CTRL_MAX_OFFSET 0x3400
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#define SHADOW_2_MME2_CTRL_SECTION 0x3400
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#define mmSHADOW_2_TENSOR_S_MME2_CTRL_BASE 0x7FFC16093Cull
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#define SHADOW_2_TENSOR_S_MME2_CTRL_MAX_OFFSET 0x4C00
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#define SHADOW_2_TENSOR_S_MME2_CTRL_SECTION 0x4C00
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#define mmSHADOW_2_AGU_S_MME2_CTRL_BASE 0x7FFC160988ull
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#define SHADOW_2_AGU_S_MME2_CTRL_MAX_OFFSET 0x2400
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#define SHADOW_2_AGU_S_MME2_CTRL_SECTION 0x2400
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#define mmSHADOW_2_TENSOR_L_MME2_CTRL_BASE 0x7FFC1609ACull
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#define SHADOW_2_TENSOR_L_MME2_CTRL_MAX_OFFSET 0x4C00
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#define SHADOW_2_TENSOR_L_MME2_CTRL_SECTION 0x4C00
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#define mmSHADOW_2_AGU_L_LOCAL_MME2_CTRL_BASE 0x7FFC1609F8ull
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#define SHADOW_2_AGU_L_LOCAL_MME2_CTRL_MAX_OFFSET 0x2400
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#define SHADOW_2_AGU_L_LOCAL_MME2_CTRL_SECTION 0x2400
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#define mmSHADOW_2_AGU_L_REMOTE_MME2_CTRL_BASE 0x7FFC160A1Cull
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#define SHADOW_2_AGU_L_REMOTE_MME2_CTRL_MAX_OFFSET 0x2400
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#define SHADOW_2_AGU_L_REMOTE_MME2_CTRL_SECTION 0x2400
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#define mmSHADOW_2_TENSOR_O_MME2_CTRL_BASE 0x7FFC160A40ull
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#define SHADOW_2_TENSOR_O_MME2_CTRL_MAX_OFFSET 0x4C00
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#define SHADOW_2_TENSOR_O_MME2_CTRL_SECTION 0x4C00
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#define mmSHADOW_2_AGU_O_LOCAL_MME2_CTRL_BASE 0x7FFC160A8Cull
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#define SHADOW_2_AGU_O_LOCAL_MME2_CTRL_MAX_OFFSET 0x2400
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#define SHADOW_2_AGU_O_LOCAL_MME2_CTRL_SECTION 0x2400
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#define mmSHADOW_2_AGU_O_REMOTE_MME2_CTRL_BASE 0x7FFC160AB0ull
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#define SHADOW_2_AGU_O_REMOTE_MME2_CTRL_MAX_OFFSET 0x2400
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#define SHADOW_2_AGU_O_REMOTE_MME2_CTRL_SECTION 0x2400
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#define mmSHADOW_2_DESC_MME2_CTRL_BASE 0x7FFC160AD4ull
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#define SHADOW_2_DESC_MME2_CTRL_MAX_OFFSET 0x5400
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#define SHADOW_2_DESC_MME2_CTRL_SECTION 0xB400
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#define mmSHADOW_3_MME2_CTRL_BASE 0x7FFC160B88ull
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#define SHADOW_3_MME2_CTRL_MAX_OFFSET 0x3400
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#define SHADOW_3_MME2_CTRL_SECTION 0x3400
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#define mmSHADOW_3_TENSOR_S_MME2_CTRL_BASE 0x7FFC160BBCull
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#define SHADOW_3_TENSOR_S_MME2_CTRL_MAX_OFFSET 0x4C00
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#define SHADOW_3_TENSOR_S_MME2_CTRL_SECTION 0x4C00
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#define mmSHADOW_3_AGU_S_MME2_CTRL_BASE 0x7FFC160C08ull
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#define SHADOW_3_AGU_S_MME2_CTRL_MAX_OFFSET 0x2400
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#define SHADOW_3_AGU_S_MME2_CTRL_SECTION 0x2400
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#define mmSHADOW_3_TENSOR_L_MME2_CTRL_BASE 0x7FFC160C2Cull
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#define SHADOW_3_TENSOR_L_MME2_CTRL_MAX_OFFSET 0x4C00
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#define SHADOW_3_TENSOR_L_MME2_CTRL_SECTION 0x4C00
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#define mmSHADOW_3_AGU_L_LOCAL_MME2_CTRL_BASE 0x7FFC160C78ull
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#define SHADOW_3_AGU_L_LOCAL_MME2_CTRL_MAX_OFFSET 0x2400
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#define SHADOW_3_AGU_L_LOCAL_MME2_CTRL_SECTION 0x2400
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#define mmSHADOW_3_AGU_L_REMOTE_MME2_CTRL_BASE 0x7FFC160C9Cull
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#define SHADOW_3_AGU_L_REMOTE_MME2_CTRL_MAX_OFFSET 0x2400
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#define SHADOW_3_AGU_L_REMOTE_MME2_CTRL_SECTION 0x2400
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#define mmSHADOW_3_TENSOR_O_MME2_CTRL_BASE 0x7FFC160CC0ull
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#define SHADOW_3_TENSOR_O_MME2_CTRL_MAX_OFFSET 0x4C00
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#define SHADOW_3_TENSOR_O_MME2_CTRL_SECTION 0x4C00
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#define mmSHADOW_3_AGU_O_LOCAL_MME2_CTRL_BASE 0x7FFC160D0Cull
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#define SHADOW_3_AGU_O_LOCAL_MME2_CTRL_MAX_OFFSET 0x2400
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#define SHADOW_3_AGU_O_LOCAL_MME2_CTRL_SECTION 0x2400
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#define mmSHADOW_3_AGU_O_REMOTE_MME2_CTRL_BASE 0x7FFC160D30ull
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#define SHADOW_3_AGU_O_REMOTE_MME2_CTRL_MAX_OFFSET 0x2400
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#define SHADOW_3_AGU_O_REMOTE_MME2_CTRL_SECTION 0x2400
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#define mmSHADOW_3_DESC_MME2_CTRL_BASE 0x7FFC160D54ull
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#define SHADOW_3_DESC_MME2_CTRL_MAX_OFFSET 0x5400
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#define SHADOW_3_DESC_MME2_CTRL_SECTION 0x72AC
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#define mmMME2_QM_BASE 0x7FFC168000ull
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#define MME2_QM_MAX_OFFSET 0xD040
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#define MME2_QM_SECTION 0x38000
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#define mmMME3_ACC_BASE 0x7FFC1A0000ull
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#define MME3_ACC_MAX_OFFSET 0x5C00
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#define MME3_ACC_SECTION 0x20000
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#define mmMME3_SBAB_BASE 0x7FFC1C0000ull
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#define MME3_SBAB_MAX_OFFSET 0x5800
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#define MME3_SBAB_SECTION 0x1000
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#define mmMME3_PRTN_BASE 0x7FFC1C1000ull
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#define MME3_PRTN_MAX_OFFSET 0x5000
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#define MME3_PRTN_SECTION 0x1F000
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#define mmMME3_CTRL_BASE 0x7FFC1E0000ull
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#define MME3_CTRL_MAX_OFFSET 0xDA80
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#define MME3_CTRL_SECTION 0x8000
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#define mmARCH_MME3_CTRL_BASE 0x7FFC1E0008ull
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#define ARCH_MME3_CTRL_MAX_OFFSET 0x3400
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#define ARCH_MME3_CTRL_SECTION 0x3400
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#define mmARCH_TENSOR_S_MME3_CTRL_BASE 0x7FFC1E003Cull
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#define ARCH_TENSOR_S_MME3_CTRL_MAX_OFFSET 0x4C00
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#define ARCH_TENSOR_S_MME3_CTRL_SECTION 0x4C00
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#define mmARCH_AGU_S_MME3_CTRL_BASE 0x7FFC1E0088ull
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#define ARCH_AGU_S_MME3_CTRL_MAX_OFFSET 0x2400
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#define ARCH_AGU_S_MME3_CTRL_SECTION 0x2400
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#define mmARCH_TENSOR_L_MME3_CTRL_BASE 0x7FFC1E00ACull
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#define ARCH_TENSOR_L_MME3_CTRL_MAX_OFFSET 0x4C00
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#define ARCH_TENSOR_L_MME3_CTRL_SECTION 0x4C00
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#define mmARCH_AGU_L_LOCAL_MME3_CTRL_BASE 0x7FFC1E00F8ull
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#define ARCH_AGU_L_LOCAL_MME3_CTRL_MAX_OFFSET 0x2400
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#define ARCH_AGU_L_LOCAL_MME3_CTRL_SECTION 0x2400
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#define mmARCH_AGU_L_REMOTE_MME3_CTRL_BASE 0x7FFC1E011Cull
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#define ARCH_AGU_L_REMOTE_MME3_CTRL_MAX_OFFSET 0x2400
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#define ARCH_AGU_L_REMOTE_MME3_CTRL_SECTION 0x2400
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#define mmARCH_TENSOR_O_MME3_CTRL_BASE 0x7FFC1E0140ull
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#define ARCH_TENSOR_O_MME3_CTRL_MAX_OFFSET 0x4C00
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#define ARCH_TENSOR_O_MME3_CTRL_SECTION 0x4C00
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#define mmARCH_AGU_O_LOCAL_MME3_CTRL_BASE 0x7FFC1E018Cull
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#define ARCH_AGU_O_LOCAL_MME3_CTRL_MAX_OFFSET 0x2400
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#define ARCH_AGU_O_LOCAL_MME3_CTRL_SECTION 0x2400
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#define mmARCH_AGU_O_REMOTE_MME3_CTRL_BASE 0x7FFC1E01B0ull
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#define ARCH_AGU_O_REMOTE_MME3_CTRL_MAX_OFFSET 0x2400
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#define ARCH_AGU_O_REMOTE_MME3_CTRL_SECTION 0x2400
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#define mmARCH_DESC_MME3_CTRL_BASE 0x7FFC1E01D4ull
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#define ARCH_DESC_MME3_CTRL_MAX_OFFSET 0x5400
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#define ARCH_DESC_MME3_CTRL_SECTION 0x2340
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#define mmSHADOW_0_MME3_CTRL_BASE 0x7FFC1E0408ull
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#define SHADOW_0_MME3_CTRL_MAX_OFFSET 0x3400
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#define SHADOW_0_MME3_CTRL_SECTION 0x3400
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#define mmSHADOW_0_TENSOR_S_MME3_CTRL_BASE 0x7FFC1E043Cull
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#define SHADOW_0_TENSOR_S_MME3_CTRL_MAX_OFFSET 0x4C00
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#define SHADOW_0_TENSOR_S_MME3_CTRL_SECTION 0x4C00
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#define mmSHADOW_0_AGU_S_MME3_CTRL_BASE 0x7FFC1E0488ull
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#define SHADOW_0_AGU_S_MME3_CTRL_MAX_OFFSET 0x2400
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#define SHADOW_0_AGU_S_MME3_CTRL_SECTION 0x2400
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#define mmSHADOW_0_TENSOR_L_MME3_CTRL_BASE 0x7FFC1E04ACull
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#define SHADOW_0_TENSOR_L_MME3_CTRL_MAX_OFFSET 0x4C00
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#define SHADOW_0_TENSOR_L_MME3_CTRL_SECTION 0x4C00
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#define mmSHADOW_0_AGU_L_LOCAL_MME3_CTRL_BASE 0x7FFC1E04F8ull
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#define SHADOW_0_AGU_L_LOCAL_MME3_CTRL_MAX_OFFSET 0x2400
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#define SHADOW_0_AGU_L_LOCAL_MME3_CTRL_SECTION 0x2400
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#define mmSHADOW_0_AGU_L_REMOTE_MME3_CTRL_BASE 0x7FFC1E051Cull
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#define SHADOW_0_AGU_L_REMOTE_MME3_CTRL_MAX_OFFSET 0x2400
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#define SHADOW_0_AGU_L_REMOTE_MME3_CTRL_SECTION 0x2400
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#define mmSHADOW_0_TENSOR_O_MME3_CTRL_BASE 0x7FFC1E0540ull
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#define SHADOW_0_TENSOR_O_MME3_CTRL_MAX_OFFSET 0x4C00
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#define SHADOW_0_TENSOR_O_MME3_CTRL_SECTION 0x4C00
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#define mmSHADOW_0_AGU_O_LOCAL_MME3_CTRL_BASE 0x7FFC1E058Cull
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#define SHADOW_0_AGU_O_LOCAL_MME3_CTRL_MAX_OFFSET 0x2400
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#define SHADOW_0_AGU_O_LOCAL_MME3_CTRL_SECTION 0x2400
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#define mmSHADOW_0_AGU_O_REMOTE_MME3_CTRL_BASE 0x7FFC1E05B0ull
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#define SHADOW_0_AGU_O_REMOTE_MME3_CTRL_MAX_OFFSET 0x2400
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#define SHADOW_0_AGU_O_REMOTE_MME3_CTRL_SECTION 0x2400
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#define mmSHADOW_0_DESC_MME3_CTRL_BASE 0x7FFC1E05D4ull
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#define SHADOW_0_DESC_MME3_CTRL_MAX_OFFSET 0x5400
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#define SHADOW_0_DESC_MME3_CTRL_SECTION 0xB400
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#define mmSHADOW_1_MME3_CTRL_BASE 0x7FFC1E0688ull
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#define SHADOW_1_MME3_CTRL_MAX_OFFSET 0x3400
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#define SHADOW_1_MME3_CTRL_SECTION 0x3400
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#define mmSHADOW_1_TENSOR_S_MME3_CTRL_BASE 0x7FFC1E06BCull
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#define SHADOW_1_TENSOR_S_MME3_CTRL_MAX_OFFSET 0x4C00
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#define SHADOW_1_TENSOR_S_MME3_CTRL_SECTION 0x4C00
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#define mmSHADOW_1_AGU_S_MME3_CTRL_BASE 0x7FFC1E0708ull
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#define SHADOW_1_AGU_S_MME3_CTRL_MAX_OFFSET 0x2400
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#define SHADOW_1_AGU_S_MME3_CTRL_SECTION 0x2400
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#define mmSHADOW_1_TENSOR_L_MME3_CTRL_BASE 0x7FFC1E072Cull
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#define SHADOW_1_TENSOR_L_MME3_CTRL_MAX_OFFSET 0x4C00
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#define SHADOW_1_TENSOR_L_MME3_CTRL_SECTION 0x4C00
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#define mmSHADOW_1_AGU_L_LOCAL_MME3_CTRL_BASE 0x7FFC1E0778ull
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#define SHADOW_1_AGU_L_LOCAL_MME3_CTRL_MAX_OFFSET 0x2400
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#define SHADOW_1_AGU_L_LOCAL_MME3_CTRL_SECTION 0x2400
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#define mmSHADOW_1_AGU_L_REMOTE_MME3_CTRL_BASE 0x7FFC1E079Cull
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#define SHADOW_1_AGU_L_REMOTE_MME3_CTRL_MAX_OFFSET 0x2400
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#define SHADOW_1_AGU_L_REMOTE_MME3_CTRL_SECTION 0x2400
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#define mmSHADOW_1_TENSOR_O_MME3_CTRL_BASE 0x7FFC1E07C0ull
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#define SHADOW_1_TENSOR_O_MME3_CTRL_MAX_OFFSET 0x4C00
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#define SHADOW_1_TENSOR_O_MME3_CTRL_SECTION 0x4C00
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#define mmSHADOW_1_AGU_O_LOCAL_MME3_CTRL_BASE 0x7FFC1E080Cull
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#define SHADOW_1_AGU_O_LOCAL_MME3_CTRL_MAX_OFFSET 0x2400
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#define SHADOW_1_AGU_O_LOCAL_MME3_CTRL_SECTION 0x2400
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#define mmSHADOW_1_AGU_O_REMOTE_MME3_CTRL_BASE 0x7FFC1E0830ull
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#define SHADOW_1_AGU_O_REMOTE_MME3_CTRL_MAX_OFFSET 0x2400
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#define SHADOW_1_AGU_O_REMOTE_MME3_CTRL_SECTION 0x2400
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#define mmSHADOW_1_DESC_MME3_CTRL_BASE 0x7FFC1E0854ull
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#define SHADOW_1_DESC_MME3_CTRL_MAX_OFFSET 0x5400
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#define SHADOW_1_DESC_MME3_CTRL_SECTION 0xB400
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#define mmSHADOW_2_MME3_CTRL_BASE 0x7FFC1E0908ull
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#define SHADOW_2_MME3_CTRL_MAX_OFFSET 0x3400
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#define SHADOW_2_MME3_CTRL_SECTION 0x3400
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#define mmSHADOW_2_TENSOR_S_MME3_CTRL_BASE 0x7FFC1E093Cull
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#define SHADOW_2_TENSOR_S_MME3_CTRL_MAX_OFFSET 0x4C00
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#define SHADOW_2_TENSOR_S_MME3_CTRL_SECTION 0x4C00
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#define mmSHADOW_2_AGU_S_MME3_CTRL_BASE 0x7FFC1E0988ull
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#define SHADOW_2_AGU_S_MME3_CTRL_MAX_OFFSET 0x2400
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#define SHADOW_2_AGU_S_MME3_CTRL_SECTION 0x2400
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#define mmSHADOW_2_TENSOR_L_MME3_CTRL_BASE 0x7FFC1E09ACull
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#define SHADOW_2_TENSOR_L_MME3_CTRL_MAX_OFFSET 0x4C00
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#define SHADOW_2_TENSOR_L_MME3_CTRL_SECTION 0x4C00
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#define mmSHADOW_2_AGU_L_LOCAL_MME3_CTRL_BASE 0x7FFC1E09F8ull
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#define SHADOW_2_AGU_L_LOCAL_MME3_CTRL_MAX_OFFSET 0x2400
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#define SHADOW_2_AGU_L_LOCAL_MME3_CTRL_SECTION 0x2400
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#define mmSHADOW_2_AGU_L_REMOTE_MME3_CTRL_BASE 0x7FFC1E0A1Cull
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#define SHADOW_2_AGU_L_REMOTE_MME3_CTRL_MAX_OFFSET 0x2400
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#define SHADOW_2_AGU_L_REMOTE_MME3_CTRL_SECTION 0x2400
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#define mmSHADOW_2_TENSOR_O_MME3_CTRL_BASE 0x7FFC1E0A40ull
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#define SHADOW_2_TENSOR_O_MME3_CTRL_MAX_OFFSET 0x4C00
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#define SHADOW_2_TENSOR_O_MME3_CTRL_SECTION 0x4C00
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#define mmSHADOW_2_AGU_O_LOCAL_MME3_CTRL_BASE 0x7FFC1E0A8Cull
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#define SHADOW_2_AGU_O_LOCAL_MME3_CTRL_MAX_OFFSET 0x2400
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#define SHADOW_2_AGU_O_LOCAL_MME3_CTRL_SECTION 0x2400
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#define mmSHADOW_2_AGU_O_REMOTE_MME3_CTRL_BASE 0x7FFC1E0AB0ull
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#define SHADOW_2_AGU_O_REMOTE_MME3_CTRL_MAX_OFFSET 0x2400
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#define SHADOW_2_AGU_O_REMOTE_MME3_CTRL_SECTION 0x2400
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#define mmSHADOW_2_DESC_MME3_CTRL_BASE 0x7FFC1E0AD4ull
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#define SHADOW_2_DESC_MME3_CTRL_MAX_OFFSET 0x5400
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#define SHADOW_2_DESC_MME3_CTRL_SECTION 0xB400
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#define mmSHADOW_3_MME3_CTRL_BASE 0x7FFC1E0B88ull
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#define SHADOW_3_MME3_CTRL_MAX_OFFSET 0x3400
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#define SHADOW_3_MME3_CTRL_SECTION 0x3400
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#define mmSHADOW_3_TENSOR_S_MME3_CTRL_BASE 0x7FFC1E0BBCull
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#define SHADOW_3_TENSOR_S_MME3_CTRL_MAX_OFFSET 0x4C00
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#define SHADOW_3_TENSOR_S_MME3_CTRL_SECTION 0x4C00
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#define mmSHADOW_3_AGU_S_MME3_CTRL_BASE 0x7FFC1E0C08ull
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#define SHADOW_3_AGU_S_MME3_CTRL_MAX_OFFSET 0x2400
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#define SHADOW_3_AGU_S_MME3_CTRL_SECTION 0x2400
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#define mmSHADOW_3_TENSOR_L_MME3_CTRL_BASE 0x7FFC1E0C2Cull
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#define SHADOW_3_TENSOR_L_MME3_CTRL_MAX_OFFSET 0x4C00
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#define SHADOW_3_TENSOR_L_MME3_CTRL_SECTION 0x4C00
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#define mmSHADOW_3_AGU_L_LOCAL_MME3_CTRL_BASE 0x7FFC1E0C78ull
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#define SHADOW_3_AGU_L_LOCAL_MME3_CTRL_MAX_OFFSET 0x2400
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#define SHADOW_3_AGU_L_LOCAL_MME3_CTRL_SECTION 0x2400
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#define mmSHADOW_3_AGU_L_REMOTE_MME3_CTRL_BASE 0x7FFC1E0C9Cull
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#define SHADOW_3_AGU_L_REMOTE_MME3_CTRL_MAX_OFFSET 0x2400
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#define SHADOW_3_AGU_L_REMOTE_MME3_CTRL_SECTION 0x2400
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#define mmSHADOW_3_TENSOR_O_MME3_CTRL_BASE 0x7FFC1E0CC0ull
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#define SHADOW_3_TENSOR_O_MME3_CTRL_MAX_OFFSET 0x4C00
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#define SHADOW_3_TENSOR_O_MME3_CTRL_SECTION 0x4C00
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#define mmSHADOW_3_AGU_O_LOCAL_MME3_CTRL_BASE 0x7FFC1E0D0Cull
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#define SHADOW_3_AGU_O_LOCAL_MME3_CTRL_MAX_OFFSET 0x2400
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#define SHADOW_3_AGU_O_LOCAL_MME3_CTRL_SECTION 0x2400
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#define mmSHADOW_3_AGU_O_REMOTE_MME3_CTRL_BASE 0x7FFC1E0D30ull
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#define SHADOW_3_AGU_O_REMOTE_MME3_CTRL_MAX_OFFSET 0x2400
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#define SHADOW_3_AGU_O_REMOTE_MME3_CTRL_SECTION 0x2400
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#define mmSHADOW_3_DESC_MME3_CTRL_BASE 0x7FFC1E0D54ull
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#define SHADOW_3_DESC_MME3_CTRL_MAX_OFFSET 0x5400
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#define SHADOW_3_DESC_MME3_CTRL_SECTION 0x72AC
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#define mmMME3_QM_BASE 0x7FFC1E8000ull
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#define MME3_QM_MAX_OFFSET 0xD040
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#define MME3_QM_SECTION 0x18000
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|
#define mmSRAM_Y0_X0_BANK_BASE 0x7FFC200000ull
|
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#define SRAM_Y0_X0_BANK_MAX_OFFSET 0x4000
|
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#define SRAM_Y0_X0_BANK_SECTION 0x1000
|
|
#define mmSRAM_Y0_X0_RTR_BASE 0x7FFC201000ull
|
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#define SRAM_Y0_X0_RTR_MAX_OFFSET 0x3340
|
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#define SRAM_Y0_X0_RTR_SECTION 0x7000
|
|
#define mmSRAM_Y0_X1_BANK_BASE 0x7FFC208000ull
|
|
#define SRAM_Y0_X1_BANK_MAX_OFFSET 0x4000
|
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#define SRAM_Y0_X1_BANK_SECTION 0x1000
|
|
#define mmSRAM_Y0_X1_RTR_BASE 0x7FFC209000ull
|
|
#define SRAM_Y0_X1_RTR_MAX_OFFSET 0x3340
|
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#define SRAM_Y0_X1_RTR_SECTION 0x7000
|
|
#define mmSRAM_Y0_X2_BANK_BASE 0x7FFC210000ull
|
|
#define SRAM_Y0_X2_BANK_MAX_OFFSET 0x4000
|
|
#define SRAM_Y0_X2_BANK_SECTION 0x1000
|
|
#define mmSRAM_Y0_X2_RTR_BASE 0x7FFC211000ull
|
|
#define SRAM_Y0_X2_RTR_MAX_OFFSET 0x3340
|
|
#define SRAM_Y0_X2_RTR_SECTION 0x7000
|
|
#define mmSRAM_Y0_X3_BANK_BASE 0x7FFC218000ull
|
|
#define SRAM_Y0_X3_BANK_MAX_OFFSET 0x4000
|
|
#define SRAM_Y0_X3_BANK_SECTION 0x1000
|
|
#define mmSRAM_Y0_X3_RTR_BASE 0x7FFC219000ull
|
|
#define SRAM_Y0_X3_RTR_MAX_OFFSET 0x3340
|
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#define SRAM_Y0_X3_RTR_SECTION 0x7000
|
|
#define mmSRAM_Y0_X4_BANK_BASE 0x7FFC220000ull
|
|
#define SRAM_Y0_X4_BANK_MAX_OFFSET 0x4000
|
|
#define SRAM_Y0_X4_BANK_SECTION 0x1000
|
|
#define mmSRAM_Y0_X4_RTR_BASE 0x7FFC221000ull
|
|
#define SRAM_Y0_X4_RTR_MAX_OFFSET 0x3340
|
|
#define SRAM_Y0_X4_RTR_SECTION 0x7000
|
|
#define mmSRAM_Y0_X5_BANK_BASE 0x7FFC228000ull
|
|
#define SRAM_Y0_X5_BANK_MAX_OFFSET 0x4000
|
|
#define SRAM_Y0_X5_BANK_SECTION 0x1000
|
|
#define mmSRAM_Y0_X5_RTR_BASE 0x7FFC229000ull
|
|
#define SRAM_Y0_X5_RTR_MAX_OFFSET 0x3340
|
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#define SRAM_Y0_X5_RTR_SECTION 0x7000
|
|
#define mmSRAM_Y0_X6_BANK_BASE 0x7FFC230000ull
|
|
#define SRAM_Y0_X6_BANK_MAX_OFFSET 0x4000
|
|
#define SRAM_Y0_X6_BANK_SECTION 0x1000
|
|
#define mmSRAM_Y0_X6_RTR_BASE 0x7FFC231000ull
|
|
#define SRAM_Y0_X6_RTR_MAX_OFFSET 0x3340
|
|
#define SRAM_Y0_X6_RTR_SECTION 0x7000
|
|
#define mmSRAM_Y0_X7_BANK_BASE 0x7FFC238000ull
|
|
#define SRAM_Y0_X7_BANK_MAX_OFFSET 0x4000
|
|
#define SRAM_Y0_X7_BANK_SECTION 0x1000
|
|
#define mmSRAM_Y0_X7_RTR_BASE 0x7FFC239000ull
|
|
#define SRAM_Y0_X7_RTR_MAX_OFFSET 0x3340
|
|
#define SRAM_Y0_X7_RTR_SECTION 0x7000
|
|
#define mmSRAM_Y1_X0_BANK_BASE 0x7FFC240000ull
|
|
#define SRAM_Y1_X0_BANK_MAX_OFFSET 0x4000
|
|
#define SRAM_Y1_X0_BANK_SECTION 0x1000
|
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#define mmSRAM_Y1_X0_RTR_BASE 0x7FFC241000ull
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#define SRAM_Y1_X0_RTR_MAX_OFFSET 0x3340
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#define SRAM_Y1_X0_RTR_SECTION 0x7000
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#define mmSRAM_Y1_X1_BANK_BASE 0x7FFC248000ull
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#define SRAM_Y1_X1_BANK_MAX_OFFSET 0x4000
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#define SRAM_Y1_X1_BANK_SECTION 0x1000
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#define mmSRAM_Y1_X1_RTR_BASE 0x7FFC249000ull
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#define SRAM_Y1_X1_RTR_MAX_OFFSET 0x3340
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#define SRAM_Y1_X1_RTR_SECTION 0x7000
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#define mmSRAM_Y1_X2_BANK_BASE 0x7FFC250000ull
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#define SRAM_Y1_X2_BANK_MAX_OFFSET 0x4000
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#define SRAM_Y1_X2_BANK_SECTION 0x1000
|
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#define mmSRAM_Y1_X2_RTR_BASE 0x7FFC251000ull
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#define SRAM_Y1_X2_RTR_MAX_OFFSET 0x3340
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#define SRAM_Y1_X2_RTR_SECTION 0x7000
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#define mmSRAM_Y1_X3_BANK_BASE 0x7FFC258000ull
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#define SRAM_Y1_X3_BANK_MAX_OFFSET 0x4000
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#define SRAM_Y1_X3_BANK_SECTION 0x1000
|
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#define mmSRAM_Y1_X3_RTR_BASE 0x7FFC259000ull
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#define SRAM_Y1_X3_RTR_MAX_OFFSET 0x3340
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#define SRAM_Y1_X3_RTR_SECTION 0x7000
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#define mmSRAM_Y1_X4_BANK_BASE 0x7FFC260000ull
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#define SRAM_Y1_X4_BANK_MAX_OFFSET 0x4000
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#define SRAM_Y1_X4_BANK_SECTION 0x1000
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#define mmSRAM_Y1_X4_RTR_BASE 0x7FFC261000ull
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#define SRAM_Y1_X4_RTR_MAX_OFFSET 0x3340
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#define SRAM_Y1_X4_RTR_SECTION 0x7000
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#define mmSRAM_Y1_X5_BANK_BASE 0x7FFC268000ull
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#define SRAM_Y1_X5_BANK_MAX_OFFSET 0x4000
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#define SRAM_Y1_X5_BANK_SECTION 0x1000
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#define mmSRAM_Y1_X5_RTR_BASE 0x7FFC269000ull
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#define SRAM_Y1_X5_RTR_MAX_OFFSET 0x3340
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#define SRAM_Y1_X5_RTR_SECTION 0x7000
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#define mmSRAM_Y1_X6_BANK_BASE 0x7FFC270000ull
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#define SRAM_Y1_X6_BANK_MAX_OFFSET 0x4000
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#define SRAM_Y1_X6_BANK_SECTION 0x1000
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#define mmSRAM_Y1_X6_RTR_BASE 0x7FFC271000ull
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#define SRAM_Y1_X6_RTR_MAX_OFFSET 0x3340
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#define SRAM_Y1_X6_RTR_SECTION 0x7000
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#define mmSRAM_Y1_X7_BANK_BASE 0x7FFC278000ull
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#define SRAM_Y1_X7_BANK_MAX_OFFSET 0x4000
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#define SRAM_Y1_X7_BANK_SECTION 0x1000
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#define mmSRAM_Y1_X7_RTR_BASE 0x7FFC279000ull
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#define SRAM_Y1_X7_RTR_MAX_OFFSET 0x3340
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#define SRAM_Y1_X7_RTR_SECTION 0x7000
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#define mmSRAM_Y2_X0_BANK_BASE 0x7FFC280000ull
|
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#define SRAM_Y2_X0_BANK_MAX_OFFSET 0x4000
|
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#define SRAM_Y2_X0_BANK_SECTION 0x1000
|
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#define mmSRAM_Y2_X0_RTR_BASE 0x7FFC281000ull
|
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#define SRAM_Y2_X0_RTR_MAX_OFFSET 0x3340
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#define SRAM_Y2_X0_RTR_SECTION 0x7000
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#define mmSRAM_Y2_X1_BANK_BASE 0x7FFC288000ull
|
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#define SRAM_Y2_X1_BANK_MAX_OFFSET 0x4000
|
|
#define SRAM_Y2_X1_BANK_SECTION 0x1000
|
|
#define mmSRAM_Y2_X1_RTR_BASE 0x7FFC289000ull
|
|
#define SRAM_Y2_X1_RTR_MAX_OFFSET 0x3340
|
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#define SRAM_Y2_X1_RTR_SECTION 0x7000
|
|
#define mmSRAM_Y2_X2_BANK_BASE 0x7FFC290000ull
|
|
#define SRAM_Y2_X2_BANK_MAX_OFFSET 0x4000
|
|
#define SRAM_Y2_X2_BANK_SECTION 0x1000
|
|
#define mmSRAM_Y2_X2_RTR_BASE 0x7FFC291000ull
|
|
#define SRAM_Y2_X2_RTR_MAX_OFFSET 0x3340
|
|
#define SRAM_Y2_X2_RTR_SECTION 0x7000
|
|
#define mmSRAM_Y2_X3_BANK_BASE 0x7FFC298000ull
|
|
#define SRAM_Y2_X3_BANK_MAX_OFFSET 0x4000
|
|
#define SRAM_Y2_X3_BANK_SECTION 0x1000
|
|
#define mmSRAM_Y2_X3_RTR_BASE 0x7FFC299000ull
|
|
#define SRAM_Y2_X3_RTR_MAX_OFFSET 0x3340
|
|
#define SRAM_Y2_X3_RTR_SECTION 0x7000
|
|
#define mmSRAM_Y2_X4_BANK_BASE 0x7FFC2A0000ull
|
|
#define SRAM_Y2_X4_BANK_MAX_OFFSET 0x4000
|
|
#define SRAM_Y2_X4_BANK_SECTION 0x1000
|
|
#define mmSRAM_Y2_X4_RTR_BASE 0x7FFC2A1000ull
|
|
#define SRAM_Y2_X4_RTR_MAX_OFFSET 0x3340
|
|
#define SRAM_Y2_X4_RTR_SECTION 0x7000
|
|
#define mmSRAM_Y2_X5_BANK_BASE 0x7FFC2A8000ull
|
|
#define SRAM_Y2_X5_BANK_MAX_OFFSET 0x4000
|
|
#define SRAM_Y2_X5_BANK_SECTION 0x1000
|
|
#define mmSRAM_Y2_X5_RTR_BASE 0x7FFC2A9000ull
|
|
#define SRAM_Y2_X5_RTR_MAX_OFFSET 0x3340
|
|
#define SRAM_Y2_X5_RTR_SECTION 0x7000
|
|
#define mmSRAM_Y2_X6_BANK_BASE 0x7FFC2B0000ull
|
|
#define SRAM_Y2_X6_BANK_MAX_OFFSET 0x4000
|
|
#define SRAM_Y2_X6_BANK_SECTION 0x1000
|
|
#define mmSRAM_Y2_X6_RTR_BASE 0x7FFC2B1000ull
|
|
#define SRAM_Y2_X6_RTR_MAX_OFFSET 0x3340
|
|
#define SRAM_Y2_X6_RTR_SECTION 0x7000
|
|
#define mmSRAM_Y2_X7_BANK_BASE 0x7FFC2B8000ull
|
|
#define SRAM_Y2_X7_BANK_MAX_OFFSET 0x4000
|
|
#define SRAM_Y2_X7_BANK_SECTION 0x1000
|
|
#define mmSRAM_Y2_X7_RTR_BASE 0x7FFC2B9000ull
|
|
#define SRAM_Y2_X7_RTR_MAX_OFFSET 0x3340
|
|
#define SRAM_Y2_X7_RTR_SECTION 0x7000
|
|
#define mmSRAM_Y3_X0_BANK_BASE 0x7FFC2C0000ull
|
|
#define SRAM_Y3_X0_BANK_MAX_OFFSET 0x4000
|
|
#define SRAM_Y3_X0_BANK_SECTION 0x1000
|
|
#define mmSRAM_Y3_X0_RTR_BASE 0x7FFC2C1000ull
|
|
#define SRAM_Y3_X0_RTR_MAX_OFFSET 0x3340
|
|
#define SRAM_Y3_X0_RTR_SECTION 0x7000
|
|
#define mmSRAM_Y3_X1_BANK_BASE 0x7FFC2C8000ull
|
|
#define SRAM_Y3_X1_BANK_MAX_OFFSET 0x4000
|
|
#define SRAM_Y3_X1_BANK_SECTION 0x1000
|
|
#define mmSRAM_Y3_X1_RTR_BASE 0x7FFC2C9000ull
|
|
#define SRAM_Y3_X1_RTR_MAX_OFFSET 0x3340
|
|
#define SRAM_Y3_X1_RTR_SECTION 0x7000
|
|
#define mmSRAM_Y3_X2_BANK_BASE 0x7FFC2D0000ull
|
|
#define SRAM_Y3_X2_BANK_MAX_OFFSET 0x4000
|
|
#define SRAM_Y3_X2_BANK_SECTION 0x1000
|
|
#define mmSRAM_Y3_X2_RTR_BASE 0x7FFC2D1000ull
|
|
#define SRAM_Y3_X2_RTR_MAX_OFFSET 0x3340
|
|
#define SRAM_Y3_X2_RTR_SECTION 0x7000
|
|
#define mmSRAM_Y3_X3_BANK_BASE 0x7FFC2D8000ull
|
|
#define SRAM_Y3_X3_BANK_MAX_OFFSET 0x4000
|
|
#define SRAM_Y3_X3_BANK_SECTION 0x1000
|
|
#define mmSRAM_Y3_X3_RTR_BASE 0x7FFC2D9000ull
|
|
#define SRAM_Y3_X3_RTR_MAX_OFFSET 0x3340
|
|
#define SRAM_Y3_X3_RTR_SECTION 0x7000
|
|
#define mmSRAM_Y3_X4_BANK_BASE 0x7FFC2E0000ull
|
|
#define SRAM_Y3_X4_BANK_MAX_OFFSET 0x4000
|
|
#define SRAM_Y3_X4_BANK_SECTION 0x1000
|
|
#define mmSRAM_Y3_X4_RTR_BASE 0x7FFC2E1000ull
|
|
#define SRAM_Y3_X4_RTR_MAX_OFFSET 0x3340
|
|
#define SRAM_Y3_X4_RTR_SECTION 0x7000
|
|
#define mmSRAM_Y3_X5_BANK_BASE 0x7FFC2E8000ull
|
|
#define SRAM_Y3_X5_BANK_MAX_OFFSET 0x4000
|
|
#define SRAM_Y3_X5_BANK_SECTION 0x1000
|
|
#define mmSRAM_Y3_X5_RTR_BASE 0x7FFC2E9000ull
|
|
#define SRAM_Y3_X5_RTR_MAX_OFFSET 0x3340
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|
#define SRAM_Y3_X5_RTR_SECTION 0x7000
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|
#define mmSRAM_Y3_X6_BANK_BASE 0x7FFC2F0000ull
|
|
#define SRAM_Y3_X6_BANK_MAX_OFFSET 0x4000
|
|
#define SRAM_Y3_X6_BANK_SECTION 0x1000
|
|
#define mmSRAM_Y3_X6_RTR_BASE 0x7FFC2F1000ull
|
|
#define SRAM_Y3_X6_RTR_MAX_OFFSET 0x3340
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|
#define SRAM_Y3_X6_RTR_SECTION 0x7000
|
|
#define mmSRAM_Y3_X7_BANK_BASE 0x7FFC2F8000ull
|
|
#define SRAM_Y3_X7_BANK_MAX_OFFSET 0x4000
|
|
#define SRAM_Y3_X7_BANK_SECTION 0x1000
|
|
#define mmSRAM_Y3_X7_RTR_BASE 0x7FFC2F9000ull
|
|
#define SRAM_Y3_X7_RTR_MAX_OFFSET 0x3340
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|
#define SRAM_Y3_X7_RTR_SECTION 0x7000
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|
#define mmSIF_RTR_0_BASE 0x7FFC300000ull
|
|
#define SIF_RTR_0_MAX_OFFSET 0x6500
|
|
#define SIF_RTR_0_SECTION 0x6000
|
|
#define mmSIF_RTR_CTRL_0_BASE 0x7FFC306000ull
|
|
#define SIF_RTR_CTRL_0_MAX_OFFSET 0xCC00
|
|
#define SIF_RTR_CTRL_0_SECTION 0xA000
|
|
#define mmSIF_RTR_1_BASE 0x7FFC310000ull
|
|
#define SIF_RTR_1_MAX_OFFSET 0x6500
|
|
#define SIF_RTR_1_SECTION 0x6000
|
|
#define mmSIF_RTR_CTRL_1_BASE 0x7FFC316000ull
|
|
#define SIF_RTR_CTRL_1_MAX_OFFSET 0xCC00
|
|
#define SIF_RTR_CTRL_1_SECTION 0xA000
|
|
#define mmSIF_RTR_2_BASE 0x7FFC320000ull
|
|
#define SIF_RTR_2_MAX_OFFSET 0x6500
|
|
#define SIF_RTR_2_SECTION 0x6000
|
|
#define mmSIF_RTR_CTRL_2_BASE 0x7FFC326000ull
|
|
#define SIF_RTR_CTRL_2_MAX_OFFSET 0xCC00
|
|
#define SIF_RTR_CTRL_2_SECTION 0xA000
|
|
#define mmSIF_RTR_3_BASE 0x7FFC330000ull
|
|
#define SIF_RTR_3_MAX_OFFSET 0x6500
|
|
#define SIF_RTR_3_SECTION 0x6000
|
|
#define mmSIF_RTR_CTRL_3_BASE 0x7FFC336000ull
|
|
#define SIF_RTR_CTRL_3_MAX_OFFSET 0xCC00
|
|
#define SIF_RTR_CTRL_3_SECTION 0xA000
|
|
#define mmSIF_RTR_4_BASE 0x7FFC340000ull
|
|
#define SIF_RTR_4_MAX_OFFSET 0x6500
|
|
#define SIF_RTR_4_SECTION 0x6000
|
|
#define mmSIF_RTR_CTRL_4_BASE 0x7FFC346000ull
|
|
#define SIF_RTR_CTRL_4_MAX_OFFSET 0xCC00
|
|
#define SIF_RTR_CTRL_4_SECTION 0xA000
|
|
#define mmSIF_RTR_5_BASE 0x7FFC350000ull
|
|
#define SIF_RTR_5_MAX_OFFSET 0x6500
|
|
#define SIF_RTR_5_SECTION 0x6000
|
|
#define mmSIF_RTR_CTRL_5_BASE 0x7FFC356000ull
|
|
#define SIF_RTR_CTRL_5_MAX_OFFSET 0xCC00
|
|
#define SIF_RTR_CTRL_5_SECTION 0xA000
|
|
#define mmSIF_RTR_6_BASE 0x7FFC360000ull
|
|
#define SIF_RTR_6_MAX_OFFSET 0x6500
|
|
#define SIF_RTR_6_SECTION 0x6000
|
|
#define mmSIF_RTR_CTRL_6_BASE 0x7FFC366000ull
|
|
#define SIF_RTR_CTRL_6_MAX_OFFSET 0xCC00
|
|
#define SIF_RTR_CTRL_6_SECTION 0xA000
|
|
#define mmSIF_RTR_7_BASE 0x7FFC370000ull
|
|
#define SIF_RTR_7_MAX_OFFSET 0x6500
|
|
#define SIF_RTR_7_SECTION 0x6000
|
|
#define mmSIF_RTR_CTRL_7_BASE 0x7FFC376000ull
|
|
#define SIF_RTR_CTRL_7_MAX_OFFSET 0xCC00
|
|
#define SIF_RTR_CTRL_7_SECTION 0xA000
|
|
#define mmNIF_RTR_0_BASE 0x7FFC380000ull
|
|
#define NIF_RTR_0_MAX_OFFSET 0x6500
|
|
#define NIF_RTR_0_SECTION 0x6000
|
|
#define mmNIF_RTR_CTRL_0_BASE 0x7FFC386000ull
|
|
#define NIF_RTR_CTRL_0_MAX_OFFSET 0xCC00
|
|
#define NIF_RTR_CTRL_0_SECTION 0xA000
|
|
#define mmNIF_RTR_1_BASE 0x7FFC390000ull
|
|
#define NIF_RTR_1_MAX_OFFSET 0x6500
|
|
#define NIF_RTR_1_SECTION 0x6000
|
|
#define mmNIF_RTR_CTRL_1_BASE 0x7FFC396000ull
|
|
#define NIF_RTR_CTRL_1_MAX_OFFSET 0xCC00
|
|
#define NIF_RTR_CTRL_1_SECTION 0xA000
|
|
#define mmNIF_RTR_2_BASE 0x7FFC3A0000ull
|
|
#define NIF_RTR_2_MAX_OFFSET 0x6500
|
|
#define NIF_RTR_2_SECTION 0x6000
|
|
#define mmNIF_RTR_CTRL_2_BASE 0x7FFC3A6000ull
|
|
#define NIF_RTR_CTRL_2_MAX_OFFSET 0xCC00
|
|
#define NIF_RTR_CTRL_2_SECTION 0xA000
|
|
#define mmNIF_RTR_3_BASE 0x7FFC3B0000ull
|
|
#define NIF_RTR_3_MAX_OFFSET 0x6500
|
|
#define NIF_RTR_3_SECTION 0x6000
|
|
#define mmNIF_RTR_CTRL_3_BASE 0x7FFC3B6000ull
|
|
#define NIF_RTR_CTRL_3_MAX_OFFSET 0xCC00
|
|
#define NIF_RTR_CTRL_3_SECTION 0xA000
|
|
#define mmNIF_RTR_4_BASE 0x7FFC3C0000ull
|
|
#define NIF_RTR_4_MAX_OFFSET 0x6500
|
|
#define NIF_RTR_4_SECTION 0x6000
|
|
#define mmNIF_RTR_CTRL_4_BASE 0x7FFC3C6000ull
|
|
#define NIF_RTR_CTRL_4_MAX_OFFSET 0xCC00
|
|
#define NIF_RTR_CTRL_4_SECTION 0xA000
|
|
#define mmNIF_RTR_5_BASE 0x7FFC3D0000ull
|
|
#define NIF_RTR_5_MAX_OFFSET 0x6500
|
|
#define NIF_RTR_5_SECTION 0x6000
|
|
#define mmNIF_RTR_CTRL_5_BASE 0x7FFC3D6000ull
|
|
#define NIF_RTR_CTRL_5_MAX_OFFSET 0xCC00
|
|
#define NIF_RTR_CTRL_5_SECTION 0xA000
|
|
#define mmNIF_RTR_6_BASE 0x7FFC3E0000ull
|
|
#define NIF_RTR_6_MAX_OFFSET 0x6500
|
|
#define NIF_RTR_6_SECTION 0x6000
|
|
#define mmNIF_RTR_CTRL_6_BASE 0x7FFC3E6000ull
|
|
#define NIF_RTR_CTRL_6_MAX_OFFSET 0xCC00
|
|
#define NIF_RTR_CTRL_6_SECTION 0xA000
|
|
#define mmNIF_RTR_7_BASE 0x7FFC3F0000ull
|
|
#define NIF_RTR_7_MAX_OFFSET 0x6500
|
|
#define NIF_RTR_7_SECTION 0x6000
|
|
#define mmNIF_RTR_CTRL_7_BASE 0x7FFC3F6000ull
|
|
#define NIF_RTR_CTRL_7_MAX_OFFSET 0xCC00
|
|
#define NIF_RTR_CTRL_7_SECTION 0x4B000
|
|
#define mmCPU_CA53_CFG_BASE 0x7FFC441000ull
|
|
#define CPU_CA53_CFG_MAX_OFFSET 0x2180
|
|
#define CPU_CA53_CFG_SECTION 0x1000
|
|
#define mmCPU_IF_BASE 0x7FFC442000ull
|
|
#define CPU_IF_MAX_OFFSET 0x43C0
|
|
#define CPU_IF_SECTION 0x2000
|
|
#define mmCPU_TIMESTAMP_BASE 0x7FFC444000ull
|
|
#define CPU_TIMESTAMP_MAX_OFFSET 0x1000
|
|
#define CPU_TIMESTAMP_SECTION 0x3C000
|
|
#define mmDMA_IF_W_S_BASE 0x7FFC480000ull
|
|
#define DMA_IF_W_S_MAX_OFFSET 0x8380
|
|
#define DMA_IF_W_S_SECTION 0x1000
|
|
#define mmDMA_IF_W_S_DOWN_CH0_BASE 0x7FFC481000ull
|
|
#define DMA_IF_W_S_DOWN_CH0_MAX_OFFSET 0xCC00
|
|
#define DMA_IF_W_S_DOWN_CH0_SECTION 0x1000
|
|
#define mmDMA_IF_W_S_DOWN_CH1_BASE 0x7FFC482000ull
|
|
#define DMA_IF_W_S_DOWN_CH1_MAX_OFFSET 0xCC00
|
|
#define DMA_IF_W_S_DOWN_CH1_SECTION 0x5000
|
|
#define mmDMA_W_PLL_BASE 0x7FFC487000ull
|
|
#define DMA_W_PLL_MAX_OFFSET 0x5200
|
|
#define DMA_W_PLL_SECTION 0x1000
|
|
#define mmIF_W_PLL_BASE 0x7FFC488000ull
|
|
#define IF_W_PLL_MAX_OFFSET 0x5200
|
|
#define IF_W_PLL_SECTION 0x1000
|
|
#define mmDMA_IF_W_S_DOWN_BASE 0x7FFC489000ull
|
|
#define DMA_IF_W_S_DOWN_MAX_OFFSET 0x1500
|
|
#define DMA_IF_W_S_DOWN_SECTION 0x7000
|
|
#define mmSYNC_MNGR_GLBL_W_S_BASE 0x7FFC490000ull
|
|
#define SYNC_MNGR_GLBL_W_S_MAX_OFFSET 0x6C00
|
|
#define SYNC_MNGR_GLBL_W_S_SECTION 0x1000
|
|
#define mmSYNC_MNGR_OBJS_W_S_BASE 0x7FFC491000ull
|
|
#define SYNC_MNGR_OBJS_W_S_MAX_OFFSET 0x5C00
|
|
#define SYNC_MNGR_OBJS_W_S_SECTION 0xF000
|
|
#define mmDMA_IF_E_S_BASE 0x7FFC4A0000ull
|
|
#define DMA_IF_E_S_MAX_OFFSET 0x8380
|
|
#define DMA_IF_E_S_SECTION 0x1000
|
|
#define mmDMA_IF_E_S_DOWN_CH0_BASE 0x7FFC4A1000ull
|
|
#define DMA_IF_E_S_DOWN_CH0_MAX_OFFSET 0xCC00
|
|
#define DMA_IF_E_S_DOWN_CH0_SECTION 0x1000
|
|
#define mmDMA_IF_E_S_DOWN_CH1_BASE 0x7FFC4A2000ull
|
|
#define DMA_IF_E_S_DOWN_CH1_MAX_OFFSET 0xCC00
|
|
#define DMA_IF_E_S_DOWN_CH1_SECTION 0x5000
|
|
#define mmIF_E_PLL_BASE 0x7FFC4A7000ull
|
|
#define IF_E_PLL_MAX_OFFSET 0x5200
|
|
#define IF_E_PLL_SECTION 0x1000
|
|
#define mmDMA_E_PLL_BASE 0x7FFC4A8000ull
|
|
#define DMA_E_PLL_MAX_OFFSET 0x5200
|
|
#define DMA_E_PLL_SECTION 0x1000
|
|
#define mmDMA_IF_E_S_DOWN_BASE 0x7FFC4A9000ull
|
|
#define DMA_IF_E_S_DOWN_MAX_OFFSET 0x1500
|
|
#define DMA_IF_E_S_DOWN_SECTION 0x7000
|
|
#define mmSYNC_MNGR_GLBL_E_S_BASE 0x7FFC4B0000ull
|
|
#define SYNC_MNGR_GLBL_E_S_MAX_OFFSET 0x6C00
|
|
#define SYNC_MNGR_GLBL_E_S_SECTION 0x1000
|
|
#define mmSYNC_MNGR_OBJS_E_S_BASE 0x7FFC4B1000ull
|
|
#define SYNC_MNGR_OBJS_E_S_MAX_OFFSET 0x5C00
|
|
#define SYNC_MNGR_OBJS_E_S_SECTION 0xF000
|
|
#define mmDMA_IF_W_N_BASE 0x7FFC4C0000ull
|
|
#define DMA_IF_W_N_MAX_OFFSET 0x8380
|
|
#define DMA_IF_W_N_SECTION 0x1000
|
|
#define mmDMA_IF_W_N_DOWN_CH0_BASE 0x7FFC4C1000ull
|
|
#define DMA_IF_W_N_DOWN_CH0_MAX_OFFSET 0xCC00
|
|
#define DMA_IF_W_N_DOWN_CH0_SECTION 0x1000
|
|
#define mmDMA_IF_W_N_DOWN_CH1_BASE 0x7FFC4C2000ull
|
|
#define DMA_IF_W_N_DOWN_CH1_MAX_OFFSET 0xCC00
|
|
#define DMA_IF_W_N_DOWN_CH1_SECTION 0x5000
|
|
#define mmMESH_W_PLL_BASE 0x7FFC4C7000ull
|
|
#define MESH_W_PLL_MAX_OFFSET 0x5200
|
|
#define MESH_W_PLL_SECTION 0x1000
|
|
#define mmSRAM_W_PLL_BASE 0x7FFC4C8000ull
|
|
#define SRAM_W_PLL_MAX_OFFSET 0x5200
|
|
#define SRAM_W_PLL_SECTION 0x1000
|
|
#define mmDMA_IF_W_N_DOWN_BASE 0x7FFC4C9000ull
|
|
#define DMA_IF_W_N_DOWN_MAX_OFFSET 0x1500
|
|
#define DMA_IF_W_N_DOWN_SECTION 0x7000
|
|
#define mmSYNC_MNGR_GLBL_W_N_BASE 0x7FFC4D0000ull
|
|
#define SYNC_MNGR_GLBL_W_N_MAX_OFFSET 0x6C00
|
|
#define SYNC_MNGR_GLBL_W_N_SECTION 0x1000
|
|
#define mmSYNC_MNGR_OBJS_W_N_BASE 0x7FFC4D1000ull
|
|
#define SYNC_MNGR_OBJS_W_N_MAX_OFFSET 0x5C00
|
|
#define SYNC_MNGR_OBJS_W_N_SECTION 0xF000
|
|
#define mmDMA_IF_E_N_BASE 0x7FFC4E0000ull
|
|
#define DMA_IF_E_N_MAX_OFFSET 0x8380
|
|
#define DMA_IF_E_N_SECTION 0x1000
|
|
#define mmDMA_IF_E_N_DOWN_CH0_BASE 0x7FFC4E1000ull
|
|
#define DMA_IF_E_N_DOWN_CH0_MAX_OFFSET 0xCC00
|
|
#define DMA_IF_E_N_DOWN_CH0_SECTION 0x1000
|
|
#define mmDMA_IF_E_N_DOWN_CH1_BASE 0x7FFC4E2000ull
|
|
#define DMA_IF_E_N_DOWN_CH1_MAX_OFFSET 0xCC00
|
|
#define DMA_IF_E_N_DOWN_CH1_SECTION 0x5000
|
|
#define mmMESH_E_PLL_BASE 0x7FFC4E7000ull
|
|
#define MESH_E_PLL_MAX_OFFSET 0x5200
|
|
#define MESH_E_PLL_SECTION 0x1000
|
|
#define mmSRAM_E_PLL_BASE 0x7FFC4E8000ull
|
|
#define SRAM_E_PLL_MAX_OFFSET 0x5200
|
|
#define SRAM_E_PLL_SECTION 0x1000
|
|
#define mmDMA_IF_E_N_DOWN_BASE 0x7FFC4E9000ull
|
|
#define DMA_IF_E_N_DOWN_MAX_OFFSET 0x1500
|
|
#define DMA_IF_E_N_DOWN_SECTION 0x7000
|
|
#define mmSYNC_MNGR_GLBL_E_N_BASE 0x7FFC4F0000ull
|
|
#define SYNC_MNGR_GLBL_E_N_MAX_OFFSET 0x6C00
|
|
#define SYNC_MNGR_GLBL_E_N_SECTION 0x1000
|
|
#define mmSYNC_MNGR_OBJS_E_N_BASE 0x7FFC4F1000ull
|
|
#define SYNC_MNGR_OBJS_E_N_MAX_OFFSET 0x5C00
|
|
#define SYNC_MNGR_OBJS_E_N_SECTION 0xF000
|
|
#define mmDMA0_CORE_BASE 0x7FFC500000ull
|
|
#define DMA0_CORE_MAX_OFFSET 0x23C0
|
|
#define DMA0_CORE_SECTION 0x8000
|
|
#define mmDMA0_QM_BASE 0x7FFC508000ull
|
|
#define DMA0_QM_MAX_OFFSET 0xD040
|
|
#define DMA0_QM_SECTION 0x18000
|
|
#define mmDMA1_CORE_BASE 0x7FFC520000ull
|
|
#define DMA1_CORE_MAX_OFFSET 0x23C0
|
|
#define DMA1_CORE_SECTION 0x8000
|
|
#define mmDMA1_QM_BASE 0x7FFC528000ull
|
|
#define DMA1_QM_MAX_OFFSET 0xD040
|
|
#define DMA1_QM_SECTION 0x18000
|
|
#define mmDMA2_CORE_BASE 0x7FFC540000ull
|
|
#define DMA2_CORE_MAX_OFFSET 0x23C0
|
|
#define DMA2_CORE_SECTION 0x8000
|
|
#define mmDMA2_QM_BASE 0x7FFC548000ull
|
|
#define DMA2_QM_MAX_OFFSET 0xD040
|
|
#define DMA2_QM_SECTION 0x18000
|
|
#define mmDMA3_CORE_BASE 0x7FFC560000ull
|
|
#define DMA3_CORE_MAX_OFFSET 0x23C0
|
|
#define DMA3_CORE_SECTION 0x8000
|
|
#define mmDMA3_QM_BASE 0x7FFC568000ull
|
|
#define DMA3_QM_MAX_OFFSET 0xD040
|
|
#define DMA3_QM_SECTION 0x18000
|
|
#define mmDMA4_CORE_BASE 0x7FFC580000ull
|
|
#define DMA4_CORE_MAX_OFFSET 0x23C0
|
|
#define DMA4_CORE_SECTION 0x8000
|
|
#define mmDMA4_QM_BASE 0x7FFC588000ull
|
|
#define DMA4_QM_MAX_OFFSET 0xD040
|
|
#define DMA4_QM_SECTION 0x18000
|
|
#define mmDMA5_CORE_BASE 0x7FFC5A0000ull
|
|
#define DMA5_CORE_MAX_OFFSET 0x23C0
|
|
#define DMA5_CORE_SECTION 0x8000
|
|
#define mmDMA5_QM_BASE 0x7FFC5A8000ull
|
|
#define DMA5_QM_MAX_OFFSET 0xD040
|
|
#define DMA5_QM_SECTION 0x18000
|
|
#define mmDMA6_CORE_BASE 0x7FFC5C0000ull
|
|
#define DMA6_CORE_MAX_OFFSET 0x23C0
|
|
#define DMA6_CORE_SECTION 0x8000
|
|
#define mmDMA6_QM_BASE 0x7FFC5C8000ull
|
|
#define DMA6_QM_MAX_OFFSET 0xD040
|
|
#define DMA6_QM_SECTION 0x18000
|
|
#define mmDMA7_CORE_BASE 0x7FFC5E0000ull
|
|
#define DMA7_CORE_MAX_OFFSET 0x23C0
|
|
#define DMA7_CORE_SECTION 0x8000
|
|
#define mmDMA7_QM_BASE 0x7FFC5E8000ull
|
|
#define DMA7_QM_MAX_OFFSET 0xD040
|
|
#define DMA7_QM_SECTION 0x18000
|
|
#define mmHBM0_BASE 0x7FFC600000ull
|
|
#define HBM0_MAX_OFFSET 0x8F58
|
|
#define HBM0_SECTION 0x80000
|
|
#define mmHBM1_BASE 0x7FFC680000ull
|
|
#define HBM1_MAX_OFFSET 0x8F58
|
|
#define HBM1_SECTION 0x80000
|
|
#define mmHBM2_BASE 0x7FFC700000ull
|
|
#define HBM2_MAX_OFFSET 0x8F58
|
|
#define HBM2_SECTION 0x80000
|
|
#define mmHBM3_BASE 0x7FFC780000ull
|
|
#define HBM3_MAX_OFFSET 0x8F58
|
|
#define HBM3_SECTION 0x80000
|
|
#define mmGIC_BASE 0x7FFC800000ull
|
|
#define GIC_MAX_OFFSET 0x10000
|
|
#define GIC_SECTION 0x401000
|
|
#define mmPCIE_WRAP_BASE 0x7FFCC01000ull
|
|
#define PCIE_WRAP_MAX_OFFSET 0xDF00
|
|
#define PCIE_WRAP_SECTION 0x1000
|
|
#define mmPCIE_DBI_BASE 0x7FFCC02000ull
|
|
#define PCIE_DBI_MAX_OFFSET 0xC040
|
|
#define PCIE_DBI_SECTION 0x2000
|
|
#define mmPCIE_CORE_BASE 0x7FFCC04000ull
|
|
#define PCIE_CORE_MAX_OFFSET 0x9BC0
|
|
#define PCIE_CORE_SECTION 0x3000
|
|
#define mmPCIE_AUX_BASE 0x7FFCC07000ull
|
|
#define PCIE_AUX_MAX_OFFSET 0x9C40
|
|
#define PCIE_AUX_SECTION 0x9000
|
|
#define mmPCIE_PHY_BASE 0x7FFCC10000ull
|
|
#define PCIE_PHY_MAX_OFFSET 0x9640
|
|
#define PCIE_PHY_SECTION 0x1000
|
|
#define mmMMU_UP_BASE 0x7FFCC11000ull
|
|
#define MMU_UP_MAX_OFFSET 0x7000
|
|
#define MMU_UP_SECTION 0x1000
|
|
#define mmSTLB_BASE 0x7FFCC12000ull
|
|
#define STLB_MAX_OFFSET 0x8800
|
|
#define STLB_SECTION 0x1000
|
|
#define mmPCIE_MSI_BASE 0x7FFCC13000ull
|
|
#define PCIE_MSI_MAX_OFFSET 0x8000
|
|
#define PCIE_MSI_SECTION 0x2D000
|
|
#define mmPSOC_I2C_M0_BASE 0x7FFCC40000ull
|
|
#define PSOC_I2C_M0_MAX_OFFSET 0x1000
|
|
#define PSOC_I2C_M0_SECTION 0x1000
|
|
#define mmPSOC_I2C_M1_BASE 0x7FFCC41000ull
|
|
#define PSOC_I2C_M1_MAX_OFFSET 0x1000
|
|
#define PSOC_I2C_M1_SECTION 0x1000
|
|
#define mmPSOC_I2C_S_BASE 0x7FFCC42000ull
|
|
#define PSOC_I2C_S_MAX_OFFSET 0x1000
|
|
#define PSOC_I2C_S_SECTION 0x1000
|
|
#define mmPSOC_SPI_BASE 0x7FFCC43000ull
|
|
#define PSOC_SPI_MAX_OFFSET 0x1000
|
|
#define PSOC_SPI_SECTION 0x2000
|
|
#define mmPSOC_UART_0_BASE 0x7FFCC45000ull
|
|
#define PSOC_UART_0_MAX_OFFSET 0x1000
|
|
#define PSOC_UART_0_SECTION 0x1000
|
|
#define mmPSOC_UART_1_BASE 0x7FFCC46000ull
|
|
#define PSOC_UART_1_MAX_OFFSET 0x1000
|
|
#define PSOC_UART_1_SECTION 0x1000
|
|
#define mmPSOC_TIMER_BASE 0x7FFCC47000ull
|
|
#define PSOC_TIMER_MAX_OFFSET 0x1000
|
|
#define PSOC_TIMER_SECTION 0x1000
|
|
#define mmPSOC_WDOG_BASE 0x7FFCC48000ull
|
|
#define PSOC_WDOG_MAX_OFFSET 0x1000
|
|
#define PSOC_WDOG_SECTION 0x1000
|
|
#define mmPSOC_TIMESTAMP_BASE 0x7FFCC49000ull
|
|
#define PSOC_TIMESTAMP_MAX_OFFSET 0x1000
|
|
#define PSOC_TIMESTAMP_SECTION 0x1000
|
|
#define mmPSOC_EFUSE_BASE 0x7FFCC4A000ull
|
|
#define PSOC_EFUSE_MAX_OFFSET 0x3040
|
|
#define PSOC_EFUSE_SECTION 0x1000
|
|
#define mmPSOC_GLOBAL_CONF_BASE 0x7FFCC4B000ull
|
|
#define PSOC_GLOBAL_CONF_MAX_OFFSET 0xCD80
|
|
#define PSOC_GLOBAL_CONF_SECTION 0x1000
|
|
#define mmPSOC_GPIO0_BASE 0x7FFCC4C000ull
|
|
#define PSOC_GPIO0_MAX_OFFSET 0x1000
|
|
#define PSOC_GPIO0_SECTION 0x1000
|
|
#define mmPSOC_GPIO1_BASE 0x7FFCC4D000ull
|
|
#define PSOC_GPIO1_MAX_OFFSET 0x1000
|
|
#define PSOC_GPIO1_SECTION 0x1000
|
|
#define mmPSOC_BTL_BASE 0x7FFCC4E000ull
|
|
#define PSOC_BTL_MAX_OFFSET 0x1480
|
|
#define PSOC_BTL_SECTION 0x1000
|
|
#define mmPSOC_CS_TRACE_BASE 0x7FFCC4F000ull
|
|
#define PSOC_CS_TRACE_MAX_OFFSET 0x1680
|
|
#define PSOC_CS_TRACE_SECTION 0x1000
|
|
#define mmPSOC_GPIO2_BASE 0x7FFCC50000ull
|
|
#define PSOC_GPIO2_MAX_OFFSET 0x1000
|
|
#define PSOC_GPIO2_SECTION 0x1000
|
|
#define mmPSOC_GPIO3_BASE 0x7FFCC51000ull
|
|
#define PSOC_GPIO3_MAX_OFFSET 0x1000
|
|
#define PSOC_GPIO3_SECTION 0x1000
|
|
#define mmPSOC_GPIO4_BASE 0x7FFCC52000ull
|
|
#define PSOC_GPIO4_MAX_OFFSET 0x1000
|
|
#define PSOC_GPIO4_SECTION 0x1000
|
|
#define mmPSOC_DFT_EFUSE_BASE 0x7FFCC53000ull
|
|
#define PSOC_DFT_EFUSE_MAX_OFFSET 0x3040
|
|
#define PSOC_DFT_EFUSE_SECTION 0x1000
|
|
#define mmPSOC_RPM_0_BASE 0x7FFCC54000ull
|
|
#define PSOC_RPM_0_MAX_OFFSET 0x8800
|
|
#define PSOC_RPM_0_SECTION 0x1000
|
|
#define mmPSOC_RPM_1_BASE 0x7FFCC55000ull
|
|
#define PSOC_RPM_1_MAX_OFFSET 0x8800
|
|
#define PSOC_RPM_1_SECTION 0x1000
|
|
#define mmPSOC_RPM_2_BASE 0x7FFCC56000ull
|
|
#define PSOC_RPM_2_MAX_OFFSET 0x8800
|
|
#define PSOC_RPM_2_SECTION 0x1000
|
|
#define mmPSOC_RPM_3_BASE 0x7FFCC57000ull
|
|
#define PSOC_RPM_3_MAX_OFFSET 0x8800
|
|
#define PSOC_RPM_3_SECTION 0x19000
|
|
#define mmPSOC_CPU_PLL_BASE 0x7FFCC70000ull
|
|
#define PSOC_CPU_PLL_MAX_OFFSET 0x5200
|
|
#define PSOC_CPU_PLL_SECTION 0x1000
|
|
#define mmPSOC_MME_PLL_BASE 0x7FFCC71000ull
|
|
#define PSOC_MME_PLL_MAX_OFFSET 0x5200
|
|
#define PSOC_MME_PLL_SECTION 0x1000
|
|
#define mmPSOC_PCI_PLL_BASE 0x7FFCC72000ull
|
|
#define PSOC_PCI_PLL_MAX_OFFSET 0x5200
|
|
#define PSOC_PCI_PLL_SECTION 0x1000
|
|
#define mmPSOC_TPC_PLL_BASE 0x7FFCC73000ull
|
|
#define PSOC_TPC_PLL_MAX_OFFSET 0x5200
|
|
#define PSOC_TPC_PLL_SECTION 0x1000
|
|
#define mmPSOC_HBM_PLL_BASE 0x7FFCC74000ull
|
|
#define PSOC_HBM_PLL_MAX_OFFSET 0x5200
|
|
#define PSOC_HBM_PLL_SECTION 0x1000
|
|
#define mmPSOC_PM_BASE 0x7FFCC75000ull
|
|
#define PSOC_PM_MAX_OFFSET 0x1F00
|
|
#define PSOC_PM_SECTION 0x1000
|
|
#define mmPSOC_TS_BASE 0x7FFCC76000ull
|
|
#define PSOC_TS_MAX_OFFSET 0xE640
|
|
#define PSOC_TS_SECTION 0x2000
|
|
#define mmPSOC_PWM0_BASE 0x7FFCC78000ull
|
|
#define PSOC_PWM0_MAX_OFFSET 0x5800
|
|
#define PSOC_PWM0_SECTION 0x1000
|
|
#define mmPSOC_PWM1_BASE 0x7FFCC79000ull
|
|
#define PSOC_PWM1_MAX_OFFSET 0x5800
|
|
#define PSOC_PWM1_SECTION 0x1000
|
|
#define mmPSOC_PWM2_BASE 0x7FFCC7A000ull
|
|
#define PSOC_PWM2_MAX_OFFSET 0x5800
|
|
#define PSOC_PWM2_SECTION 0x1000
|
|
#define mmPSOC_PWM3_BASE 0x7FFCC7B000ull
|
|
#define PSOC_PWM3_MAX_OFFSET 0x5800
|
|
#define PSOC_PWM3_SECTION 0x1000
|
|
#define mmPSOC_GPIO5_BASE 0x7FFCC7C000ull
|
|
#define PSOC_GPIO5_MAX_OFFSET 0x1000
|
|
#define PSOC_GPIO5_SECTION 0x1000
|
|
#define mmPSOC_GPIO6_BASE 0x7FFCC7D000ull
|
|
#define PSOC_GPIO6_MAX_OFFSET 0x1000
|
|
#define PSOC_GPIO6_SECTION 0x3000
|
|
#define mmPCIE_PMA_0_BASE 0x7FFCC80000ull
|
|
#define PCIE_PMA_0_MAX_OFFSET 0x10003
|
|
#define PCIE_PMA_0_SECTION 0x10000
|
|
#define mmPCIE_PMA_1_BASE 0x7FFCC90000ull
|
|
#define PCIE_PMA_1_MAX_OFFSET 0x10003
|
|
#define PCIE_PMA_1_SECTION 0x10000
|
|
#define mmPCIE_PMA_2_BASE 0x7FFCCA0000ull
|
|
#define PCIE_PMA_2_MAX_OFFSET 0x10003
|
|
#define PCIE_PMA_2_SECTION 0x10000
|
|
#define mmPCIE_PMA_3_BASE 0x7FFCCB0000ull
|
|
#define PCIE_PMA_3_MAX_OFFSET 0x10003
|
|
#define PCIE_PMA_3_SECTION 0x10000
|
|
#define mmNIC0_MAC_CH0_BASE 0x7FFCCC0000ull
|
|
#define NIC0_MAC_CH0_MAX_OFFSET 0x8400
|
|
#define NIC0_MAC_CH0_SECTION 0x1000
|
|
#define mmNIC0_MAC_CH1_BASE 0x7FFCCC1000ull
|
|
#define NIC0_MAC_CH1_MAX_OFFSET 0x8400
|
|
#define NIC0_MAC_CH1_SECTION 0x1000
|
|
#define mmNIC0_MAC_CH2_BASE 0x7FFCCC2000ull
|
|
#define NIC0_MAC_CH2_MAX_OFFSET 0x8400
|
|
#define NIC0_MAC_CH2_SECTION 0x1000
|
|
#define mmNIC0_MAC_CH3_BASE 0x7FFCCC3000ull
|
|
#define NIC0_MAC_CH3_MAX_OFFSET 0x8400
|
|
#define NIC0_MAC_CH3_SECTION 0x1000
|
|
#define mmNIC0_STAT_BASE 0x7FFCCC4000ull
|
|
#define NIC0_STAT_MAX_OFFSET 0x4D00
|
|
#define NIC0_STAT_SECTION 0x1000
|
|
#define mmNIC0_MAC_XPCS91_BASE 0x7FFCCC5000ull
|
|
#define NIC0_MAC_XPCS91_MAX_OFFSET 0x2380
|
|
#define NIC0_MAC_XPCS91_SECTION 0x3000
|
|
#define mmNIC0_MAC_CORE_BASE 0x7FFCCC8000ull
|
|
#define NIC0_MAC_CORE_MAX_OFFSET 0x5400
|
|
#define NIC0_MAC_CORE_SECTION 0x1000
|
|
#define mmNIC0_MAC_AUX_BASE 0x7FFCCC9000ull
|
|
#define NIC0_MAC_AUX_MAX_OFFSET 0x3000
|
|
#define NIC0_MAC_AUX_SECTION 0xF000
|
|
#define mmNIC0_PHY_BASE 0x7FFCCD8000ull
|
|
#define NIC0_PHY_MAX_OFFSET 0x3400
|
|
#define NIC0_PHY_SECTION 0x8000
|
|
#define mmNIC0_QM0_BASE 0x7FFCCE0000ull
|
|
#define NIC0_QM0_MAX_OFFSET 0xD040
|
|
#define NIC0_QM0_SECTION 0x2000
|
|
#define mmNIC0_QM1_BASE 0x7FFCCE2000ull
|
|
#define NIC0_QM1_MAX_OFFSET 0xD040
|
|
#define NIC0_QM1_SECTION 0x2000
|
|
#define mmNIC0_QPC0_BASE 0x7FFCCE4000ull
|
|
#define NIC0_QPC0_MAX_OFFSET 0x7140
|
|
#define NIC0_QPC0_SECTION 0x1000
|
|
#define mmNIC0_QPC1_BASE 0x7FFCCE5000ull
|
|
#define NIC0_QPC1_MAX_OFFSET 0x7140
|
|
#define NIC0_QPC1_SECTION 0x3000
|
|
#define mmNIC0_RXB_BASE 0x7FFCCE8000ull
|
|
#define NIC0_RXB_MAX_OFFSET 0x6040
|
|
#define NIC0_RXB_SECTION 0x1000
|
|
#define mmNIC0_RXE0_BASE 0x7FFCCE9000ull
|
|
#define NIC0_RXE0_MAX_OFFSET 0x2FC0
|
|
#define NIC0_RXE0_SECTION 0x1000
|
|
#define mmNIC0_RXE1_BASE 0x7FFCCEA000ull
|
|
#define NIC0_RXE1_MAX_OFFSET 0x2FC0
|
|
#define NIC0_RXE1_SECTION 0x1000
|
|
#define mmNIC0_RX_GW_BASE 0x7FFCCEB000ull
|
|
#define NIC0_RX_GW_MAX_OFFSET 0x4540
|
|
#define NIC0_RX_GW_SECTION 0x5000
|
|
#define mmNIC0_TXS0_BASE 0x7FFCCF0000ull
|
|
#define NIC0_TXS0_MAX_OFFSET 0x19C0
|
|
#define NIC0_TXS0_SECTION 0x1000
|
|
#define mmNIC0_TXS1_BASE 0x7FFCCF1000ull
|
|
#define NIC0_TXS1_MAX_OFFSET 0x19C0
|
|
#define NIC0_TXS1_SECTION 0x1000
|
|
#define mmNIC0_TXE0_BASE 0x7FFCCF2000ull
|
|
#define NIC0_TXE0_MAX_OFFSET 0x2040
|
|
#define NIC0_TXE0_SECTION 0x1000
|
|
#define mmNIC0_TXE1_BASE 0x7FFCCF3000ull
|
|
#define NIC0_TXE1_MAX_OFFSET 0x2040
|
|
#define NIC0_TXE1_SECTION 0x1000
|
|
#define mmNIC0_TXB_BASE 0x7FFCCF4000ull
|
|
#define NIC0_TXB_MAX_OFFSET 0xD400
|
|
#define NIC0_TXB_SECTION 0x1000
|
|
#define mmNIC0_TMR_BASE 0x7FFCCF5000ull
|
|
#define NIC0_TMR_MAX_OFFSET 0x1600
|
|
#define NIC0_TMR_SECTION 0x1000
|
|
#define mmNIC0_TX_GW_BASE 0x7FFCCF6000ull
|
|
#define NIC0_TX_GW_MAX_OFFSET 0x1400
|
|
#define NIC0_TX_GW_SECTION 0x2000
|
|
#define mmNIC0_TS_BASE 0x7FFCCF8000ull
|
|
#define NIC0_TS_MAX_OFFSET 0xE640
|
|
#define NIC0_TS_SECTION 0x1000
|
|
#define mmNIC0_PLL_BASE 0x7FFCCF9000ull
|
|
#define NIC0_PLL_MAX_OFFSET 0x5200
|
|
#define NIC0_PLL_SECTION 0x1000
|
|
#define mmNIC0_PM_BASE 0x7FFCCFA000ull
|
|
#define NIC0_PM_MAX_OFFSET 0x1F00
|
|
#define NIC0_PM_SECTION 0x6000
|
|
#define mmNIC1_MAC_CH0_BASE 0x7FFCD00000ull
|
|
#define NIC1_MAC_CH0_MAX_OFFSET 0x8400
|
|
#define NIC1_MAC_CH0_SECTION 0x1000
|
|
#define mmNIC1_MAC_CH1_BASE 0x7FFCD01000ull
|
|
#define NIC1_MAC_CH1_MAX_OFFSET 0x8400
|
|
#define NIC1_MAC_CH1_SECTION 0x1000
|
|
#define mmNIC1_MAC_CH2_BASE 0x7FFCD02000ull
|
|
#define NIC1_MAC_CH2_MAX_OFFSET 0x8400
|
|
#define NIC1_MAC_CH2_SECTION 0x1000
|
|
#define mmNIC1_MAC_CH3_BASE 0x7FFCD03000ull
|
|
#define NIC1_MAC_CH3_MAX_OFFSET 0x8400
|
|
#define NIC1_MAC_CH3_SECTION 0x1000
|
|
#define mmNIC1_STAT_BASE 0x7FFCD04000ull
|
|
#define NIC1_STAT_MAX_OFFSET 0x4D00
|
|
#define NIC1_STAT_SECTION 0x1000
|
|
#define mmNIC1_MAC_XPCS91_BASE 0x7FFCD05000ull
|
|
#define NIC1_MAC_XPCS91_MAX_OFFSET 0x2380
|
|
#define NIC1_MAC_XPCS91_SECTION 0x3000
|
|
#define mmNIC1_MAC_CORE_BASE 0x7FFCD08000ull
|
|
#define NIC1_MAC_CORE_MAX_OFFSET 0x5400
|
|
#define NIC1_MAC_CORE_SECTION 0x1000
|
|
#define mmNIC1_MAC_AUX_BASE 0x7FFCD09000ull
|
|
#define NIC1_MAC_AUX_MAX_OFFSET 0x3000
|
|
#define NIC1_MAC_AUX_SECTION 0xF000
|
|
#define mmNIC1_PHY_BASE 0x7FFCD18000ull
|
|
#define NIC1_PHY_MAX_OFFSET 0x3400
|
|
#define NIC1_PHY_SECTION 0x8000
|
|
#define mmNIC1_QM0_BASE 0x7FFCD20000ull
|
|
#define NIC1_QM0_MAX_OFFSET 0xD040
|
|
#define NIC1_QM0_SECTION 0x2000
|
|
#define mmNIC1_QM1_BASE 0x7FFCD22000ull
|
|
#define NIC1_QM1_MAX_OFFSET 0xD040
|
|
#define NIC1_QM1_SECTION 0x2000
|
|
#define mmNIC1_QPC0_BASE 0x7FFCD24000ull
|
|
#define NIC1_QPC0_MAX_OFFSET 0x7140
|
|
#define NIC1_QPC0_SECTION 0x1000
|
|
#define mmNIC1_QPC1_BASE 0x7FFCD25000ull
|
|
#define NIC1_QPC1_MAX_OFFSET 0x7140
|
|
#define NIC1_QPC1_SECTION 0x3000
|
|
#define mmNIC1_RXB_BASE 0x7FFCD28000ull
|
|
#define NIC1_RXB_MAX_OFFSET 0x6040
|
|
#define NIC1_RXB_SECTION 0x1000
|
|
#define mmNIC1_RXE0_BASE 0x7FFCD29000ull
|
|
#define NIC1_RXE0_MAX_OFFSET 0x2FC0
|
|
#define NIC1_RXE0_SECTION 0x1000
|
|
#define mmNIC1_RXE1_BASE 0x7FFCD2A000ull
|
|
#define NIC1_RXE1_MAX_OFFSET 0x2FC0
|
|
#define NIC1_RXE1_SECTION 0x1000
|
|
#define mmNIC1_RX_GW_BASE 0x7FFCD2B000ull
|
|
#define NIC1_RX_GW_MAX_OFFSET 0x4540
|
|
#define NIC1_RX_GW_SECTION 0x5000
|
|
#define mmNIC1_TXS0_BASE 0x7FFCD30000ull
|
|
#define NIC1_TXS0_MAX_OFFSET 0x19C0
|
|
#define NIC1_TXS0_SECTION 0x1000
|
|
#define mmNIC1_TXS1_BASE 0x7FFCD31000ull
|
|
#define NIC1_TXS1_MAX_OFFSET 0x19C0
|
|
#define NIC1_TXS1_SECTION 0x1000
|
|
#define mmNIC1_TXE0_BASE 0x7FFCD32000ull
|
|
#define NIC1_TXE0_MAX_OFFSET 0x2040
|
|
#define NIC1_TXE0_SECTION 0x1000
|
|
#define mmNIC1_TXE1_BASE 0x7FFCD33000ull
|
|
#define NIC1_TXE1_MAX_OFFSET 0x2040
|
|
#define NIC1_TXE1_SECTION 0x1000
|
|
#define mmNIC1_TXB_BASE 0x7FFCD34000ull
|
|
#define NIC1_TXB_MAX_OFFSET 0xD400
|
|
#define NIC1_TXB_SECTION 0x1000
|
|
#define mmNIC1_TMR_BASE 0x7FFCD35000ull
|
|
#define NIC1_TMR_MAX_OFFSET 0x1600
|
|
#define NIC1_TMR_SECTION 0x1000
|
|
#define mmNIC1_TX_GW_BASE 0x7FFCD36000ull
|
|
#define NIC1_TX_GW_MAX_OFFSET 0x1400
|
|
#define NIC1_TX_GW_SECTION 0x2000
|
|
#define mmNIC1_TS_BASE 0x7FFCD38000ull
|
|
#define NIC1_TS_MAX_OFFSET 0xE640
|
|
#define NIC1_TS_SECTION 0x1000
|
|
#define mmNIC1_PLL_BASE 0x7FFCD39000ull
|
|
#define NIC1_PLL_MAX_OFFSET 0x5200
|
|
#define NIC1_PLL_SECTION 0x1000
|
|
#define mmNIC1_PM_BASE 0x7FFCD3A000ull
|
|
#define NIC1_PM_MAX_OFFSET 0x1F00
|
|
#define NIC1_PM_SECTION 0x6000
|
|
#define mmNIC2_MAC_CH0_BASE 0x7FFCD40000ull
|
|
#define NIC2_MAC_CH0_MAX_OFFSET 0x8400
|
|
#define NIC2_MAC_CH0_SECTION 0x1000
|
|
#define mmNIC2_MAC_CH1_BASE 0x7FFCD41000ull
|
|
#define NIC2_MAC_CH1_MAX_OFFSET 0x8400
|
|
#define NIC2_MAC_CH1_SECTION 0x1000
|
|
#define mmNIC2_MAC_CH2_BASE 0x7FFCD42000ull
|
|
#define NIC2_MAC_CH2_MAX_OFFSET 0x8400
|
|
#define NIC2_MAC_CH2_SECTION 0x1000
|
|
#define mmNIC2_MAC_CH3_BASE 0x7FFCD43000ull
|
|
#define NIC2_MAC_CH3_MAX_OFFSET 0x8400
|
|
#define NIC2_MAC_CH3_SECTION 0x1000
|
|
#define mmNIC2_STAT_BASE 0x7FFCD44000ull
|
|
#define NIC2_STAT_MAX_OFFSET 0x4D00
|
|
#define NIC2_STAT_SECTION 0x1000
|
|
#define mmNIC2_MAC_XPCS91_BASE 0x7FFCD45000ull
|
|
#define NIC2_MAC_XPCS91_MAX_OFFSET 0x2380
|
|
#define NIC2_MAC_XPCS91_SECTION 0x3000
|
|
#define mmNIC2_MAC_CORE_BASE 0x7FFCD48000ull
|
|
#define NIC2_MAC_CORE_MAX_OFFSET 0x5400
|
|
#define NIC2_MAC_CORE_SECTION 0x1000
|
|
#define mmNIC2_MAC_AUX_BASE 0x7FFCD49000ull
|
|
#define NIC2_MAC_AUX_MAX_OFFSET 0x3000
|
|
#define NIC2_MAC_AUX_SECTION 0xF000
|
|
#define mmNIC2_PHY_BASE 0x7FFCD58000ull
|
|
#define NIC2_PHY_MAX_OFFSET 0x3400
|
|
#define NIC2_PHY_SECTION 0x8000
|
|
#define mmNIC2_QM0_BASE 0x7FFCD60000ull
|
|
#define NIC2_QM0_MAX_OFFSET 0xD040
|
|
#define NIC2_QM0_SECTION 0x2000
|
|
#define mmNIC2_QM1_BASE 0x7FFCD62000ull
|
|
#define NIC2_QM1_MAX_OFFSET 0xD040
|
|
#define NIC2_QM1_SECTION 0x2000
|
|
#define mmNIC2_QPC0_BASE 0x7FFCD64000ull
|
|
#define NIC2_QPC0_MAX_OFFSET 0x7140
|
|
#define NIC2_QPC0_SECTION 0x1000
|
|
#define mmNIC2_QPC1_BASE 0x7FFCD65000ull
|
|
#define NIC2_QPC1_MAX_OFFSET 0x7140
|
|
#define NIC2_QPC1_SECTION 0x3000
|
|
#define mmNIC2_RXB_BASE 0x7FFCD68000ull
|
|
#define NIC2_RXB_MAX_OFFSET 0x6040
|
|
#define NIC2_RXB_SECTION 0x1000
|
|
#define mmNIC2_RXE0_BASE 0x7FFCD69000ull
|
|
#define NIC2_RXE0_MAX_OFFSET 0x2FC0
|
|
#define NIC2_RXE0_SECTION 0x1000
|
|
#define mmNIC2_RXE1_BASE 0x7FFCD6A000ull
|
|
#define NIC2_RXE1_MAX_OFFSET 0x2FC0
|
|
#define NIC2_RXE1_SECTION 0x1000
|
|
#define mmNIC2_RX_GW_BASE 0x7FFCD6B000ull
|
|
#define NIC2_RX_GW_MAX_OFFSET 0x4540
|
|
#define NIC2_RX_GW_SECTION 0x5000
|
|
#define mmNIC2_TXS0_BASE 0x7FFCD70000ull
|
|
#define NIC2_TXS0_MAX_OFFSET 0x19C0
|
|
#define NIC2_TXS0_SECTION 0x1000
|
|
#define mmNIC2_TXS1_BASE 0x7FFCD71000ull
|
|
#define NIC2_TXS1_MAX_OFFSET 0x19C0
|
|
#define NIC2_TXS1_SECTION 0x1000
|
|
#define mmNIC2_TXE0_BASE 0x7FFCD72000ull
|
|
#define NIC2_TXE0_MAX_OFFSET 0x2040
|
|
#define NIC2_TXE0_SECTION 0x1000
|
|
#define mmNIC2_TXE1_BASE 0x7FFCD73000ull
|
|
#define NIC2_TXE1_MAX_OFFSET 0x2040
|
|
#define NIC2_TXE1_SECTION 0x1000
|
|
#define mmNIC2_TXB_BASE 0x7FFCD74000ull
|
|
#define NIC2_TXB_MAX_OFFSET 0xD400
|
|
#define NIC2_TXB_SECTION 0x1000
|
|
#define mmNIC2_TMR_BASE 0x7FFCD75000ull
|
|
#define NIC2_TMR_MAX_OFFSET 0x1600
|
|
#define NIC2_TMR_SECTION 0x1000
|
|
#define mmNIC2_TX_GW_BASE 0x7FFCD76000ull
|
|
#define NIC2_TX_GW_MAX_OFFSET 0x1400
|
|
#define NIC2_TX_GW_SECTION 0x2000
|
|
#define mmNIC2_HBM_PLL_BASE 0x7FFCD78000ull
|
|
#define NIC2_HBM_PLL_MAX_OFFSET 0x5200
|
|
#define NIC2_HBM_PLL_SECTION 0x1000
|
|
#define mmNIC2_MME_PLL_BASE 0x7FFCD79000ull
|
|
#define NIC2_MME_PLL_MAX_OFFSET 0x5200
|
|
#define NIC2_MME_PLL_SECTION 0x1000
|
|
#define mmNIC2_TPC_PLL_BASE 0x7FFCD7A000ull
|
|
#define NIC2_TPC_PLL_MAX_OFFSET 0x5200
|
|
#define NIC2_TPC_PLL_SECTION 0x6000
|
|
#define mmNIC3_MAC_CH0_BASE 0x7FFCD80000ull
|
|
#define NIC3_MAC_CH0_MAX_OFFSET 0x8400
|
|
#define NIC3_MAC_CH0_SECTION 0x1000
|
|
#define mmNIC3_MAC_CH1_BASE 0x7FFCD81000ull
|
|
#define NIC3_MAC_CH1_MAX_OFFSET 0x8400
|
|
#define NIC3_MAC_CH1_SECTION 0x1000
|
|
#define mmNIC3_MAC_CH2_BASE 0x7FFCD82000ull
|
|
#define NIC3_MAC_CH2_MAX_OFFSET 0x8400
|
|
#define NIC3_MAC_CH2_SECTION 0x1000
|
|
#define mmNIC3_MAC_CH3_BASE 0x7FFCD83000ull
|
|
#define NIC3_MAC_CH3_MAX_OFFSET 0x8400
|
|
#define NIC3_MAC_CH3_SECTION 0x1000
|
|
#define mmNIC3_STAT_BASE 0x7FFCD84000ull
|
|
#define NIC3_STAT_MAX_OFFSET 0x4D00
|
|
#define NIC3_STAT_SECTION 0x1000
|
|
#define mmNIC3_MAC_XPCS91_BASE 0x7FFCD85000ull
|
|
#define NIC3_MAC_XPCS91_MAX_OFFSET 0x2380
|
|
#define NIC3_MAC_XPCS91_SECTION 0x3000
|
|
#define mmNIC3_MAC_CORE_BASE 0x7FFCD88000ull
|
|
#define NIC3_MAC_CORE_MAX_OFFSET 0x5400
|
|
#define NIC3_MAC_CORE_SECTION 0x1000
|
|
#define mmNIC3_MAC_AUX_BASE 0x7FFCD89000ull
|
|
#define NIC3_MAC_AUX_MAX_OFFSET 0x3000
|
|
#define NIC3_MAC_AUX_SECTION 0xF000
|
|
#define mmNIC3_PHY_BASE 0x7FFCD98000ull
|
|
#define NIC3_PHY_MAX_OFFSET 0x3400
|
|
#define NIC3_PHY_SECTION 0x8000
|
|
#define mmNIC3_QM0_BASE 0x7FFCDA0000ull
|
|
#define NIC3_QM0_MAX_OFFSET 0xD040
|
|
#define NIC3_QM0_SECTION 0x2000
|
|
#define mmNIC3_QM1_BASE 0x7FFCDA2000ull
|
|
#define NIC3_QM1_MAX_OFFSET 0xD040
|
|
#define NIC3_QM1_SECTION 0x2000
|
|
#define mmNIC3_QPC0_BASE 0x7FFCDA4000ull
|
|
#define NIC3_QPC0_MAX_OFFSET 0x7140
|
|
#define NIC3_QPC0_SECTION 0x1000
|
|
#define mmNIC3_QPC1_BASE 0x7FFCDA5000ull
|
|
#define NIC3_QPC1_MAX_OFFSET 0x7140
|
|
#define NIC3_QPC1_SECTION 0x3000
|
|
#define mmNIC3_RXB_BASE 0x7FFCDA8000ull
|
|
#define NIC3_RXB_MAX_OFFSET 0x6040
|
|
#define NIC3_RXB_SECTION 0x1000
|
|
#define mmNIC3_RXE0_BASE 0x7FFCDA9000ull
|
|
#define NIC3_RXE0_MAX_OFFSET 0x2FC0
|
|
#define NIC3_RXE0_SECTION 0x1000
|
|
#define mmNIC3_RXE1_BASE 0x7FFCDAA000ull
|
|
#define NIC3_RXE1_MAX_OFFSET 0x2FC0
|
|
#define NIC3_RXE1_SECTION 0x1000
|
|
#define mmNIC3_RX_GW_BASE 0x7FFCDAB000ull
|
|
#define NIC3_RX_GW_MAX_OFFSET 0x4540
|
|
#define NIC3_RX_GW_SECTION 0x5000
|
|
#define mmNIC3_TXS0_BASE 0x7FFCDB0000ull
|
|
#define NIC3_TXS0_MAX_OFFSET 0x19C0
|
|
#define NIC3_TXS0_SECTION 0x1000
|
|
#define mmNIC3_TXS1_BASE 0x7FFCDB1000ull
|
|
#define NIC3_TXS1_MAX_OFFSET 0x19C0
|
|
#define NIC3_TXS1_SECTION 0x1000
|
|
#define mmNIC3_TXE0_BASE 0x7FFCDB2000ull
|
|
#define NIC3_TXE0_MAX_OFFSET 0x2040
|
|
#define NIC3_TXE0_SECTION 0x1000
|
|
#define mmNIC3_TXE1_BASE 0x7FFCDB3000ull
|
|
#define NIC3_TXE1_MAX_OFFSET 0x2040
|
|
#define NIC3_TXE1_SECTION 0x1000
|
|
#define mmNIC3_TXB_BASE 0x7FFCDB4000ull
|
|
#define NIC3_TXB_MAX_OFFSET 0xD400
|
|
#define NIC3_TXB_SECTION 0x1000
|
|
#define mmNIC3_TMR_BASE 0x7FFCDB5000ull
|
|
#define NIC3_TMR_MAX_OFFSET 0x1600
|
|
#define NIC3_TMR_SECTION 0x1000
|
|
#define mmNIC3_TX_GW_BASE 0x7FFCDB6000ull
|
|
#define NIC3_TX_GW_MAX_OFFSET 0x1400
|
|
#define NIC3_TX_GW_SECTION 0x2000
|
|
#define mmNIC3_TS_BASE 0x7FFCDB8000ull
|
|
#define NIC3_TS_MAX_OFFSET 0xE640
|
|
#define NIC3_TS_SECTION 0x2000
|
|
#define mmNIC3_PM_BASE 0x7FFCDBA000ull
|
|
#define NIC3_PM_MAX_OFFSET 0x1F00
|
|
#define NIC3_PM_SECTION 0x6000
|
|
#define mmNIC4_MAC_CH0_BASE 0x7FFCDC0000ull
|
|
#define NIC4_MAC_CH0_MAX_OFFSET 0x8400
|
|
#define NIC4_MAC_CH0_SECTION 0x1000
|
|
#define mmNIC4_MAC_CH1_BASE 0x7FFCDC1000ull
|
|
#define NIC4_MAC_CH1_MAX_OFFSET 0x8400
|
|
#define NIC4_MAC_CH1_SECTION 0x1000
|
|
#define mmNIC4_MAC_CH2_BASE 0x7FFCDC2000ull
|
|
#define NIC4_MAC_CH2_MAX_OFFSET 0x8400
|
|
#define NIC4_MAC_CH2_SECTION 0x1000
|
|
#define mmNIC4_MAC_CH3_BASE 0x7FFCDC3000ull
|
|
#define NIC4_MAC_CH3_MAX_OFFSET 0x8400
|
|
#define NIC4_MAC_CH3_SECTION 0x1000
|
|
#define mmNIC4_STAT_BASE 0x7FFCDC4000ull
|
|
#define NIC4_STAT_MAX_OFFSET 0x4D00
|
|
#define NIC4_STAT_SECTION 0x1000
|
|
#define mmNIC4_MAC_XPCS91_BASE 0x7FFCDC5000ull
|
|
#define NIC4_MAC_XPCS91_MAX_OFFSET 0x2380
|
|
#define NIC4_MAC_XPCS91_SECTION 0x3000
|
|
#define mmNIC4_MAC_CORE_BASE 0x7FFCDC8000ull
|
|
#define NIC4_MAC_CORE_MAX_OFFSET 0x5400
|
|
#define NIC4_MAC_CORE_SECTION 0x1000
|
|
#define mmNIC4_MAC_AUX_BASE 0x7FFCDC9000ull
|
|
#define NIC4_MAC_AUX_MAX_OFFSET 0x3000
|
|
#define NIC4_MAC_AUX_SECTION 0xF000
|
|
#define mmNIC4_PHY_BASE 0x7FFCDD8000ull
|
|
#define NIC4_PHY_MAX_OFFSET 0x3400
|
|
#define NIC4_PHY_SECTION 0x8000
|
|
#define mmNIC4_QM0_BASE 0x7FFCDE0000ull
|
|
#define NIC4_QM0_MAX_OFFSET 0xD040
|
|
#define NIC4_QM0_SECTION 0x2000
|
|
#define mmNIC4_QM1_BASE 0x7FFCDE2000ull
|
|
#define NIC4_QM1_MAX_OFFSET 0xD040
|
|
#define NIC4_QM1_SECTION 0x2000
|
|
#define mmNIC4_QPC0_BASE 0x7FFCDE4000ull
|
|
#define NIC4_QPC0_MAX_OFFSET 0x7140
|
|
#define NIC4_QPC0_SECTION 0x1000
|
|
#define mmNIC4_QPC1_BASE 0x7FFCDE5000ull
|
|
#define NIC4_QPC1_MAX_OFFSET 0x7140
|
|
#define NIC4_QPC1_SECTION 0x3000
|
|
#define mmNIC4_RXB_BASE 0x7FFCDE8000ull
|
|
#define NIC4_RXB_MAX_OFFSET 0x6040
|
|
#define NIC4_RXB_SECTION 0x1000
|
|
#define mmNIC4_RXE0_BASE 0x7FFCDE9000ull
|
|
#define NIC4_RXE0_MAX_OFFSET 0x2FC0
|
|
#define NIC4_RXE0_SECTION 0x1000
|
|
#define mmNIC4_RXE1_BASE 0x7FFCDEA000ull
|
|
#define NIC4_RXE1_MAX_OFFSET 0x2FC0
|
|
#define NIC4_RXE1_SECTION 0x1000
|
|
#define mmNIC4_RX_GW_BASE 0x7FFCDEB000ull
|
|
#define NIC4_RX_GW_MAX_OFFSET 0x4540
|
|
#define NIC4_RX_GW_SECTION 0x5000
|
|
#define mmNIC4_TXS0_BASE 0x7FFCDF0000ull
|
|
#define NIC4_TXS0_MAX_OFFSET 0x19C0
|
|
#define NIC4_TXS0_SECTION 0x1000
|
|
#define mmNIC4_TXS1_BASE 0x7FFCDF1000ull
|
|
#define NIC4_TXS1_MAX_OFFSET 0x19C0
|
|
#define NIC4_TXS1_SECTION 0x1000
|
|
#define mmNIC4_TXE0_BASE 0x7FFCDF2000ull
|
|
#define NIC4_TXE0_MAX_OFFSET 0x2040
|
|
#define NIC4_TXE0_SECTION 0x1000
|
|
#define mmNIC4_TXE1_BASE 0x7FFCDF3000ull
|
|
#define NIC4_TXE1_MAX_OFFSET 0x2040
|
|
#define NIC4_TXE1_SECTION 0x1000
|
|
#define mmNIC4_TXB_BASE 0x7FFCDF4000ull
|
|
#define NIC4_TXB_MAX_OFFSET 0xD400
|
|
#define NIC4_TXB_SECTION 0x1000
|
|
#define mmNIC4_TMR_BASE 0x7FFCDF5000ull
|
|
#define NIC4_TMR_MAX_OFFSET 0x1600
|
|
#define NIC4_TMR_SECTION 0x1000
|
|
#define mmNIC4_TX_GW_BASE 0x7FFCDF6000ull
|
|
#define NIC4_TX_GW_MAX_OFFSET 0x1400
|
|
#define NIC4_TX_GW_SECTION 0x10000
|
|
#define mmTPC0_CFG_BASE 0x7FFCE06000ull
|
|
#define TPC0_CFG_MAX_OFFSET 0xE400
|
|
#define TPC0_CFG_SECTION 0x4000
|
|
#define mmKERNEL_TENSOR_0_TPC0_CFG_BASE 0x7FFCE06400ull
|
|
#define KERNEL_TENSOR_0_TPC0_CFG_MAX_OFFSET 0x3800
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#define KERNEL_TENSOR_0_TPC0_CFG_SECTION 0x3800
|
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#define mmKERNEL_TENSOR_1_TPC0_CFG_BASE 0x7FFCE06438ull
|
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#define KERNEL_TENSOR_1_TPC0_CFG_MAX_OFFSET 0x3800
|
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#define KERNEL_TENSOR_1_TPC0_CFG_SECTION 0x3800
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#define mmKERNEL_TENSOR_2_TPC0_CFG_BASE 0x7FFCE06470ull
|
|
#define KERNEL_TENSOR_2_TPC0_CFG_MAX_OFFSET 0x3800
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#define KERNEL_TENSOR_2_TPC0_CFG_SECTION 0x3800
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#define mmKERNEL_TENSOR_3_TPC0_CFG_BASE 0x7FFCE064A8ull
|
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#define KERNEL_TENSOR_3_TPC0_CFG_MAX_OFFSET 0x3800
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#define KERNEL_TENSOR_3_TPC0_CFG_SECTION 0x3800
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#define mmKERNEL_TENSOR_4_TPC0_CFG_BASE 0x7FFCE064E0ull
|
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#define KERNEL_TENSOR_4_TPC0_CFG_MAX_OFFSET 0x3800
|
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#define KERNEL_TENSOR_4_TPC0_CFG_SECTION 0x3800
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#define mmKERNEL_TENSOR_5_TPC0_CFG_BASE 0x7FFCE06518ull
|
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#define KERNEL_TENSOR_5_TPC0_CFG_MAX_OFFSET 0x3800
|
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#define KERNEL_TENSOR_5_TPC0_CFG_SECTION 0x3800
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#define mmKERNEL_TENSOR_6_TPC0_CFG_BASE 0x7FFCE06550ull
|
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#define KERNEL_TENSOR_6_TPC0_CFG_MAX_OFFSET 0x3800
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#define KERNEL_TENSOR_6_TPC0_CFG_SECTION 0x3800
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#define mmKERNEL_TENSOR_7_TPC0_CFG_BASE 0x7FFCE06588ull
|
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#define KERNEL_TENSOR_7_TPC0_CFG_MAX_OFFSET 0x3800
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#define KERNEL_TENSOR_7_TPC0_CFG_SECTION 0x3800
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#define mmKERNEL_TENSOR_8_TPC0_CFG_BASE 0x7FFCE065C0ull
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#define KERNEL_TENSOR_8_TPC0_CFG_MAX_OFFSET 0x3800
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#define KERNEL_TENSOR_8_TPC0_CFG_SECTION 0x3800
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#define mmKERNEL_TENSOR_9_TPC0_CFG_BASE 0x7FFCE065F8ull
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#define KERNEL_TENSOR_9_TPC0_CFG_MAX_OFFSET 0x3800
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#define KERNEL_TENSOR_9_TPC0_CFG_SECTION 0x3800
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#define mmKERNEL_TENSOR_10_TPC0_CFG_BASE 0x7FFCE06630ull
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#define KERNEL_TENSOR_10_TPC0_CFG_MAX_OFFSET 0x3800
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#define KERNEL_TENSOR_10_TPC0_CFG_SECTION 0x3800
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#define mmKERNEL_TENSOR_11_TPC0_CFG_BASE 0x7FFCE06668ull
|
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#define KERNEL_TENSOR_11_TPC0_CFG_MAX_OFFSET 0x3800
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#define KERNEL_TENSOR_11_TPC0_CFG_SECTION 0x3800
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#define mmKERNEL_TENSOR_12_TPC0_CFG_BASE 0x7FFCE066A0ull
|
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#define KERNEL_TENSOR_12_TPC0_CFG_MAX_OFFSET 0x3800
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#define KERNEL_TENSOR_12_TPC0_CFG_SECTION 0x3800
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#define mmKERNEL_TENSOR_13_TPC0_CFG_BASE 0x7FFCE066D8ull
|
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#define KERNEL_TENSOR_13_TPC0_CFG_MAX_OFFSET 0x3800
|
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#define KERNEL_TENSOR_13_TPC0_CFG_SECTION 0x3800
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#define mmKERNEL_TENSOR_14_TPC0_CFG_BASE 0x7FFCE06710ull
|
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#define KERNEL_TENSOR_14_TPC0_CFG_MAX_OFFSET 0x3800
|
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#define KERNEL_TENSOR_14_TPC0_CFG_SECTION 0x3800
|
|
#define mmKERNEL_TENSOR_15_TPC0_CFG_BASE 0x7FFCE06748ull
|
|
#define KERNEL_TENSOR_15_TPC0_CFG_MAX_OFFSET 0x3800
|
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#define KERNEL_TENSOR_15_TPC0_CFG_SECTION 0x3800
|
|
#define mmKERNEL_SYNC_OBJECT_TPC0_CFG_BASE 0x7FFCE06780ull
|
|
#define KERNEL_SYNC_OBJECT_TPC0_CFG_MAX_OFFSET 0x8000
|
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#define KERNEL_SYNC_OBJECT_TPC0_CFG_SECTION 0x8000
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#define mmKERNEL_TPC0_CFG_BASE 0x7FFCE06788ull
|
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#define KERNEL_TPC0_CFG_MAX_OFFSET 0xB800
|
|
#define KERNEL_TPC0_CFG_SECTION 0x2780
|
|
#define mmQM_TENSOR_0_TPC0_CFG_BASE 0x7FFCE06A00ull
|
|
#define QM_TENSOR_0_TPC0_CFG_MAX_OFFSET 0x3800
|
|
#define QM_TENSOR_0_TPC0_CFG_SECTION 0x3800
|
|
#define mmQM_TENSOR_1_TPC0_CFG_BASE 0x7FFCE06A38ull
|
|
#define QM_TENSOR_1_TPC0_CFG_MAX_OFFSET 0x3800
|
|
#define QM_TENSOR_1_TPC0_CFG_SECTION 0x3800
|
|
#define mmQM_TENSOR_2_TPC0_CFG_BASE 0x7FFCE06A70ull
|
|
#define QM_TENSOR_2_TPC0_CFG_MAX_OFFSET 0x3800
|
|
#define QM_TENSOR_2_TPC0_CFG_SECTION 0x3800
|
|
#define mmQM_TENSOR_3_TPC0_CFG_BASE 0x7FFCE06AA8ull
|
|
#define QM_TENSOR_3_TPC0_CFG_MAX_OFFSET 0x3800
|
|
#define QM_TENSOR_3_TPC0_CFG_SECTION 0x3800
|
|
#define mmQM_TENSOR_4_TPC0_CFG_BASE 0x7FFCE06AE0ull
|
|
#define QM_TENSOR_4_TPC0_CFG_MAX_OFFSET 0x3800
|
|
#define QM_TENSOR_4_TPC0_CFG_SECTION 0x3800
|
|
#define mmQM_TENSOR_5_TPC0_CFG_BASE 0x7FFCE06B18ull
|
|
#define QM_TENSOR_5_TPC0_CFG_MAX_OFFSET 0x3800
|
|
#define QM_TENSOR_5_TPC0_CFG_SECTION 0x3800
|
|
#define mmQM_TENSOR_6_TPC0_CFG_BASE 0x7FFCE06B50ull
|
|
#define QM_TENSOR_6_TPC0_CFG_MAX_OFFSET 0x3800
|
|
#define QM_TENSOR_6_TPC0_CFG_SECTION 0x3800
|
|
#define mmQM_TENSOR_7_TPC0_CFG_BASE 0x7FFCE06B88ull
|
|
#define QM_TENSOR_7_TPC0_CFG_MAX_OFFSET 0x3800
|
|
#define QM_TENSOR_7_TPC0_CFG_SECTION 0x3800
|
|
#define mmQM_TENSOR_8_TPC0_CFG_BASE 0x7FFCE06BC0ull
|
|
#define QM_TENSOR_8_TPC0_CFG_MAX_OFFSET 0x3800
|
|
#define QM_TENSOR_8_TPC0_CFG_SECTION 0x3800
|
|
#define mmQM_TENSOR_9_TPC0_CFG_BASE 0x7FFCE06BF8ull
|
|
#define QM_TENSOR_9_TPC0_CFG_MAX_OFFSET 0x3800
|
|
#define QM_TENSOR_9_TPC0_CFG_SECTION 0x3800
|
|
#define mmQM_TENSOR_10_TPC0_CFG_BASE 0x7FFCE06C30ull
|
|
#define QM_TENSOR_10_TPC0_CFG_MAX_OFFSET 0x3800
|
|
#define QM_TENSOR_10_TPC0_CFG_SECTION 0x3800
|
|
#define mmQM_TENSOR_11_TPC0_CFG_BASE 0x7FFCE06C68ull
|
|
#define QM_TENSOR_11_TPC0_CFG_MAX_OFFSET 0x3800
|
|
#define QM_TENSOR_11_TPC0_CFG_SECTION 0x3800
|
|
#define mmQM_TENSOR_12_TPC0_CFG_BASE 0x7FFCE06CA0ull
|
|
#define QM_TENSOR_12_TPC0_CFG_MAX_OFFSET 0x3800
|
|
#define QM_TENSOR_12_TPC0_CFG_SECTION 0x3800
|
|
#define mmQM_TENSOR_13_TPC0_CFG_BASE 0x7FFCE06CD8ull
|
|
#define QM_TENSOR_13_TPC0_CFG_MAX_OFFSET 0x3800
|
|
#define QM_TENSOR_13_TPC0_CFG_SECTION 0x3800
|
|
#define mmQM_TENSOR_14_TPC0_CFG_BASE 0x7FFCE06D10ull
|
|
#define QM_TENSOR_14_TPC0_CFG_MAX_OFFSET 0x3800
|
|
#define QM_TENSOR_14_TPC0_CFG_SECTION 0x3800
|
|
#define mmQM_TENSOR_15_TPC0_CFG_BASE 0x7FFCE06D48ull
|
|
#define QM_TENSOR_15_TPC0_CFG_MAX_OFFSET 0x3800
|
|
#define QM_TENSOR_15_TPC0_CFG_SECTION 0x3800
|
|
#define mmQM_SYNC_OBJECT_TPC0_CFG_BASE 0x7FFCE06D80ull
|
|
#define QM_SYNC_OBJECT_TPC0_CFG_MAX_OFFSET 0x8000
|
|
#define QM_SYNC_OBJECT_TPC0_CFG_SECTION 0x8000
|
|
#define mmQM_TPC0_CFG_BASE 0x7FFCE06D88ull
|
|
#define QM_TPC0_CFG_MAX_OFFSET 0xB800
|
|
#define QM_TPC0_CFG_SECTION 0x2780
|
|
#define mmTPC0_E2E_CRED_BASE 0x7FFCE07000ull
|
|
#define TPC0_E2E_CRED_MAX_OFFSET 0x1680
|
|
#define TPC0_E2E_CRED_SECTION 0x1000
|
|
#define mmTPC0_QM_BASE 0x7FFCE08000ull
|
|
#define TPC0_QM_MAX_OFFSET 0xD040
|
|
#define TPC0_QM_SECTION 0x3E000
|
|
#define mmTPC1_CFG_BASE 0x7FFCE46000ull
|
|
#define TPC1_CFG_MAX_OFFSET 0xE400
|
|
#define TPC1_CFG_SECTION 0x4000
|
|
#define mmKERNEL_TENSOR_0_TPC1_CFG_BASE 0x7FFCE46400ull
|
|
#define KERNEL_TENSOR_0_TPC1_CFG_MAX_OFFSET 0x3800
|
|
#define KERNEL_TENSOR_0_TPC1_CFG_SECTION 0x3800
|
|
#define mmKERNEL_TENSOR_1_TPC1_CFG_BASE 0x7FFCE46438ull
|
|
#define KERNEL_TENSOR_1_TPC1_CFG_MAX_OFFSET 0x3800
|
|
#define KERNEL_TENSOR_1_TPC1_CFG_SECTION 0x3800
|
|
#define mmKERNEL_TENSOR_2_TPC1_CFG_BASE 0x7FFCE46470ull
|
|
#define KERNEL_TENSOR_2_TPC1_CFG_MAX_OFFSET 0x3800
|
|
#define KERNEL_TENSOR_2_TPC1_CFG_SECTION 0x3800
|
|
#define mmKERNEL_TENSOR_3_TPC1_CFG_BASE 0x7FFCE464A8ull
|
|
#define KERNEL_TENSOR_3_TPC1_CFG_MAX_OFFSET 0x3800
|
|
#define KERNEL_TENSOR_3_TPC1_CFG_SECTION 0x3800
|
|
#define mmKERNEL_TENSOR_4_TPC1_CFG_BASE 0x7FFCE464E0ull
|
|
#define KERNEL_TENSOR_4_TPC1_CFG_MAX_OFFSET 0x3800
|
|
#define KERNEL_TENSOR_4_TPC1_CFG_SECTION 0x3800
|
|
#define mmKERNEL_TENSOR_5_TPC1_CFG_BASE 0x7FFCE46518ull
|
|
#define KERNEL_TENSOR_5_TPC1_CFG_MAX_OFFSET 0x3800
|
|
#define KERNEL_TENSOR_5_TPC1_CFG_SECTION 0x3800
|
|
#define mmKERNEL_TENSOR_6_TPC1_CFG_BASE 0x7FFCE46550ull
|
|
#define KERNEL_TENSOR_6_TPC1_CFG_MAX_OFFSET 0x3800
|
|
#define KERNEL_TENSOR_6_TPC1_CFG_SECTION 0x3800
|
|
#define mmKERNEL_TENSOR_7_TPC1_CFG_BASE 0x7FFCE46588ull
|
|
#define KERNEL_TENSOR_7_TPC1_CFG_MAX_OFFSET 0x3800
|
|
#define KERNEL_TENSOR_7_TPC1_CFG_SECTION 0x3800
|
|
#define mmKERNEL_TENSOR_8_TPC1_CFG_BASE 0x7FFCE465C0ull
|
|
#define KERNEL_TENSOR_8_TPC1_CFG_MAX_OFFSET 0x3800
|
|
#define KERNEL_TENSOR_8_TPC1_CFG_SECTION 0x3800
|
|
#define mmKERNEL_TENSOR_9_TPC1_CFG_BASE 0x7FFCE465F8ull
|
|
#define KERNEL_TENSOR_9_TPC1_CFG_MAX_OFFSET 0x3800
|
|
#define KERNEL_TENSOR_9_TPC1_CFG_SECTION 0x3800
|
|
#define mmKERNEL_TENSOR_10_TPC1_CFG_BASE 0x7FFCE46630ull
|
|
#define KERNEL_TENSOR_10_TPC1_CFG_MAX_OFFSET 0x3800
|
|
#define KERNEL_TENSOR_10_TPC1_CFG_SECTION 0x3800
|
|
#define mmKERNEL_TENSOR_11_TPC1_CFG_BASE 0x7FFCE46668ull
|
|
#define KERNEL_TENSOR_11_TPC1_CFG_MAX_OFFSET 0x3800
|
|
#define KERNEL_TENSOR_11_TPC1_CFG_SECTION 0x3800
|
|
#define mmKERNEL_TENSOR_12_TPC1_CFG_BASE 0x7FFCE466A0ull
|
|
#define KERNEL_TENSOR_12_TPC1_CFG_MAX_OFFSET 0x3800
|
|
#define KERNEL_TENSOR_12_TPC1_CFG_SECTION 0x3800
|
|
#define mmKERNEL_TENSOR_13_TPC1_CFG_BASE 0x7FFCE466D8ull
|
|
#define KERNEL_TENSOR_13_TPC1_CFG_MAX_OFFSET 0x3800
|
|
#define KERNEL_TENSOR_13_TPC1_CFG_SECTION 0x3800
|
|
#define mmKERNEL_TENSOR_14_TPC1_CFG_BASE 0x7FFCE46710ull
|
|
#define KERNEL_TENSOR_14_TPC1_CFG_MAX_OFFSET 0x3800
|
|
#define KERNEL_TENSOR_14_TPC1_CFG_SECTION 0x3800
|
|
#define mmKERNEL_TENSOR_15_TPC1_CFG_BASE 0x7FFCE46748ull
|
|
#define KERNEL_TENSOR_15_TPC1_CFG_MAX_OFFSET 0x3800
|
|
#define KERNEL_TENSOR_15_TPC1_CFG_SECTION 0x3800
|
|
#define mmKERNEL_SYNC_OBJECT_TPC1_CFG_BASE 0x7FFCE46780ull
|
|
#define KERNEL_SYNC_OBJECT_TPC1_CFG_MAX_OFFSET 0x8000
|
|
#define KERNEL_SYNC_OBJECT_TPC1_CFG_SECTION 0x8000
|
|
#define mmKERNEL_TPC1_CFG_BASE 0x7FFCE46788ull
|
|
#define KERNEL_TPC1_CFG_MAX_OFFSET 0xB800
|
|
#define KERNEL_TPC1_CFG_SECTION 0x2780
|
|
#define mmQM_TENSOR_0_TPC1_CFG_BASE 0x7FFCE46A00ull
|
|
#define QM_TENSOR_0_TPC1_CFG_MAX_OFFSET 0x3800
|
|
#define QM_TENSOR_0_TPC1_CFG_SECTION 0x3800
|
|
#define mmQM_TENSOR_1_TPC1_CFG_BASE 0x7FFCE46A38ull
|
|
#define QM_TENSOR_1_TPC1_CFG_MAX_OFFSET 0x3800
|
|
#define QM_TENSOR_1_TPC1_CFG_SECTION 0x3800
|
|
#define mmQM_TENSOR_2_TPC1_CFG_BASE 0x7FFCE46A70ull
|
|
#define QM_TENSOR_2_TPC1_CFG_MAX_OFFSET 0x3800
|
|
#define QM_TENSOR_2_TPC1_CFG_SECTION 0x3800
|
|
#define mmQM_TENSOR_3_TPC1_CFG_BASE 0x7FFCE46AA8ull
|
|
#define QM_TENSOR_3_TPC1_CFG_MAX_OFFSET 0x3800
|
|
#define QM_TENSOR_3_TPC1_CFG_SECTION 0x3800
|
|
#define mmQM_TENSOR_4_TPC1_CFG_BASE 0x7FFCE46AE0ull
|
|
#define QM_TENSOR_4_TPC1_CFG_MAX_OFFSET 0x3800
|
|
#define QM_TENSOR_4_TPC1_CFG_SECTION 0x3800
|
|
#define mmQM_TENSOR_5_TPC1_CFG_BASE 0x7FFCE46B18ull
|
|
#define QM_TENSOR_5_TPC1_CFG_MAX_OFFSET 0x3800
|
|
#define QM_TENSOR_5_TPC1_CFG_SECTION 0x3800
|
|
#define mmQM_TENSOR_6_TPC1_CFG_BASE 0x7FFCE46B50ull
|
|
#define QM_TENSOR_6_TPC1_CFG_MAX_OFFSET 0x3800
|
|
#define QM_TENSOR_6_TPC1_CFG_SECTION 0x3800
|
|
#define mmQM_TENSOR_7_TPC1_CFG_BASE 0x7FFCE46B88ull
|
|
#define QM_TENSOR_7_TPC1_CFG_MAX_OFFSET 0x3800
|
|
#define QM_TENSOR_7_TPC1_CFG_SECTION 0x3800
|
|
#define mmQM_TENSOR_8_TPC1_CFG_BASE 0x7FFCE46BC0ull
|
|
#define QM_TENSOR_8_TPC1_CFG_MAX_OFFSET 0x3800
|
|
#define QM_TENSOR_8_TPC1_CFG_SECTION 0x3800
|
|
#define mmQM_TENSOR_9_TPC1_CFG_BASE 0x7FFCE46BF8ull
|
|
#define QM_TENSOR_9_TPC1_CFG_MAX_OFFSET 0x3800
|
|
#define QM_TENSOR_9_TPC1_CFG_SECTION 0x3800
|
|
#define mmQM_TENSOR_10_TPC1_CFG_BASE 0x7FFCE46C30ull
|
|
#define QM_TENSOR_10_TPC1_CFG_MAX_OFFSET 0x3800
|
|
#define QM_TENSOR_10_TPC1_CFG_SECTION 0x3800
|
|
#define mmQM_TENSOR_11_TPC1_CFG_BASE 0x7FFCE46C68ull
|
|
#define QM_TENSOR_11_TPC1_CFG_MAX_OFFSET 0x3800
|
|
#define QM_TENSOR_11_TPC1_CFG_SECTION 0x3800
|
|
#define mmQM_TENSOR_12_TPC1_CFG_BASE 0x7FFCE46CA0ull
|
|
#define QM_TENSOR_12_TPC1_CFG_MAX_OFFSET 0x3800
|
|
#define QM_TENSOR_12_TPC1_CFG_SECTION 0x3800
|
|
#define mmQM_TENSOR_13_TPC1_CFG_BASE 0x7FFCE46CD8ull
|
|
#define QM_TENSOR_13_TPC1_CFG_MAX_OFFSET 0x3800
|
|
#define QM_TENSOR_13_TPC1_CFG_SECTION 0x3800
|
|
#define mmQM_TENSOR_14_TPC1_CFG_BASE 0x7FFCE46D10ull
|
|
#define QM_TENSOR_14_TPC1_CFG_MAX_OFFSET 0x3800
|
|
#define QM_TENSOR_14_TPC1_CFG_SECTION 0x3800
|
|
#define mmQM_TENSOR_15_TPC1_CFG_BASE 0x7FFCE46D48ull
|
|
#define QM_TENSOR_15_TPC1_CFG_MAX_OFFSET 0x3800
|
|
#define QM_TENSOR_15_TPC1_CFG_SECTION 0x3800
|
|
#define mmQM_SYNC_OBJECT_TPC1_CFG_BASE 0x7FFCE46D80ull
|
|
#define QM_SYNC_OBJECT_TPC1_CFG_MAX_OFFSET 0x8000
|
|
#define QM_SYNC_OBJECT_TPC1_CFG_SECTION 0x8000
|
|
#define mmQM_TPC1_CFG_BASE 0x7FFCE46D88ull
|
|
#define QM_TPC1_CFG_MAX_OFFSET 0xB800
|
|
#define QM_TPC1_CFG_SECTION 0x2780
|
|
#define mmTPC1_E2E_CRED_BASE 0x7FFCE47000ull
|
|
#define TPC1_E2E_CRED_MAX_OFFSET 0x1680
|
|
#define TPC1_E2E_CRED_SECTION 0x1000
|
|
#define mmTPC1_QM_BASE 0x7FFCE48000ull
|
|
#define TPC1_QM_MAX_OFFSET 0xD040
|
|
#define TPC1_QM_SECTION 0x3E000
|
|
#define mmTPC2_CFG_BASE 0x7FFCE86000ull
|
|
#define TPC2_CFG_MAX_OFFSET 0xE400
|
|
#define TPC2_CFG_SECTION 0x4000
|
|
#define mmKERNEL_TENSOR_0_TPC2_CFG_BASE 0x7FFCE86400ull
|
|
#define KERNEL_TENSOR_0_TPC2_CFG_MAX_OFFSET 0x3800
|
|
#define KERNEL_TENSOR_0_TPC2_CFG_SECTION 0x3800
|
|
#define mmKERNEL_TENSOR_1_TPC2_CFG_BASE 0x7FFCE86438ull
|
|
#define KERNEL_TENSOR_1_TPC2_CFG_MAX_OFFSET 0x3800
|
|
#define KERNEL_TENSOR_1_TPC2_CFG_SECTION 0x3800
|
|
#define mmKERNEL_TENSOR_2_TPC2_CFG_BASE 0x7FFCE86470ull
|
|
#define KERNEL_TENSOR_2_TPC2_CFG_MAX_OFFSET 0x3800
|
|
#define KERNEL_TENSOR_2_TPC2_CFG_SECTION 0x3800
|
|
#define mmKERNEL_TENSOR_3_TPC2_CFG_BASE 0x7FFCE864A8ull
|
|
#define KERNEL_TENSOR_3_TPC2_CFG_MAX_OFFSET 0x3800
|
|
#define KERNEL_TENSOR_3_TPC2_CFG_SECTION 0x3800
|
|
#define mmKERNEL_TENSOR_4_TPC2_CFG_BASE 0x7FFCE864E0ull
|
|
#define KERNEL_TENSOR_4_TPC2_CFG_MAX_OFFSET 0x3800
|
|
#define KERNEL_TENSOR_4_TPC2_CFG_SECTION 0x3800
|
|
#define mmKERNEL_TENSOR_5_TPC2_CFG_BASE 0x7FFCE86518ull
|
|
#define KERNEL_TENSOR_5_TPC2_CFG_MAX_OFFSET 0x3800
|
|
#define KERNEL_TENSOR_5_TPC2_CFG_SECTION 0x3800
|
|
#define mmKERNEL_TENSOR_6_TPC2_CFG_BASE 0x7FFCE86550ull
|
|
#define KERNEL_TENSOR_6_TPC2_CFG_MAX_OFFSET 0x3800
|
|
#define KERNEL_TENSOR_6_TPC2_CFG_SECTION 0x3800
|
|
#define mmKERNEL_TENSOR_7_TPC2_CFG_BASE 0x7FFCE86588ull
|
|
#define KERNEL_TENSOR_7_TPC2_CFG_MAX_OFFSET 0x3800
|
|
#define KERNEL_TENSOR_7_TPC2_CFG_SECTION 0x3800
|
|
#define mmKERNEL_TENSOR_8_TPC2_CFG_BASE 0x7FFCE865C0ull
|
|
#define KERNEL_TENSOR_8_TPC2_CFG_MAX_OFFSET 0x3800
|
|
#define KERNEL_TENSOR_8_TPC2_CFG_SECTION 0x3800
|
|
#define mmKERNEL_TENSOR_9_TPC2_CFG_BASE 0x7FFCE865F8ull
|
|
#define KERNEL_TENSOR_9_TPC2_CFG_MAX_OFFSET 0x3800
|
|
#define KERNEL_TENSOR_9_TPC2_CFG_SECTION 0x3800
|
|
#define mmKERNEL_TENSOR_10_TPC2_CFG_BASE 0x7FFCE86630ull
|
|
#define KERNEL_TENSOR_10_TPC2_CFG_MAX_OFFSET 0x3800
|
|
#define KERNEL_TENSOR_10_TPC2_CFG_SECTION 0x3800
|
|
#define mmKERNEL_TENSOR_11_TPC2_CFG_BASE 0x7FFCE86668ull
|
|
#define KERNEL_TENSOR_11_TPC2_CFG_MAX_OFFSET 0x3800
|
|
#define KERNEL_TENSOR_11_TPC2_CFG_SECTION 0x3800
|
|
#define mmKERNEL_TENSOR_12_TPC2_CFG_BASE 0x7FFCE866A0ull
|
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#define KERNEL_TENSOR_12_TPC2_CFG_MAX_OFFSET 0x3800
|
|
#define KERNEL_TENSOR_12_TPC2_CFG_SECTION 0x3800
|
|
#define mmKERNEL_TENSOR_13_TPC2_CFG_BASE 0x7FFCE866D8ull
|
|
#define KERNEL_TENSOR_13_TPC2_CFG_MAX_OFFSET 0x3800
|
|
#define KERNEL_TENSOR_13_TPC2_CFG_SECTION 0x3800
|
|
#define mmKERNEL_TENSOR_14_TPC2_CFG_BASE 0x7FFCE86710ull
|
|
#define KERNEL_TENSOR_14_TPC2_CFG_MAX_OFFSET 0x3800
|
|
#define KERNEL_TENSOR_14_TPC2_CFG_SECTION 0x3800
|
|
#define mmKERNEL_TENSOR_15_TPC2_CFG_BASE 0x7FFCE86748ull
|
|
#define KERNEL_TENSOR_15_TPC2_CFG_MAX_OFFSET 0x3800
|
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#define KERNEL_TENSOR_15_TPC2_CFG_SECTION 0x3800
|
|
#define mmKERNEL_SYNC_OBJECT_TPC2_CFG_BASE 0x7FFCE86780ull
|
|
#define KERNEL_SYNC_OBJECT_TPC2_CFG_MAX_OFFSET 0x8000
|
|
#define KERNEL_SYNC_OBJECT_TPC2_CFG_SECTION 0x8000
|
|
#define mmKERNEL_TPC2_CFG_BASE 0x7FFCE86788ull
|
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#define KERNEL_TPC2_CFG_MAX_OFFSET 0xB800
|
|
#define KERNEL_TPC2_CFG_SECTION 0x2780
|
|
#define mmQM_TENSOR_0_TPC2_CFG_BASE 0x7FFCE86A00ull
|
|
#define QM_TENSOR_0_TPC2_CFG_MAX_OFFSET 0x3800
|
|
#define QM_TENSOR_0_TPC2_CFG_SECTION 0x3800
|
|
#define mmQM_TENSOR_1_TPC2_CFG_BASE 0x7FFCE86A38ull
|
|
#define QM_TENSOR_1_TPC2_CFG_MAX_OFFSET 0x3800
|
|
#define QM_TENSOR_1_TPC2_CFG_SECTION 0x3800
|
|
#define mmQM_TENSOR_2_TPC2_CFG_BASE 0x7FFCE86A70ull
|
|
#define QM_TENSOR_2_TPC2_CFG_MAX_OFFSET 0x3800
|
|
#define QM_TENSOR_2_TPC2_CFG_SECTION 0x3800
|
|
#define mmQM_TENSOR_3_TPC2_CFG_BASE 0x7FFCE86AA8ull
|
|
#define QM_TENSOR_3_TPC2_CFG_MAX_OFFSET 0x3800
|
|
#define QM_TENSOR_3_TPC2_CFG_SECTION 0x3800
|
|
#define mmQM_TENSOR_4_TPC2_CFG_BASE 0x7FFCE86AE0ull
|
|
#define QM_TENSOR_4_TPC2_CFG_MAX_OFFSET 0x3800
|
|
#define QM_TENSOR_4_TPC2_CFG_SECTION 0x3800
|
|
#define mmQM_TENSOR_5_TPC2_CFG_BASE 0x7FFCE86B18ull
|
|
#define QM_TENSOR_5_TPC2_CFG_MAX_OFFSET 0x3800
|
|
#define QM_TENSOR_5_TPC2_CFG_SECTION 0x3800
|
|
#define mmQM_TENSOR_6_TPC2_CFG_BASE 0x7FFCE86B50ull
|
|
#define QM_TENSOR_6_TPC2_CFG_MAX_OFFSET 0x3800
|
|
#define QM_TENSOR_6_TPC2_CFG_SECTION 0x3800
|
|
#define mmQM_TENSOR_7_TPC2_CFG_BASE 0x7FFCE86B88ull
|
|
#define QM_TENSOR_7_TPC2_CFG_MAX_OFFSET 0x3800
|
|
#define QM_TENSOR_7_TPC2_CFG_SECTION 0x3800
|
|
#define mmQM_TENSOR_8_TPC2_CFG_BASE 0x7FFCE86BC0ull
|
|
#define QM_TENSOR_8_TPC2_CFG_MAX_OFFSET 0x3800
|
|
#define QM_TENSOR_8_TPC2_CFG_SECTION 0x3800
|
|
#define mmQM_TENSOR_9_TPC2_CFG_BASE 0x7FFCE86BF8ull
|
|
#define QM_TENSOR_9_TPC2_CFG_MAX_OFFSET 0x3800
|
|
#define QM_TENSOR_9_TPC2_CFG_SECTION 0x3800
|
|
#define mmQM_TENSOR_10_TPC2_CFG_BASE 0x7FFCE86C30ull
|
|
#define QM_TENSOR_10_TPC2_CFG_MAX_OFFSET 0x3800
|
|
#define QM_TENSOR_10_TPC2_CFG_SECTION 0x3800
|
|
#define mmQM_TENSOR_11_TPC2_CFG_BASE 0x7FFCE86C68ull
|
|
#define QM_TENSOR_11_TPC2_CFG_MAX_OFFSET 0x3800
|
|
#define QM_TENSOR_11_TPC2_CFG_SECTION 0x3800
|
|
#define mmQM_TENSOR_12_TPC2_CFG_BASE 0x7FFCE86CA0ull
|
|
#define QM_TENSOR_12_TPC2_CFG_MAX_OFFSET 0x3800
|
|
#define QM_TENSOR_12_TPC2_CFG_SECTION 0x3800
|
|
#define mmQM_TENSOR_13_TPC2_CFG_BASE 0x7FFCE86CD8ull
|
|
#define QM_TENSOR_13_TPC2_CFG_MAX_OFFSET 0x3800
|
|
#define QM_TENSOR_13_TPC2_CFG_SECTION 0x3800
|
|
#define mmQM_TENSOR_14_TPC2_CFG_BASE 0x7FFCE86D10ull
|
|
#define QM_TENSOR_14_TPC2_CFG_MAX_OFFSET 0x3800
|
|
#define QM_TENSOR_14_TPC2_CFG_SECTION 0x3800
|
|
#define mmQM_TENSOR_15_TPC2_CFG_BASE 0x7FFCE86D48ull
|
|
#define QM_TENSOR_15_TPC2_CFG_MAX_OFFSET 0x3800
|
|
#define QM_TENSOR_15_TPC2_CFG_SECTION 0x3800
|
|
#define mmQM_SYNC_OBJECT_TPC2_CFG_BASE 0x7FFCE86D80ull
|
|
#define QM_SYNC_OBJECT_TPC2_CFG_MAX_OFFSET 0x8000
|
|
#define QM_SYNC_OBJECT_TPC2_CFG_SECTION 0x8000
|
|
#define mmQM_TPC2_CFG_BASE 0x7FFCE86D88ull
|
|
#define QM_TPC2_CFG_MAX_OFFSET 0xB800
|
|
#define QM_TPC2_CFG_SECTION 0x2780
|
|
#define mmTPC2_E2E_CRED_BASE 0x7FFCE87000ull
|
|
#define TPC2_E2E_CRED_MAX_OFFSET 0x1680
|
|
#define TPC2_E2E_CRED_SECTION 0x1000
|
|
#define mmTPC2_QM_BASE 0x7FFCE88000ull
|
|
#define TPC2_QM_MAX_OFFSET 0xD040
|
|
#define TPC2_QM_SECTION 0x3E000
|
|
#define mmTPC3_CFG_BASE 0x7FFCEC6000ull
|
|
#define TPC3_CFG_MAX_OFFSET 0xE400
|
|
#define TPC3_CFG_SECTION 0x4000
|
|
#define mmKERNEL_TENSOR_0_TPC3_CFG_BASE 0x7FFCEC6400ull
|
|
#define KERNEL_TENSOR_0_TPC3_CFG_MAX_OFFSET 0x3800
|
|
#define KERNEL_TENSOR_0_TPC3_CFG_SECTION 0x3800
|
|
#define mmKERNEL_TENSOR_1_TPC3_CFG_BASE 0x7FFCEC6438ull
|
|
#define KERNEL_TENSOR_1_TPC3_CFG_MAX_OFFSET 0x3800
|
|
#define KERNEL_TENSOR_1_TPC3_CFG_SECTION 0x3800
|
|
#define mmKERNEL_TENSOR_2_TPC3_CFG_BASE 0x7FFCEC6470ull
|
|
#define KERNEL_TENSOR_2_TPC3_CFG_MAX_OFFSET 0x3800
|
|
#define KERNEL_TENSOR_2_TPC3_CFG_SECTION 0x3800
|
|
#define mmKERNEL_TENSOR_3_TPC3_CFG_BASE 0x7FFCEC64A8ull
|
|
#define KERNEL_TENSOR_3_TPC3_CFG_MAX_OFFSET 0x3800
|
|
#define KERNEL_TENSOR_3_TPC3_CFG_SECTION 0x3800
|
|
#define mmKERNEL_TENSOR_4_TPC3_CFG_BASE 0x7FFCEC64E0ull
|
|
#define KERNEL_TENSOR_4_TPC3_CFG_MAX_OFFSET 0x3800
|
|
#define KERNEL_TENSOR_4_TPC3_CFG_SECTION 0x3800
|
|
#define mmKERNEL_TENSOR_5_TPC3_CFG_BASE 0x7FFCEC6518ull
|
|
#define KERNEL_TENSOR_5_TPC3_CFG_MAX_OFFSET 0x3800
|
|
#define KERNEL_TENSOR_5_TPC3_CFG_SECTION 0x3800
|
|
#define mmKERNEL_TENSOR_6_TPC3_CFG_BASE 0x7FFCEC6550ull
|
|
#define KERNEL_TENSOR_6_TPC3_CFG_MAX_OFFSET 0x3800
|
|
#define KERNEL_TENSOR_6_TPC3_CFG_SECTION 0x3800
|
|
#define mmKERNEL_TENSOR_7_TPC3_CFG_BASE 0x7FFCEC6588ull
|
|
#define KERNEL_TENSOR_7_TPC3_CFG_MAX_OFFSET 0x3800
|
|
#define KERNEL_TENSOR_7_TPC3_CFG_SECTION 0x3800
|
|
#define mmKERNEL_TENSOR_8_TPC3_CFG_BASE 0x7FFCEC65C0ull
|
|
#define KERNEL_TENSOR_8_TPC3_CFG_MAX_OFFSET 0x3800
|
|
#define KERNEL_TENSOR_8_TPC3_CFG_SECTION 0x3800
|
|
#define mmKERNEL_TENSOR_9_TPC3_CFG_BASE 0x7FFCEC65F8ull
|
|
#define KERNEL_TENSOR_9_TPC3_CFG_MAX_OFFSET 0x3800
|
|
#define KERNEL_TENSOR_9_TPC3_CFG_SECTION 0x3800
|
|
#define mmKERNEL_TENSOR_10_TPC3_CFG_BASE 0x7FFCEC6630ull
|
|
#define KERNEL_TENSOR_10_TPC3_CFG_MAX_OFFSET 0x3800
|
|
#define KERNEL_TENSOR_10_TPC3_CFG_SECTION 0x3800
|
|
#define mmKERNEL_TENSOR_11_TPC3_CFG_BASE 0x7FFCEC6668ull
|
|
#define KERNEL_TENSOR_11_TPC3_CFG_MAX_OFFSET 0x3800
|
|
#define KERNEL_TENSOR_11_TPC3_CFG_SECTION 0x3800
|
|
#define mmKERNEL_TENSOR_12_TPC3_CFG_BASE 0x7FFCEC66A0ull
|
|
#define KERNEL_TENSOR_12_TPC3_CFG_MAX_OFFSET 0x3800
|
|
#define KERNEL_TENSOR_12_TPC3_CFG_SECTION 0x3800
|
|
#define mmKERNEL_TENSOR_13_TPC3_CFG_BASE 0x7FFCEC66D8ull
|
|
#define KERNEL_TENSOR_13_TPC3_CFG_MAX_OFFSET 0x3800
|
|
#define KERNEL_TENSOR_13_TPC3_CFG_SECTION 0x3800
|
|
#define mmKERNEL_TENSOR_14_TPC3_CFG_BASE 0x7FFCEC6710ull
|
|
#define KERNEL_TENSOR_14_TPC3_CFG_MAX_OFFSET 0x3800
|
|
#define KERNEL_TENSOR_14_TPC3_CFG_SECTION 0x3800
|
|
#define mmKERNEL_TENSOR_15_TPC3_CFG_BASE 0x7FFCEC6748ull
|
|
#define KERNEL_TENSOR_15_TPC3_CFG_MAX_OFFSET 0x3800
|
|
#define KERNEL_TENSOR_15_TPC3_CFG_SECTION 0x3800
|
|
#define mmKERNEL_SYNC_OBJECT_TPC3_CFG_BASE 0x7FFCEC6780ull
|
|
#define KERNEL_SYNC_OBJECT_TPC3_CFG_MAX_OFFSET 0x8000
|
|
#define KERNEL_SYNC_OBJECT_TPC3_CFG_SECTION 0x8000
|
|
#define mmKERNEL_TPC3_CFG_BASE 0x7FFCEC6788ull
|
|
#define KERNEL_TPC3_CFG_MAX_OFFSET 0xB800
|
|
#define KERNEL_TPC3_CFG_SECTION 0x2780
|
|
#define mmQM_TENSOR_0_TPC3_CFG_BASE 0x7FFCEC6A00ull
|
|
#define QM_TENSOR_0_TPC3_CFG_MAX_OFFSET 0x3800
|
|
#define QM_TENSOR_0_TPC3_CFG_SECTION 0x3800
|
|
#define mmQM_TENSOR_1_TPC3_CFG_BASE 0x7FFCEC6A38ull
|
|
#define QM_TENSOR_1_TPC3_CFG_MAX_OFFSET 0x3800
|
|
#define QM_TENSOR_1_TPC3_CFG_SECTION 0x3800
|
|
#define mmQM_TENSOR_2_TPC3_CFG_BASE 0x7FFCEC6A70ull
|
|
#define QM_TENSOR_2_TPC3_CFG_MAX_OFFSET 0x3800
|
|
#define QM_TENSOR_2_TPC3_CFG_SECTION 0x3800
|
|
#define mmQM_TENSOR_3_TPC3_CFG_BASE 0x7FFCEC6AA8ull
|
|
#define QM_TENSOR_3_TPC3_CFG_MAX_OFFSET 0x3800
|
|
#define QM_TENSOR_3_TPC3_CFG_SECTION 0x3800
|
|
#define mmQM_TENSOR_4_TPC3_CFG_BASE 0x7FFCEC6AE0ull
|
|
#define QM_TENSOR_4_TPC3_CFG_MAX_OFFSET 0x3800
|
|
#define QM_TENSOR_4_TPC3_CFG_SECTION 0x3800
|
|
#define mmQM_TENSOR_5_TPC3_CFG_BASE 0x7FFCEC6B18ull
|
|
#define QM_TENSOR_5_TPC3_CFG_MAX_OFFSET 0x3800
|
|
#define QM_TENSOR_5_TPC3_CFG_SECTION 0x3800
|
|
#define mmQM_TENSOR_6_TPC3_CFG_BASE 0x7FFCEC6B50ull
|
|
#define QM_TENSOR_6_TPC3_CFG_MAX_OFFSET 0x3800
|
|
#define QM_TENSOR_6_TPC3_CFG_SECTION 0x3800
|
|
#define mmQM_TENSOR_7_TPC3_CFG_BASE 0x7FFCEC6B88ull
|
|
#define QM_TENSOR_7_TPC3_CFG_MAX_OFFSET 0x3800
|
|
#define QM_TENSOR_7_TPC3_CFG_SECTION 0x3800
|
|
#define mmQM_TENSOR_8_TPC3_CFG_BASE 0x7FFCEC6BC0ull
|
|
#define QM_TENSOR_8_TPC3_CFG_MAX_OFFSET 0x3800
|
|
#define QM_TENSOR_8_TPC3_CFG_SECTION 0x3800
|
|
#define mmQM_TENSOR_9_TPC3_CFG_BASE 0x7FFCEC6BF8ull
|
|
#define QM_TENSOR_9_TPC3_CFG_MAX_OFFSET 0x3800
|
|
#define QM_TENSOR_9_TPC3_CFG_SECTION 0x3800
|
|
#define mmQM_TENSOR_10_TPC3_CFG_BASE 0x7FFCEC6C30ull
|
|
#define QM_TENSOR_10_TPC3_CFG_MAX_OFFSET 0x3800
|
|
#define QM_TENSOR_10_TPC3_CFG_SECTION 0x3800
|
|
#define mmQM_TENSOR_11_TPC3_CFG_BASE 0x7FFCEC6C68ull
|
|
#define QM_TENSOR_11_TPC3_CFG_MAX_OFFSET 0x3800
|
|
#define QM_TENSOR_11_TPC3_CFG_SECTION 0x3800
|
|
#define mmQM_TENSOR_12_TPC3_CFG_BASE 0x7FFCEC6CA0ull
|
|
#define QM_TENSOR_12_TPC3_CFG_MAX_OFFSET 0x3800
|
|
#define QM_TENSOR_12_TPC3_CFG_SECTION 0x3800
|
|
#define mmQM_TENSOR_13_TPC3_CFG_BASE 0x7FFCEC6CD8ull
|
|
#define QM_TENSOR_13_TPC3_CFG_MAX_OFFSET 0x3800
|
|
#define QM_TENSOR_13_TPC3_CFG_SECTION 0x3800
|
|
#define mmQM_TENSOR_14_TPC3_CFG_BASE 0x7FFCEC6D10ull
|
|
#define QM_TENSOR_14_TPC3_CFG_MAX_OFFSET 0x3800
|
|
#define QM_TENSOR_14_TPC3_CFG_SECTION 0x3800
|
|
#define mmQM_TENSOR_15_TPC3_CFG_BASE 0x7FFCEC6D48ull
|
|
#define QM_TENSOR_15_TPC3_CFG_MAX_OFFSET 0x3800
|
|
#define QM_TENSOR_15_TPC3_CFG_SECTION 0x3800
|
|
#define mmQM_SYNC_OBJECT_TPC3_CFG_BASE 0x7FFCEC6D80ull
|
|
#define QM_SYNC_OBJECT_TPC3_CFG_MAX_OFFSET 0x8000
|
|
#define QM_SYNC_OBJECT_TPC3_CFG_SECTION 0x8000
|
|
#define mmQM_TPC3_CFG_BASE 0x7FFCEC6D88ull
|
|
#define QM_TPC3_CFG_MAX_OFFSET 0xB800
|
|
#define QM_TPC3_CFG_SECTION 0x2780
|
|
#define mmTPC3_E2E_CRED_BASE 0x7FFCEC7000ull
|
|
#define TPC3_E2E_CRED_MAX_OFFSET 0x1680
|
|
#define TPC3_E2E_CRED_SECTION 0x1000
|
|
#define mmTPC3_QM_BASE 0x7FFCEC8000ull
|
|
#define TPC3_QM_MAX_OFFSET 0xD040
|
|
#define TPC3_QM_SECTION 0x3E000
|
|
#define mmTPC4_CFG_BASE 0x7FFCF06000ull
|
|
#define TPC4_CFG_MAX_OFFSET 0xE400
|
|
#define TPC4_CFG_SECTION 0x4000
|
|
#define mmKERNEL_TENSOR_0_TPC4_CFG_BASE 0x7FFCF06400ull
|
|
#define KERNEL_TENSOR_0_TPC4_CFG_MAX_OFFSET 0x3800
|
|
#define KERNEL_TENSOR_0_TPC4_CFG_SECTION 0x3800
|
|
#define mmKERNEL_TENSOR_1_TPC4_CFG_BASE 0x7FFCF06438ull
|
|
#define KERNEL_TENSOR_1_TPC4_CFG_MAX_OFFSET 0x3800
|
|
#define KERNEL_TENSOR_1_TPC4_CFG_SECTION 0x3800
|
|
#define mmKERNEL_TENSOR_2_TPC4_CFG_BASE 0x7FFCF06470ull
|
|
#define KERNEL_TENSOR_2_TPC4_CFG_MAX_OFFSET 0x3800
|
|
#define KERNEL_TENSOR_2_TPC4_CFG_SECTION 0x3800
|
|
#define mmKERNEL_TENSOR_3_TPC4_CFG_BASE 0x7FFCF064A8ull
|
|
#define KERNEL_TENSOR_3_TPC4_CFG_MAX_OFFSET 0x3800
|
|
#define KERNEL_TENSOR_3_TPC4_CFG_SECTION 0x3800
|
|
#define mmKERNEL_TENSOR_4_TPC4_CFG_BASE 0x7FFCF064E0ull
|
|
#define KERNEL_TENSOR_4_TPC4_CFG_MAX_OFFSET 0x3800
|
|
#define KERNEL_TENSOR_4_TPC4_CFG_SECTION 0x3800
|
|
#define mmKERNEL_TENSOR_5_TPC4_CFG_BASE 0x7FFCF06518ull
|
|
#define KERNEL_TENSOR_5_TPC4_CFG_MAX_OFFSET 0x3800
|
|
#define KERNEL_TENSOR_5_TPC4_CFG_SECTION 0x3800
|
|
#define mmKERNEL_TENSOR_6_TPC4_CFG_BASE 0x7FFCF06550ull
|
|
#define KERNEL_TENSOR_6_TPC4_CFG_MAX_OFFSET 0x3800
|
|
#define KERNEL_TENSOR_6_TPC4_CFG_SECTION 0x3800
|
|
#define mmKERNEL_TENSOR_7_TPC4_CFG_BASE 0x7FFCF06588ull
|
|
#define KERNEL_TENSOR_7_TPC4_CFG_MAX_OFFSET 0x3800
|
|
#define KERNEL_TENSOR_7_TPC4_CFG_SECTION 0x3800
|
|
#define mmKERNEL_TENSOR_8_TPC4_CFG_BASE 0x7FFCF065C0ull
|
|
#define KERNEL_TENSOR_8_TPC4_CFG_MAX_OFFSET 0x3800
|
|
#define KERNEL_TENSOR_8_TPC4_CFG_SECTION 0x3800
|
|
#define mmKERNEL_TENSOR_9_TPC4_CFG_BASE 0x7FFCF065F8ull
|
|
#define KERNEL_TENSOR_9_TPC4_CFG_MAX_OFFSET 0x3800
|
|
#define KERNEL_TENSOR_9_TPC4_CFG_SECTION 0x3800
|
|
#define mmKERNEL_TENSOR_10_TPC4_CFG_BASE 0x7FFCF06630ull
|
|
#define KERNEL_TENSOR_10_TPC4_CFG_MAX_OFFSET 0x3800
|
|
#define KERNEL_TENSOR_10_TPC4_CFG_SECTION 0x3800
|
|
#define mmKERNEL_TENSOR_11_TPC4_CFG_BASE 0x7FFCF06668ull
|
|
#define KERNEL_TENSOR_11_TPC4_CFG_MAX_OFFSET 0x3800
|
|
#define KERNEL_TENSOR_11_TPC4_CFG_SECTION 0x3800
|
|
#define mmKERNEL_TENSOR_12_TPC4_CFG_BASE 0x7FFCF066A0ull
|
|
#define KERNEL_TENSOR_12_TPC4_CFG_MAX_OFFSET 0x3800
|
|
#define KERNEL_TENSOR_12_TPC4_CFG_SECTION 0x3800
|
|
#define mmKERNEL_TENSOR_13_TPC4_CFG_BASE 0x7FFCF066D8ull
|
|
#define KERNEL_TENSOR_13_TPC4_CFG_MAX_OFFSET 0x3800
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#define KERNEL_TENSOR_13_TPC4_CFG_SECTION 0x3800
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#define mmKERNEL_TENSOR_14_TPC4_CFG_BASE 0x7FFCF06710ull
|
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#define KERNEL_TENSOR_14_TPC4_CFG_MAX_OFFSET 0x3800
|
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#define KERNEL_TENSOR_14_TPC4_CFG_SECTION 0x3800
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#define mmKERNEL_TENSOR_15_TPC4_CFG_BASE 0x7FFCF06748ull
|
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#define KERNEL_TENSOR_15_TPC4_CFG_MAX_OFFSET 0x3800
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#define KERNEL_TENSOR_15_TPC4_CFG_SECTION 0x3800
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#define mmKERNEL_SYNC_OBJECT_TPC4_CFG_BASE 0x7FFCF06780ull
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#define KERNEL_SYNC_OBJECT_TPC4_CFG_MAX_OFFSET 0x8000
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#define KERNEL_SYNC_OBJECT_TPC4_CFG_SECTION 0x8000
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#define mmKERNEL_TPC4_CFG_BASE 0x7FFCF06788ull
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#define KERNEL_TPC4_CFG_MAX_OFFSET 0xB800
|
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#define KERNEL_TPC4_CFG_SECTION 0x2780
|
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#define mmQM_TENSOR_0_TPC4_CFG_BASE 0x7FFCF06A00ull
|
|
#define QM_TENSOR_0_TPC4_CFG_MAX_OFFSET 0x3800
|
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#define QM_TENSOR_0_TPC4_CFG_SECTION 0x3800
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#define mmQM_TENSOR_1_TPC4_CFG_BASE 0x7FFCF06A38ull
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#define QM_TENSOR_1_TPC4_CFG_MAX_OFFSET 0x3800
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#define QM_TENSOR_1_TPC4_CFG_SECTION 0x3800
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#define mmQM_TENSOR_2_TPC4_CFG_BASE 0x7FFCF06A70ull
|
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#define QM_TENSOR_2_TPC4_CFG_MAX_OFFSET 0x3800
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#define QM_TENSOR_2_TPC4_CFG_SECTION 0x3800
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#define mmQM_TENSOR_3_TPC4_CFG_BASE 0x7FFCF06AA8ull
|
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#define QM_TENSOR_3_TPC4_CFG_MAX_OFFSET 0x3800
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#define QM_TENSOR_3_TPC4_CFG_SECTION 0x3800
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#define mmQM_TENSOR_4_TPC4_CFG_BASE 0x7FFCF06AE0ull
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#define QM_TENSOR_4_TPC4_CFG_MAX_OFFSET 0x3800
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#define QM_TENSOR_4_TPC4_CFG_SECTION 0x3800
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#define mmQM_TENSOR_5_TPC4_CFG_BASE 0x7FFCF06B18ull
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#define QM_TENSOR_5_TPC4_CFG_MAX_OFFSET 0x3800
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#define QM_TENSOR_5_TPC4_CFG_SECTION 0x3800
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#define mmQM_TENSOR_6_TPC4_CFG_BASE 0x7FFCF06B50ull
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#define QM_TENSOR_6_TPC4_CFG_MAX_OFFSET 0x3800
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#define QM_TENSOR_6_TPC4_CFG_SECTION 0x3800
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#define mmQM_TENSOR_7_TPC4_CFG_BASE 0x7FFCF06B88ull
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#define QM_TENSOR_7_TPC4_CFG_MAX_OFFSET 0x3800
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#define QM_TENSOR_7_TPC4_CFG_SECTION 0x3800
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#define mmQM_TENSOR_8_TPC4_CFG_BASE 0x7FFCF06BC0ull
|
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#define QM_TENSOR_8_TPC4_CFG_MAX_OFFSET 0x3800
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#define QM_TENSOR_8_TPC4_CFG_SECTION 0x3800
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#define mmQM_TENSOR_9_TPC4_CFG_BASE 0x7FFCF06BF8ull
|
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#define QM_TENSOR_9_TPC4_CFG_MAX_OFFSET 0x3800
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#define QM_TENSOR_9_TPC4_CFG_SECTION 0x3800
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#define mmQM_TENSOR_10_TPC4_CFG_BASE 0x7FFCF06C30ull
|
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#define QM_TENSOR_10_TPC4_CFG_MAX_OFFSET 0x3800
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|
#define QM_TENSOR_10_TPC4_CFG_SECTION 0x3800
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|
#define mmQM_TENSOR_11_TPC4_CFG_BASE 0x7FFCF06C68ull
|
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#define QM_TENSOR_11_TPC4_CFG_MAX_OFFSET 0x3800
|
|
#define QM_TENSOR_11_TPC4_CFG_SECTION 0x3800
|
|
#define mmQM_TENSOR_12_TPC4_CFG_BASE 0x7FFCF06CA0ull
|
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#define QM_TENSOR_12_TPC4_CFG_MAX_OFFSET 0x3800
|
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#define QM_TENSOR_12_TPC4_CFG_SECTION 0x3800
|
|
#define mmQM_TENSOR_13_TPC4_CFG_BASE 0x7FFCF06CD8ull
|
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#define QM_TENSOR_13_TPC4_CFG_MAX_OFFSET 0x3800
|
|
#define QM_TENSOR_13_TPC4_CFG_SECTION 0x3800
|
|
#define mmQM_TENSOR_14_TPC4_CFG_BASE 0x7FFCF06D10ull
|
|
#define QM_TENSOR_14_TPC4_CFG_MAX_OFFSET 0x3800
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|
#define QM_TENSOR_14_TPC4_CFG_SECTION 0x3800
|
|
#define mmQM_TENSOR_15_TPC4_CFG_BASE 0x7FFCF06D48ull
|
|
#define QM_TENSOR_15_TPC4_CFG_MAX_OFFSET 0x3800
|
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#define QM_TENSOR_15_TPC4_CFG_SECTION 0x3800
|
|
#define mmQM_SYNC_OBJECT_TPC4_CFG_BASE 0x7FFCF06D80ull
|
|
#define QM_SYNC_OBJECT_TPC4_CFG_MAX_OFFSET 0x8000
|
|
#define QM_SYNC_OBJECT_TPC4_CFG_SECTION 0x8000
|
|
#define mmQM_TPC4_CFG_BASE 0x7FFCF06D88ull
|
|
#define QM_TPC4_CFG_MAX_OFFSET 0xB800
|
|
#define QM_TPC4_CFG_SECTION 0x2780
|
|
#define mmTPC4_E2E_CRED_BASE 0x7FFCF07000ull
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|
#define TPC4_E2E_CRED_MAX_OFFSET 0x1680
|
|
#define TPC4_E2E_CRED_SECTION 0x1000
|
|
#define mmTPC4_QM_BASE 0x7FFCF08000ull
|
|
#define TPC4_QM_MAX_OFFSET 0xD040
|
|
#define TPC4_QM_SECTION 0x3E000
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|
#define mmTPC5_CFG_BASE 0x7FFCF46000ull
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|
#define TPC5_CFG_MAX_OFFSET 0xE400
|
|
#define TPC5_CFG_SECTION 0x4000
|
|
#define mmKERNEL_TENSOR_0_TPC5_CFG_BASE 0x7FFCF46400ull
|
|
#define KERNEL_TENSOR_0_TPC5_CFG_MAX_OFFSET 0x3800
|
|
#define KERNEL_TENSOR_0_TPC5_CFG_SECTION 0x3800
|
|
#define mmKERNEL_TENSOR_1_TPC5_CFG_BASE 0x7FFCF46438ull
|
|
#define KERNEL_TENSOR_1_TPC5_CFG_MAX_OFFSET 0x3800
|
|
#define KERNEL_TENSOR_1_TPC5_CFG_SECTION 0x3800
|
|
#define mmKERNEL_TENSOR_2_TPC5_CFG_BASE 0x7FFCF46470ull
|
|
#define KERNEL_TENSOR_2_TPC5_CFG_MAX_OFFSET 0x3800
|
|
#define KERNEL_TENSOR_2_TPC5_CFG_SECTION 0x3800
|
|
#define mmKERNEL_TENSOR_3_TPC5_CFG_BASE 0x7FFCF464A8ull
|
|
#define KERNEL_TENSOR_3_TPC5_CFG_MAX_OFFSET 0x3800
|
|
#define KERNEL_TENSOR_3_TPC5_CFG_SECTION 0x3800
|
|
#define mmKERNEL_TENSOR_4_TPC5_CFG_BASE 0x7FFCF464E0ull
|
|
#define KERNEL_TENSOR_4_TPC5_CFG_MAX_OFFSET 0x3800
|
|
#define KERNEL_TENSOR_4_TPC5_CFG_SECTION 0x3800
|
|
#define mmKERNEL_TENSOR_5_TPC5_CFG_BASE 0x7FFCF46518ull
|
|
#define KERNEL_TENSOR_5_TPC5_CFG_MAX_OFFSET 0x3800
|
|
#define KERNEL_TENSOR_5_TPC5_CFG_SECTION 0x3800
|
|
#define mmKERNEL_TENSOR_6_TPC5_CFG_BASE 0x7FFCF46550ull
|
|
#define KERNEL_TENSOR_6_TPC5_CFG_MAX_OFFSET 0x3800
|
|
#define KERNEL_TENSOR_6_TPC5_CFG_SECTION 0x3800
|
|
#define mmKERNEL_TENSOR_7_TPC5_CFG_BASE 0x7FFCF46588ull
|
|
#define KERNEL_TENSOR_7_TPC5_CFG_MAX_OFFSET 0x3800
|
|
#define KERNEL_TENSOR_7_TPC5_CFG_SECTION 0x3800
|
|
#define mmKERNEL_TENSOR_8_TPC5_CFG_BASE 0x7FFCF465C0ull
|
|
#define KERNEL_TENSOR_8_TPC5_CFG_MAX_OFFSET 0x3800
|
|
#define KERNEL_TENSOR_8_TPC5_CFG_SECTION 0x3800
|
|
#define mmKERNEL_TENSOR_9_TPC5_CFG_BASE 0x7FFCF465F8ull
|
|
#define KERNEL_TENSOR_9_TPC5_CFG_MAX_OFFSET 0x3800
|
|
#define KERNEL_TENSOR_9_TPC5_CFG_SECTION 0x3800
|
|
#define mmKERNEL_TENSOR_10_TPC5_CFG_BASE 0x7FFCF46630ull
|
|
#define KERNEL_TENSOR_10_TPC5_CFG_MAX_OFFSET 0x3800
|
|
#define KERNEL_TENSOR_10_TPC5_CFG_SECTION 0x3800
|
|
#define mmKERNEL_TENSOR_11_TPC5_CFG_BASE 0x7FFCF46668ull
|
|
#define KERNEL_TENSOR_11_TPC5_CFG_MAX_OFFSET 0x3800
|
|
#define KERNEL_TENSOR_11_TPC5_CFG_SECTION 0x3800
|
|
#define mmKERNEL_TENSOR_12_TPC5_CFG_BASE 0x7FFCF466A0ull
|
|
#define KERNEL_TENSOR_12_TPC5_CFG_MAX_OFFSET 0x3800
|
|
#define KERNEL_TENSOR_12_TPC5_CFG_SECTION 0x3800
|
|
#define mmKERNEL_TENSOR_13_TPC5_CFG_BASE 0x7FFCF466D8ull
|
|
#define KERNEL_TENSOR_13_TPC5_CFG_MAX_OFFSET 0x3800
|
|
#define KERNEL_TENSOR_13_TPC5_CFG_SECTION 0x3800
|
|
#define mmKERNEL_TENSOR_14_TPC5_CFG_BASE 0x7FFCF46710ull
|
|
#define KERNEL_TENSOR_14_TPC5_CFG_MAX_OFFSET 0x3800
|
|
#define KERNEL_TENSOR_14_TPC5_CFG_SECTION 0x3800
|
|
#define mmKERNEL_TENSOR_15_TPC5_CFG_BASE 0x7FFCF46748ull
|
|
#define KERNEL_TENSOR_15_TPC5_CFG_MAX_OFFSET 0x3800
|
|
#define KERNEL_TENSOR_15_TPC5_CFG_SECTION 0x3800
|
|
#define mmKERNEL_SYNC_OBJECT_TPC5_CFG_BASE 0x7FFCF46780ull
|
|
#define KERNEL_SYNC_OBJECT_TPC5_CFG_MAX_OFFSET 0x8000
|
|
#define KERNEL_SYNC_OBJECT_TPC5_CFG_SECTION 0x8000
|
|
#define mmKERNEL_TPC5_CFG_BASE 0x7FFCF46788ull
|
|
#define KERNEL_TPC5_CFG_MAX_OFFSET 0xB800
|
|
#define KERNEL_TPC5_CFG_SECTION 0x2780
|
|
#define mmQM_TENSOR_0_TPC5_CFG_BASE 0x7FFCF46A00ull
|
|
#define QM_TENSOR_0_TPC5_CFG_MAX_OFFSET 0x3800
|
|
#define QM_TENSOR_0_TPC5_CFG_SECTION 0x3800
|
|
#define mmQM_TENSOR_1_TPC5_CFG_BASE 0x7FFCF46A38ull
|
|
#define QM_TENSOR_1_TPC5_CFG_MAX_OFFSET 0x3800
|
|
#define QM_TENSOR_1_TPC5_CFG_SECTION 0x3800
|
|
#define mmQM_TENSOR_2_TPC5_CFG_BASE 0x7FFCF46A70ull
|
|
#define QM_TENSOR_2_TPC5_CFG_MAX_OFFSET 0x3800
|
|
#define QM_TENSOR_2_TPC5_CFG_SECTION 0x3800
|
|
#define mmQM_TENSOR_3_TPC5_CFG_BASE 0x7FFCF46AA8ull
|
|
#define QM_TENSOR_3_TPC5_CFG_MAX_OFFSET 0x3800
|
|
#define QM_TENSOR_3_TPC5_CFG_SECTION 0x3800
|
|
#define mmQM_TENSOR_4_TPC5_CFG_BASE 0x7FFCF46AE0ull
|
|
#define QM_TENSOR_4_TPC5_CFG_MAX_OFFSET 0x3800
|
|
#define QM_TENSOR_4_TPC5_CFG_SECTION 0x3800
|
|
#define mmQM_TENSOR_5_TPC5_CFG_BASE 0x7FFCF46B18ull
|
|
#define QM_TENSOR_5_TPC5_CFG_MAX_OFFSET 0x3800
|
|
#define QM_TENSOR_5_TPC5_CFG_SECTION 0x3800
|
|
#define mmQM_TENSOR_6_TPC5_CFG_BASE 0x7FFCF46B50ull
|
|
#define QM_TENSOR_6_TPC5_CFG_MAX_OFFSET 0x3800
|
|
#define QM_TENSOR_6_TPC5_CFG_SECTION 0x3800
|
|
#define mmQM_TENSOR_7_TPC5_CFG_BASE 0x7FFCF46B88ull
|
|
#define QM_TENSOR_7_TPC5_CFG_MAX_OFFSET 0x3800
|
|
#define QM_TENSOR_7_TPC5_CFG_SECTION 0x3800
|
|
#define mmQM_TENSOR_8_TPC5_CFG_BASE 0x7FFCF46BC0ull
|
|
#define QM_TENSOR_8_TPC5_CFG_MAX_OFFSET 0x3800
|
|
#define QM_TENSOR_8_TPC5_CFG_SECTION 0x3800
|
|
#define mmQM_TENSOR_9_TPC5_CFG_BASE 0x7FFCF46BF8ull
|
|
#define QM_TENSOR_9_TPC5_CFG_MAX_OFFSET 0x3800
|
|
#define QM_TENSOR_9_TPC5_CFG_SECTION 0x3800
|
|
#define mmQM_TENSOR_10_TPC5_CFG_BASE 0x7FFCF46C30ull
|
|
#define QM_TENSOR_10_TPC5_CFG_MAX_OFFSET 0x3800
|
|
#define QM_TENSOR_10_TPC5_CFG_SECTION 0x3800
|
|
#define mmQM_TENSOR_11_TPC5_CFG_BASE 0x7FFCF46C68ull
|
|
#define QM_TENSOR_11_TPC5_CFG_MAX_OFFSET 0x3800
|
|
#define QM_TENSOR_11_TPC5_CFG_SECTION 0x3800
|
|
#define mmQM_TENSOR_12_TPC5_CFG_BASE 0x7FFCF46CA0ull
|
|
#define QM_TENSOR_12_TPC5_CFG_MAX_OFFSET 0x3800
|
|
#define QM_TENSOR_12_TPC5_CFG_SECTION 0x3800
|
|
#define mmQM_TENSOR_13_TPC5_CFG_BASE 0x7FFCF46CD8ull
|
|
#define QM_TENSOR_13_TPC5_CFG_MAX_OFFSET 0x3800
|
|
#define QM_TENSOR_13_TPC5_CFG_SECTION 0x3800
|
|
#define mmQM_TENSOR_14_TPC5_CFG_BASE 0x7FFCF46D10ull
|
|
#define QM_TENSOR_14_TPC5_CFG_MAX_OFFSET 0x3800
|
|
#define QM_TENSOR_14_TPC5_CFG_SECTION 0x3800
|
|
#define mmQM_TENSOR_15_TPC5_CFG_BASE 0x7FFCF46D48ull
|
|
#define QM_TENSOR_15_TPC5_CFG_MAX_OFFSET 0x3800
|
|
#define QM_TENSOR_15_TPC5_CFG_SECTION 0x3800
|
|
#define mmQM_SYNC_OBJECT_TPC5_CFG_BASE 0x7FFCF46D80ull
|
|
#define QM_SYNC_OBJECT_TPC5_CFG_MAX_OFFSET 0x8000
|
|
#define QM_SYNC_OBJECT_TPC5_CFG_SECTION 0x8000
|
|
#define mmQM_TPC5_CFG_BASE 0x7FFCF46D88ull
|
|
#define QM_TPC5_CFG_MAX_OFFSET 0xB800
|
|
#define QM_TPC5_CFG_SECTION 0x2780
|
|
#define mmTPC5_E2E_CRED_BASE 0x7FFCF47000ull
|
|
#define TPC5_E2E_CRED_MAX_OFFSET 0x1680
|
|
#define TPC5_E2E_CRED_SECTION 0x1000
|
|
#define mmTPC5_QM_BASE 0x7FFCF48000ull
|
|
#define TPC5_QM_MAX_OFFSET 0xD040
|
|
#define TPC5_QM_SECTION 0x3E000
|
|
#define mmTPC6_CFG_BASE 0x7FFCF86000ull
|
|
#define TPC6_CFG_MAX_OFFSET 0xE400
|
|
#define TPC6_CFG_SECTION 0x4000
|
|
#define mmKERNEL_TENSOR_0_TPC6_CFG_BASE 0x7FFCF86400ull
|
|
#define KERNEL_TENSOR_0_TPC6_CFG_MAX_OFFSET 0x3800
|
|
#define KERNEL_TENSOR_0_TPC6_CFG_SECTION 0x3800
|
|
#define mmKERNEL_TENSOR_1_TPC6_CFG_BASE 0x7FFCF86438ull
|
|
#define KERNEL_TENSOR_1_TPC6_CFG_MAX_OFFSET 0x3800
|
|
#define KERNEL_TENSOR_1_TPC6_CFG_SECTION 0x3800
|
|
#define mmKERNEL_TENSOR_2_TPC6_CFG_BASE 0x7FFCF86470ull
|
|
#define KERNEL_TENSOR_2_TPC6_CFG_MAX_OFFSET 0x3800
|
|
#define KERNEL_TENSOR_2_TPC6_CFG_SECTION 0x3800
|
|
#define mmKERNEL_TENSOR_3_TPC6_CFG_BASE 0x7FFCF864A8ull
|
|
#define KERNEL_TENSOR_3_TPC6_CFG_MAX_OFFSET 0x3800
|
|
#define KERNEL_TENSOR_3_TPC6_CFG_SECTION 0x3800
|
|
#define mmKERNEL_TENSOR_4_TPC6_CFG_BASE 0x7FFCF864E0ull
|
|
#define KERNEL_TENSOR_4_TPC6_CFG_MAX_OFFSET 0x3800
|
|
#define KERNEL_TENSOR_4_TPC6_CFG_SECTION 0x3800
|
|
#define mmKERNEL_TENSOR_5_TPC6_CFG_BASE 0x7FFCF86518ull
|
|
#define KERNEL_TENSOR_5_TPC6_CFG_MAX_OFFSET 0x3800
|
|
#define KERNEL_TENSOR_5_TPC6_CFG_SECTION 0x3800
|
|
#define mmKERNEL_TENSOR_6_TPC6_CFG_BASE 0x7FFCF86550ull
|
|
#define KERNEL_TENSOR_6_TPC6_CFG_MAX_OFFSET 0x3800
|
|
#define KERNEL_TENSOR_6_TPC6_CFG_SECTION 0x3800
|
|
#define mmKERNEL_TENSOR_7_TPC6_CFG_BASE 0x7FFCF86588ull
|
|
#define KERNEL_TENSOR_7_TPC6_CFG_MAX_OFFSET 0x3800
|
|
#define KERNEL_TENSOR_7_TPC6_CFG_SECTION 0x3800
|
|
#define mmKERNEL_TENSOR_8_TPC6_CFG_BASE 0x7FFCF865C0ull
|
|
#define KERNEL_TENSOR_8_TPC6_CFG_MAX_OFFSET 0x3800
|
|
#define KERNEL_TENSOR_8_TPC6_CFG_SECTION 0x3800
|
|
#define mmKERNEL_TENSOR_9_TPC6_CFG_BASE 0x7FFCF865F8ull
|
|
#define KERNEL_TENSOR_9_TPC6_CFG_MAX_OFFSET 0x3800
|
|
#define KERNEL_TENSOR_9_TPC6_CFG_SECTION 0x3800
|
|
#define mmKERNEL_TENSOR_10_TPC6_CFG_BASE 0x7FFCF86630ull
|
|
#define KERNEL_TENSOR_10_TPC6_CFG_MAX_OFFSET 0x3800
|
|
#define KERNEL_TENSOR_10_TPC6_CFG_SECTION 0x3800
|
|
#define mmKERNEL_TENSOR_11_TPC6_CFG_BASE 0x7FFCF86668ull
|
|
#define KERNEL_TENSOR_11_TPC6_CFG_MAX_OFFSET 0x3800
|
|
#define KERNEL_TENSOR_11_TPC6_CFG_SECTION 0x3800
|
|
#define mmKERNEL_TENSOR_12_TPC6_CFG_BASE 0x7FFCF866A0ull
|
|
#define KERNEL_TENSOR_12_TPC6_CFG_MAX_OFFSET 0x3800
|
|
#define KERNEL_TENSOR_12_TPC6_CFG_SECTION 0x3800
|
|
#define mmKERNEL_TENSOR_13_TPC6_CFG_BASE 0x7FFCF866D8ull
|
|
#define KERNEL_TENSOR_13_TPC6_CFG_MAX_OFFSET 0x3800
|
|
#define KERNEL_TENSOR_13_TPC6_CFG_SECTION 0x3800
|
|
#define mmKERNEL_TENSOR_14_TPC6_CFG_BASE 0x7FFCF86710ull
|
|
#define KERNEL_TENSOR_14_TPC6_CFG_MAX_OFFSET 0x3800
|
|
#define KERNEL_TENSOR_14_TPC6_CFG_SECTION 0x3800
|
|
#define mmKERNEL_TENSOR_15_TPC6_CFG_BASE 0x7FFCF86748ull
|
|
#define KERNEL_TENSOR_15_TPC6_CFG_MAX_OFFSET 0x3800
|
|
#define KERNEL_TENSOR_15_TPC6_CFG_SECTION 0x3800
|
|
#define mmKERNEL_SYNC_OBJECT_TPC6_CFG_BASE 0x7FFCF86780ull
|
|
#define KERNEL_SYNC_OBJECT_TPC6_CFG_MAX_OFFSET 0x8000
|
|
#define KERNEL_SYNC_OBJECT_TPC6_CFG_SECTION 0x8000
|
|
#define mmKERNEL_TPC6_CFG_BASE 0x7FFCF86788ull
|
|
#define KERNEL_TPC6_CFG_MAX_OFFSET 0xB800
|
|
#define KERNEL_TPC6_CFG_SECTION 0x2780
|
|
#define mmQM_TENSOR_0_TPC6_CFG_BASE 0x7FFCF86A00ull
|
|
#define QM_TENSOR_0_TPC6_CFG_MAX_OFFSET 0x3800
|
|
#define QM_TENSOR_0_TPC6_CFG_SECTION 0x3800
|
|
#define mmQM_TENSOR_1_TPC6_CFG_BASE 0x7FFCF86A38ull
|
|
#define QM_TENSOR_1_TPC6_CFG_MAX_OFFSET 0x3800
|
|
#define QM_TENSOR_1_TPC6_CFG_SECTION 0x3800
|
|
#define mmQM_TENSOR_2_TPC6_CFG_BASE 0x7FFCF86A70ull
|
|
#define QM_TENSOR_2_TPC6_CFG_MAX_OFFSET 0x3800
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#define QM_TENSOR_2_TPC6_CFG_SECTION 0x3800
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#define mmQM_TENSOR_3_TPC6_CFG_BASE 0x7FFCF86AA8ull
|
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#define QM_TENSOR_3_TPC6_CFG_MAX_OFFSET 0x3800
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#define QM_TENSOR_3_TPC6_CFG_SECTION 0x3800
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#define mmQM_TENSOR_4_TPC6_CFG_BASE 0x7FFCF86AE0ull
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#define QM_TENSOR_4_TPC6_CFG_MAX_OFFSET 0x3800
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#define QM_TENSOR_4_TPC6_CFG_SECTION 0x3800
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#define mmQM_TENSOR_5_TPC6_CFG_BASE 0x7FFCF86B18ull
|
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#define QM_TENSOR_5_TPC6_CFG_MAX_OFFSET 0x3800
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#define QM_TENSOR_5_TPC6_CFG_SECTION 0x3800
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#define mmQM_TENSOR_6_TPC6_CFG_BASE 0x7FFCF86B50ull
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#define QM_TENSOR_6_TPC6_CFG_MAX_OFFSET 0x3800
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#define QM_TENSOR_6_TPC6_CFG_SECTION 0x3800
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#define mmQM_TENSOR_7_TPC6_CFG_BASE 0x7FFCF86B88ull
|
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#define QM_TENSOR_7_TPC6_CFG_MAX_OFFSET 0x3800
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#define QM_TENSOR_7_TPC6_CFG_SECTION 0x3800
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#define mmQM_TENSOR_8_TPC6_CFG_BASE 0x7FFCF86BC0ull
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#define QM_TENSOR_8_TPC6_CFG_MAX_OFFSET 0x3800
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#define QM_TENSOR_8_TPC6_CFG_SECTION 0x3800
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#define mmQM_TENSOR_9_TPC6_CFG_BASE 0x7FFCF86BF8ull
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#define QM_TENSOR_9_TPC6_CFG_MAX_OFFSET 0x3800
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#define QM_TENSOR_9_TPC6_CFG_SECTION 0x3800
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#define mmQM_TENSOR_10_TPC6_CFG_BASE 0x7FFCF86C30ull
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#define QM_TENSOR_10_TPC6_CFG_MAX_OFFSET 0x3800
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#define QM_TENSOR_10_TPC6_CFG_SECTION 0x3800
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#define mmQM_TENSOR_11_TPC6_CFG_BASE 0x7FFCF86C68ull
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#define QM_TENSOR_11_TPC6_CFG_MAX_OFFSET 0x3800
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#define QM_TENSOR_11_TPC6_CFG_SECTION 0x3800
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#define mmQM_TENSOR_12_TPC6_CFG_BASE 0x7FFCF86CA0ull
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#define QM_TENSOR_12_TPC6_CFG_MAX_OFFSET 0x3800
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#define QM_TENSOR_12_TPC6_CFG_SECTION 0x3800
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#define mmQM_TENSOR_13_TPC6_CFG_BASE 0x7FFCF86CD8ull
|
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#define QM_TENSOR_13_TPC6_CFG_MAX_OFFSET 0x3800
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#define QM_TENSOR_13_TPC6_CFG_SECTION 0x3800
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#define mmQM_TENSOR_14_TPC6_CFG_BASE 0x7FFCF86D10ull
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#define QM_TENSOR_14_TPC6_CFG_MAX_OFFSET 0x3800
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#define QM_TENSOR_14_TPC6_CFG_SECTION 0x3800
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#define mmQM_TENSOR_15_TPC6_CFG_BASE 0x7FFCF86D48ull
|
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#define QM_TENSOR_15_TPC6_CFG_MAX_OFFSET 0x3800
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#define QM_TENSOR_15_TPC6_CFG_SECTION 0x3800
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#define mmQM_SYNC_OBJECT_TPC6_CFG_BASE 0x7FFCF86D80ull
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#define QM_SYNC_OBJECT_TPC6_CFG_MAX_OFFSET 0x8000
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#define QM_SYNC_OBJECT_TPC6_CFG_SECTION 0x8000
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#define mmQM_TPC6_CFG_BASE 0x7FFCF86D88ull
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#define QM_TPC6_CFG_MAX_OFFSET 0xB800
|
|
#define QM_TPC6_CFG_SECTION 0x2780
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|
#define mmTPC6_E2E_CRED_BASE 0x7FFCF87000ull
|
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#define TPC6_E2E_CRED_MAX_OFFSET 0x1680
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#define TPC6_E2E_CRED_SECTION 0x1000
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|
#define mmTPC6_QM_BASE 0x7FFCF88000ull
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#define TPC6_QM_MAX_OFFSET 0xD040
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#define TPC6_QM_SECTION 0x3E000
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#define mmTPC7_CFG_BASE 0x7FFCFC6000ull
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#define TPC7_CFG_MAX_OFFSET 0xE400
|
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#define TPC7_CFG_SECTION 0x4000
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|
#define mmKERNEL_TENSOR_0_TPC7_CFG_BASE 0x7FFCFC6400ull
|
|
#define KERNEL_TENSOR_0_TPC7_CFG_MAX_OFFSET 0x3800
|
|
#define KERNEL_TENSOR_0_TPC7_CFG_SECTION 0x3800
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|
#define mmKERNEL_TENSOR_1_TPC7_CFG_BASE 0x7FFCFC6438ull
|
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#define KERNEL_TENSOR_1_TPC7_CFG_MAX_OFFSET 0x3800
|
|
#define KERNEL_TENSOR_1_TPC7_CFG_SECTION 0x3800
|
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#define mmKERNEL_TENSOR_2_TPC7_CFG_BASE 0x7FFCFC6470ull
|
|
#define KERNEL_TENSOR_2_TPC7_CFG_MAX_OFFSET 0x3800
|
|
#define KERNEL_TENSOR_2_TPC7_CFG_SECTION 0x3800
|
|
#define mmKERNEL_TENSOR_3_TPC7_CFG_BASE 0x7FFCFC64A8ull
|
|
#define KERNEL_TENSOR_3_TPC7_CFG_MAX_OFFSET 0x3800
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|
#define KERNEL_TENSOR_3_TPC7_CFG_SECTION 0x3800
|
|
#define mmKERNEL_TENSOR_4_TPC7_CFG_BASE 0x7FFCFC64E0ull
|
|
#define KERNEL_TENSOR_4_TPC7_CFG_MAX_OFFSET 0x3800
|
|
#define KERNEL_TENSOR_4_TPC7_CFG_SECTION 0x3800
|
|
#define mmKERNEL_TENSOR_5_TPC7_CFG_BASE 0x7FFCFC6518ull
|
|
#define KERNEL_TENSOR_5_TPC7_CFG_MAX_OFFSET 0x3800
|
|
#define KERNEL_TENSOR_5_TPC7_CFG_SECTION 0x3800
|
|
#define mmKERNEL_TENSOR_6_TPC7_CFG_BASE 0x7FFCFC6550ull
|
|
#define KERNEL_TENSOR_6_TPC7_CFG_MAX_OFFSET 0x3800
|
|
#define KERNEL_TENSOR_6_TPC7_CFG_SECTION 0x3800
|
|
#define mmKERNEL_TENSOR_7_TPC7_CFG_BASE 0x7FFCFC6588ull
|
|
#define KERNEL_TENSOR_7_TPC7_CFG_MAX_OFFSET 0x3800
|
|
#define KERNEL_TENSOR_7_TPC7_CFG_SECTION 0x3800
|
|
#define mmKERNEL_TENSOR_8_TPC7_CFG_BASE 0x7FFCFC65C0ull
|
|
#define KERNEL_TENSOR_8_TPC7_CFG_MAX_OFFSET 0x3800
|
|
#define KERNEL_TENSOR_8_TPC7_CFG_SECTION 0x3800
|
|
#define mmKERNEL_TENSOR_9_TPC7_CFG_BASE 0x7FFCFC65F8ull
|
|
#define KERNEL_TENSOR_9_TPC7_CFG_MAX_OFFSET 0x3800
|
|
#define KERNEL_TENSOR_9_TPC7_CFG_SECTION 0x3800
|
|
#define mmKERNEL_TENSOR_10_TPC7_CFG_BASE 0x7FFCFC6630ull
|
|
#define KERNEL_TENSOR_10_TPC7_CFG_MAX_OFFSET 0x3800
|
|
#define KERNEL_TENSOR_10_TPC7_CFG_SECTION 0x3800
|
|
#define mmKERNEL_TENSOR_11_TPC7_CFG_BASE 0x7FFCFC6668ull
|
|
#define KERNEL_TENSOR_11_TPC7_CFG_MAX_OFFSET 0x3800
|
|
#define KERNEL_TENSOR_11_TPC7_CFG_SECTION 0x3800
|
|
#define mmKERNEL_TENSOR_12_TPC7_CFG_BASE 0x7FFCFC66A0ull
|
|
#define KERNEL_TENSOR_12_TPC7_CFG_MAX_OFFSET 0x3800
|
|
#define KERNEL_TENSOR_12_TPC7_CFG_SECTION 0x3800
|
|
#define mmKERNEL_TENSOR_13_TPC7_CFG_BASE 0x7FFCFC66D8ull
|
|
#define KERNEL_TENSOR_13_TPC7_CFG_MAX_OFFSET 0x3800
|
|
#define KERNEL_TENSOR_13_TPC7_CFG_SECTION 0x3800
|
|
#define mmKERNEL_TENSOR_14_TPC7_CFG_BASE 0x7FFCFC6710ull
|
|
#define KERNEL_TENSOR_14_TPC7_CFG_MAX_OFFSET 0x3800
|
|
#define KERNEL_TENSOR_14_TPC7_CFG_SECTION 0x3800
|
|
#define mmKERNEL_TENSOR_15_TPC7_CFG_BASE 0x7FFCFC6748ull
|
|
#define KERNEL_TENSOR_15_TPC7_CFG_MAX_OFFSET 0x3800
|
|
#define KERNEL_TENSOR_15_TPC7_CFG_SECTION 0x3800
|
|
#define mmKERNEL_SYNC_OBJECT_TPC7_CFG_BASE 0x7FFCFC6780ull
|
|
#define KERNEL_SYNC_OBJECT_TPC7_CFG_MAX_OFFSET 0x8000
|
|
#define KERNEL_SYNC_OBJECT_TPC7_CFG_SECTION 0x8000
|
|
#define mmKERNEL_TPC7_CFG_BASE 0x7FFCFC6788ull
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|
#define KERNEL_TPC7_CFG_MAX_OFFSET 0xB800
|
|
#define KERNEL_TPC7_CFG_SECTION 0x2780
|
|
#define mmQM_TENSOR_0_TPC7_CFG_BASE 0x7FFCFC6A00ull
|
|
#define QM_TENSOR_0_TPC7_CFG_MAX_OFFSET 0x3800
|
|
#define QM_TENSOR_0_TPC7_CFG_SECTION 0x3800
|
|
#define mmQM_TENSOR_1_TPC7_CFG_BASE 0x7FFCFC6A38ull
|
|
#define QM_TENSOR_1_TPC7_CFG_MAX_OFFSET 0x3800
|
|
#define QM_TENSOR_1_TPC7_CFG_SECTION 0x3800
|
|
#define mmQM_TENSOR_2_TPC7_CFG_BASE 0x7FFCFC6A70ull
|
|
#define QM_TENSOR_2_TPC7_CFG_MAX_OFFSET 0x3800
|
|
#define QM_TENSOR_2_TPC7_CFG_SECTION 0x3800
|
|
#define mmQM_TENSOR_3_TPC7_CFG_BASE 0x7FFCFC6AA8ull
|
|
#define QM_TENSOR_3_TPC7_CFG_MAX_OFFSET 0x3800
|
|
#define QM_TENSOR_3_TPC7_CFG_SECTION 0x3800
|
|
#define mmQM_TENSOR_4_TPC7_CFG_BASE 0x7FFCFC6AE0ull
|
|
#define QM_TENSOR_4_TPC7_CFG_MAX_OFFSET 0x3800
|
|
#define QM_TENSOR_4_TPC7_CFG_SECTION 0x3800
|
|
#define mmQM_TENSOR_5_TPC7_CFG_BASE 0x7FFCFC6B18ull
|
|
#define QM_TENSOR_5_TPC7_CFG_MAX_OFFSET 0x3800
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|
#define QM_TENSOR_5_TPC7_CFG_SECTION 0x3800
|
|
#define mmQM_TENSOR_6_TPC7_CFG_BASE 0x7FFCFC6B50ull
|
|
#define QM_TENSOR_6_TPC7_CFG_MAX_OFFSET 0x3800
|
|
#define QM_TENSOR_6_TPC7_CFG_SECTION 0x3800
|
|
#define mmQM_TENSOR_7_TPC7_CFG_BASE 0x7FFCFC6B88ull
|
|
#define QM_TENSOR_7_TPC7_CFG_MAX_OFFSET 0x3800
|
|
#define QM_TENSOR_7_TPC7_CFG_SECTION 0x3800
|
|
#define mmQM_TENSOR_8_TPC7_CFG_BASE 0x7FFCFC6BC0ull
|
|
#define QM_TENSOR_8_TPC7_CFG_MAX_OFFSET 0x3800
|
|
#define QM_TENSOR_8_TPC7_CFG_SECTION 0x3800
|
|
#define mmQM_TENSOR_9_TPC7_CFG_BASE 0x7FFCFC6BF8ull
|
|
#define QM_TENSOR_9_TPC7_CFG_MAX_OFFSET 0x3800
|
|
#define QM_TENSOR_9_TPC7_CFG_SECTION 0x3800
|
|
#define mmQM_TENSOR_10_TPC7_CFG_BASE 0x7FFCFC6C30ull
|
|
#define QM_TENSOR_10_TPC7_CFG_MAX_OFFSET 0x3800
|
|
#define QM_TENSOR_10_TPC7_CFG_SECTION 0x3800
|
|
#define mmQM_TENSOR_11_TPC7_CFG_BASE 0x7FFCFC6C68ull
|
|
#define QM_TENSOR_11_TPC7_CFG_MAX_OFFSET 0x3800
|
|
#define QM_TENSOR_11_TPC7_CFG_SECTION 0x3800
|
|
#define mmQM_TENSOR_12_TPC7_CFG_BASE 0x7FFCFC6CA0ull
|
|
#define QM_TENSOR_12_TPC7_CFG_MAX_OFFSET 0x3800
|
|
#define QM_TENSOR_12_TPC7_CFG_SECTION 0x3800
|
|
#define mmQM_TENSOR_13_TPC7_CFG_BASE 0x7FFCFC6CD8ull
|
|
#define QM_TENSOR_13_TPC7_CFG_MAX_OFFSET 0x3800
|
|
#define QM_TENSOR_13_TPC7_CFG_SECTION 0x3800
|
|
#define mmQM_TENSOR_14_TPC7_CFG_BASE 0x7FFCFC6D10ull
|
|
#define QM_TENSOR_14_TPC7_CFG_MAX_OFFSET 0x3800
|
|
#define QM_TENSOR_14_TPC7_CFG_SECTION 0x3800
|
|
#define mmQM_TENSOR_15_TPC7_CFG_BASE 0x7FFCFC6D48ull
|
|
#define QM_TENSOR_15_TPC7_CFG_MAX_OFFSET 0x3800
|
|
#define QM_TENSOR_15_TPC7_CFG_SECTION 0x3800
|
|
#define mmQM_SYNC_OBJECT_TPC7_CFG_BASE 0x7FFCFC6D80ull
|
|
#define QM_SYNC_OBJECT_TPC7_CFG_MAX_OFFSET 0x8000
|
|
#define QM_SYNC_OBJECT_TPC7_CFG_SECTION 0x8000
|
|
#define mmQM_TPC7_CFG_BASE 0x7FFCFC6D88ull
|
|
#define QM_TPC7_CFG_MAX_OFFSET 0xB800
|
|
#define QM_TPC7_CFG_SECTION 0x2780
|
|
#define mmTPC7_E2E_CRED_BASE 0x7FFCFC7000ull
|
|
#define TPC7_E2E_CRED_MAX_OFFSET 0x1680
|
|
#define TPC7_E2E_CRED_SECTION 0x1000
|
|
#define mmTPC7_QM_BASE 0x7FFCFC8000ull
|
|
#define TPC7_QM_MAX_OFFSET 0xD040
|
|
#define TPC7_QM_SECTION 0x1038000
|
|
#define mmMME_S_ROM_TABLE_BASE 0x7FFE000000ull
|
|
#define MME_S_ROM_TABLE_MAX_OFFSET 0x1000
|
|
#define MME_S_ROM_TABLE_SECTION 0x21000
|
|
#define mmMME0_ACC_STM_BASE 0x7FFE021000ull
|
|
#define MME0_ACC_STM_MAX_OFFSET 0x1000
|
|
#define MME0_ACC_STM_SECTION 0x1000
|
|
#define mmMME0_ACC_CTI_BASE 0x7FFE022000ull
|
|
#define MME0_ACC_CTI_MAX_OFFSET 0x1000
|
|
#define MME0_ACC_CTI_SECTION 0x1000
|
|
#define mmMME0_ACC_ETF_BASE 0x7FFE023000ull
|
|
#define MME0_ACC_ETF_MAX_OFFSET 0x1000
|
|
#define MME0_ACC_ETF_SECTION 0x1000
|
|
#define mmMME0_ACC_SPMU_BASE 0x7FFE024000ull
|
|
#define MME0_ACC_SPMU_MAX_OFFSET 0x1000
|
|
#define MME0_ACC_SPMU_SECTION 0x1000
|
|
#define mmMME0_ACC_CTI0_BASE 0x7FFE025000ull
|
|
#define MME0_ACC_CTI0_MAX_OFFSET 0x1000
|
|
#define MME0_ACC_CTI0_SECTION 0x1000
|
|
#define mmMME0_ACC_CTI1_BASE 0x7FFE026000ull
|
|
#define MME0_ACC_CTI1_MAX_OFFSET 0x1000
|
|
#define MME0_ACC_CTI1_SECTION 0x1000
|
|
#define mmMME0_ACC_BMON0_BASE 0x7FFE027000ull
|
|
#define MME0_ACC_BMON0_MAX_OFFSET 0x1000
|
|
#define MME0_ACC_BMON0_SECTION 0x9000
|
|
#define mmMME0_ACC_FUNNEL_BASE 0x7FFE030000ull
|
|
#define MME0_ACC_FUNNEL_MAX_OFFSET 0x1000
|
|
#define MME0_ACC_FUNNEL_SECTION 0x11000
|
|
#define mmMME0_SBAB_STM_BASE 0x7FFE041000ull
|
|
#define MME0_SBAB_STM_MAX_OFFSET 0x1000
|
|
#define MME0_SBAB_STM_SECTION 0x1000
|
|
#define mmMME0_SBAB_CTI_BASE 0x7FFE042000ull
|
|
#define MME0_SBAB_CTI_MAX_OFFSET 0x1000
|
|
#define MME0_SBAB_CTI_SECTION 0x1000
|
|
#define mmMME0_SBAB_ETF_BASE 0x7FFE043000ull
|
|
#define MME0_SBAB_ETF_MAX_OFFSET 0x1000
|
|
#define MME0_SBAB_ETF_SECTION 0x1000
|
|
#define mmMME0_SBAB_SPMU_BASE 0x7FFE044000ull
|
|
#define MME0_SBAB_SPMU_MAX_OFFSET 0x1000
|
|
#define MME0_SBAB_SPMU_SECTION 0x1000
|
|
#define mmMME0_SBAB_CTI0_BASE 0x7FFE045000ull
|
|
#define MME0_SBAB_CTI0_MAX_OFFSET 0x1000
|
|
#define MME0_SBAB_CTI0_SECTION 0x1000
|
|
#define mmMME0_SBAB_CTI1_BASE 0x7FFE046000ull
|
|
#define MME0_SBAB_CTI1_MAX_OFFSET 0x1000
|
|
#define MME0_SBAB_CTI1_SECTION 0x1000
|
|
#define mmMME0_SBAB_BMON0_BASE 0x7FFE047000ull
|
|
#define MME0_SBAB_BMON0_MAX_OFFSET 0x1000
|
|
#define MME0_SBAB_BMON0_SECTION 0x1000
|
|
#define mmMME0_SBAB_BMON1_BASE 0x7FFE048000ull
|
|
#define MME0_SBAB_BMON1_MAX_OFFSET 0x1000
|
|
#define MME0_SBAB_BMON1_SECTION 0x19000
|
|
#define mmMME0_CTRL_STM_BASE 0x7FFE061000ull
|
|
#define MME0_CTRL_STM_MAX_OFFSET 0x1000
|
|
#define MME0_CTRL_STM_SECTION 0x1000
|
|
#define mmMME0_CTRL_CTI_BASE 0x7FFE062000ull
|
|
#define MME0_CTRL_CTI_MAX_OFFSET 0x1000
|
|
#define MME0_CTRL_CTI_SECTION 0x1000
|
|
#define mmMME0_CTRL_ETF_BASE 0x7FFE063000ull
|
|
#define MME0_CTRL_ETF_MAX_OFFSET 0x1000
|
|
#define MME0_CTRL_ETF_SECTION 0x1000
|
|
#define mmMME0_CTRL_SPMU_BASE 0x7FFE064000ull
|
|
#define MME0_CTRL_SPMU_MAX_OFFSET 0x1000
|
|
#define MME0_CTRL_SPMU_SECTION 0x1000
|
|
#define mmMME0_CTRL_CTI0_BASE 0x7FFE065000ull
|
|
#define MME0_CTRL_CTI0_MAX_OFFSET 0x1000
|
|
#define MME0_CTRL_CTI0_SECTION 0x1000
|
|
#define mmMME0_CTRL_CTI1_BASE 0x7FFE066000ull
|
|
#define MME0_CTRL_CTI1_MAX_OFFSET 0x1000
|
|
#define MME0_CTRL_CTI1_SECTION 0x1000
|
|
#define mmMME0_CTRL_BMON0_BASE 0x7FFE067000ull
|
|
#define MME0_CTRL_BMON0_MAX_OFFSET 0x1000
|
|
#define MME0_CTRL_BMON0_SECTION 0x1000
|
|
#define mmMME0_CTRL_BMON1_BASE 0x7FFE068000ull
|
|
#define MME0_CTRL_BMON1_MAX_OFFSET 0x1000
|
|
#define MME0_CTRL_BMON1_SECTION 0x39000
|
|
#define mmMME1_ACC_STM_BASE 0x7FFE0A1000ull
|
|
#define MME1_ACC_STM_MAX_OFFSET 0x1000
|
|
#define MME1_ACC_STM_SECTION 0x1000
|
|
#define mmMME1_ACC_CTI_BASE 0x7FFE0A2000ull
|
|
#define MME1_ACC_CTI_MAX_OFFSET 0x1000
|
|
#define MME1_ACC_CTI_SECTION 0x1000
|
|
#define mmMME1_ACC_ETF_BASE 0x7FFE0A3000ull
|
|
#define MME1_ACC_ETF_MAX_OFFSET 0x1000
|
|
#define MME1_ACC_ETF_SECTION 0x1000
|
|
#define mmMME1_ACC_SPMU_BASE 0x7FFE0A4000ull
|
|
#define MME1_ACC_SPMU_MAX_OFFSET 0x1000
|
|
#define MME1_ACC_SPMU_SECTION 0x1000
|
|
#define mmMME1_ACC_CTI0_BASE 0x7FFE0A5000ull
|
|
#define MME1_ACC_CTI0_MAX_OFFSET 0x1000
|
|
#define MME1_ACC_CTI0_SECTION 0x1000
|
|
#define mmMME1_ACC_CTI1_BASE 0x7FFE0A6000ull
|
|
#define MME1_ACC_CTI1_MAX_OFFSET 0x1000
|
|
#define MME1_ACC_CTI1_SECTION 0x1000
|
|
#define mmMME1_ACC_BMON0_BASE 0x7FFE0A7000ull
|
|
#define MME1_ACC_BMON0_MAX_OFFSET 0x1000
|
|
#define MME1_ACC_BMON0_SECTION 0x9000
|
|
#define mmMME1_ACC_FUNNEL_BASE 0x7FFE0B0000ull
|
|
#define MME1_ACC_FUNNEL_MAX_OFFSET 0x1000
|
|
#define MME1_ACC_FUNNEL_SECTION 0x11000
|
|
#define mmMME1_SBAB_STM_BASE 0x7FFE0C1000ull
|
|
#define MME1_SBAB_STM_MAX_OFFSET 0x1000
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#define MME1_SBAB_STM_SECTION 0x1000
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#define mmMME1_SBAB_CTI_BASE 0x7FFE0C2000ull
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#define MME1_SBAB_CTI_MAX_OFFSET 0x1000
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#define MME1_SBAB_CTI_SECTION 0x1000
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#define mmMME1_SBAB_ETF_BASE 0x7FFE0C3000ull
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#define MME1_SBAB_ETF_MAX_OFFSET 0x1000
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#define MME1_SBAB_ETF_SECTION 0x1000
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#define mmMME1_SBAB_SPMU_BASE 0x7FFE0C4000ull
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#define MME1_SBAB_SPMU_MAX_OFFSET 0x1000
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#define MME1_SBAB_SPMU_SECTION 0x1000
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#define mmMME1_SBAB_CTI0_BASE 0x7FFE0C5000ull
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#define MME1_SBAB_CTI0_MAX_OFFSET 0x1000
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#define MME1_SBAB_CTI0_SECTION 0x1000
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#define mmMME1_SBAB_CTI1_BASE 0x7FFE0C6000ull
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#define MME1_SBAB_CTI1_MAX_OFFSET 0x1000
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#define MME1_SBAB_CTI1_SECTION 0x1000
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#define mmMME1_SBAB_BMON0_BASE 0x7FFE0C7000ull
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#define MME1_SBAB_BMON0_MAX_OFFSET 0x1000
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#define MME1_SBAB_BMON0_SECTION 0x1000
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#define mmMME1_SBAB_BMON1_BASE 0x7FFE0C8000ull
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#define MME1_SBAB_BMON1_MAX_OFFSET 0x1000
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#define MME1_SBAB_BMON1_SECTION 0x19000
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#define mmMME1_CTRL_STM_BASE 0x7FFE0E1000ull
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#define MME1_CTRL_STM_MAX_OFFSET 0x1000
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#define MME1_CTRL_STM_SECTION 0x1000
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#define mmMME1_CTRL_CTI_BASE 0x7FFE0E2000ull
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#define MME1_CTRL_CTI_MAX_OFFSET 0x1000
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#define MME1_CTRL_CTI_SECTION 0x1000
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#define mmMME1_CTRL_ETF_BASE 0x7FFE0E3000ull
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#define MME1_CTRL_ETF_MAX_OFFSET 0x1000
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#define MME1_CTRL_ETF_SECTION 0x1000
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#define mmMME1_CTRL_SPMU_BASE 0x7FFE0E4000ull
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#define MME1_CTRL_SPMU_MAX_OFFSET 0x1000
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#define MME1_CTRL_SPMU_SECTION 0x1000
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#define mmMME1_CTRL_CTI0_BASE 0x7FFE0E5000ull
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#define MME1_CTRL_CTI0_MAX_OFFSET 0x1000
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#define MME1_CTRL_CTI0_SECTION 0x1000
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#define mmMME1_CTRL_CTI1_BASE 0x7FFE0E6000ull
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#define MME1_CTRL_CTI1_MAX_OFFSET 0x1000
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#define MME1_CTRL_CTI1_SECTION 0x1000
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#define mmMME1_CTRL_BMON0_BASE 0x7FFE0E7000ull
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#define MME1_CTRL_BMON0_MAX_OFFSET 0x1000
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#define MME1_CTRL_BMON0_SECTION 0x1000
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#define mmMME1_CTRL_BMON1_BASE 0x7FFE0E8000ull
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#define MME1_CTRL_BMON1_MAX_OFFSET 0x1000
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#define MME1_CTRL_BMON1_SECTION 0x18000
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#define mmMME_N_ROM_TABLE_BASE 0x7FFE100000ull
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#define MME_N_ROM_TABLE_MAX_OFFSET 0x1000
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#define MME_N_ROM_TABLE_SECTION 0x21000
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#define mmMME2_ACC_STM_BASE 0x7FFE121000ull
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#define MME2_ACC_STM_MAX_OFFSET 0x1000
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#define MME2_ACC_STM_SECTION 0x1000
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#define mmMME2_ACC_CTI_BASE 0x7FFE122000ull
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#define MME2_ACC_CTI_MAX_OFFSET 0x1000
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#define MME2_ACC_CTI_SECTION 0x1000
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#define mmMME2_MME2_ACC_ETF_BASE 0x7FFE123000ull
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#define MME2_MME2_ACC_ETF_MAX_OFFSET 0x1000
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#define MME2_MME2_ACC_ETF_SECTION 0x1000
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#define mmMME2_ACC_SPMU_BASE 0x7FFE124000ull
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#define MME2_ACC_SPMU_MAX_OFFSET 0x1000
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#define MME2_ACC_SPMU_SECTION 0x1000
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#define mmMME2_ACC_CTI0_BASE 0x7FFE125000ull
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#define MME2_ACC_CTI0_MAX_OFFSET 0x1000
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#define MME2_ACC_CTI0_SECTION 0x1000
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#define mmMME2_ACC_CTI1_BASE 0x7FFE126000ull
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#define MME2_ACC_CTI1_MAX_OFFSET 0x1000
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#define MME2_ACC_CTI1_SECTION 0x1000
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#define mmMME2_ACC_BMON0_BASE 0x7FFE127000ull
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#define MME2_ACC_BMON0_MAX_OFFSET 0x1000
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#define MME2_ACC_BMON0_SECTION 0x9000
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#define mmMME2_ACC_FUNNEL_BASE 0x7FFE130000ull
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#define MME2_ACC_FUNNEL_MAX_OFFSET 0x1000
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#define MME2_ACC_FUNNEL_SECTION 0x11000
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#define mmMME2_SBAB_STM_BASE 0x7FFE141000ull
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#define MME2_SBAB_STM_MAX_OFFSET 0x1000
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#define MME2_SBAB_STM_SECTION 0x1000
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#define mmMME2_SBAB_CTI_BASE 0x7FFE142000ull
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#define MME2_SBAB_CTI_MAX_OFFSET 0x1000
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#define MME2_SBAB_CTI_SECTION 0x1000
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#define mmMME2_SBAB_ETF_BASE 0x7FFE143000ull
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#define MME2_SBAB_ETF_MAX_OFFSET 0x1000
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#define MME2_SBAB_ETF_SECTION 0x1000
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#define mmMME2_SBAB_SPMU_BASE 0x7FFE144000ull
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#define MME2_SBAB_SPMU_MAX_OFFSET 0x1000
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#define MME2_SBAB_SPMU_SECTION 0x1000
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#define mmMME2_SBAB_CTI0_BASE 0x7FFE145000ull
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#define MME2_SBAB_CTI0_MAX_OFFSET 0x1000
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#define MME2_SBAB_CTI0_SECTION 0x1000
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#define mmMME2_SBAB_CTI1_BASE 0x7FFE146000ull
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#define MME2_SBAB_CTI1_MAX_OFFSET 0x1000
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#define MME2_SBAB_CTI1_SECTION 0x1000
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#define mmMME2_SBAB_BMON0_BASE 0x7FFE147000ull
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#define MME2_SBAB_BMON0_MAX_OFFSET 0x1000
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#define MME2_SBAB_BMON0_SECTION 0x1000
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#define mmMME2_SBAB_BMON1_BASE 0x7FFE148000ull
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#define MME2_SBAB_BMON1_MAX_OFFSET 0x1000
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#define MME2_SBAB_BMON1_SECTION 0x19000
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#define mmMME2_CTRL_STM_BASE 0x7FFE161000ull
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#define MME2_CTRL_STM_MAX_OFFSET 0x1000
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#define MME2_CTRL_STM_SECTION 0x1000
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#define mmMME2_CTRL_CTI_BASE 0x7FFE162000ull
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#define MME2_CTRL_CTI_MAX_OFFSET 0x1000
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#define MME2_CTRL_CTI_SECTION 0x1000
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#define mmMME2_CTRL_ETF_BASE 0x7FFE163000ull
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#define MME2_CTRL_ETF_MAX_OFFSET 0x1000
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#define MME2_CTRL_ETF_SECTION 0x1000
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#define mmMME2_CTRL_SPMU_BASE 0x7FFE164000ull
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#define MME2_CTRL_SPMU_MAX_OFFSET 0x1000
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#define MME2_CTRL_SPMU_SECTION 0x1000
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#define mmMME2_CTRL_CTI0_BASE 0x7FFE165000ull
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#define MME2_CTRL_CTI0_MAX_OFFSET 0x1000
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#define MME2_CTRL_CTI0_SECTION 0x1000
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#define mmMME2_CTRL_CTI1_BASE 0x7FFE166000ull
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#define MME2_CTRL_CTI1_MAX_OFFSET 0x1000
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#define MME2_CTRL_CTI1_SECTION 0x1000
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#define mmMME2_CTRL_BMON0_BASE 0x7FFE167000ull
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#define MME2_CTRL_BMON0_MAX_OFFSET 0x1000
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#define MME2_CTRL_BMON0_SECTION 0x1000
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#define mmMME2_CTRL_BMON1_BASE 0x7FFE168000ull
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#define MME2_CTRL_BMON1_MAX_OFFSET 0x1000
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#define MME2_CTRL_BMON1_SECTION 0x39000
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#define mmMME3_ACC_STM_BASE 0x7FFE1A1000ull
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#define MME3_ACC_STM_MAX_OFFSET 0x1000
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#define MME3_ACC_STM_SECTION 0x1000
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#define mmMME3_ACC_CTI_BASE 0x7FFE1A2000ull
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#define MME3_ACC_CTI_MAX_OFFSET 0x1000
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#define MME3_ACC_CTI_SECTION 0x1000
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|
#define mmMME3_ACC_ETF_BASE 0x7FFE1A3000ull
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#define MME3_ACC_ETF_MAX_OFFSET 0x1000
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#define MME3_ACC_ETF_SECTION 0x1000
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|
#define mmMME3_ACC_SPMU_BASE 0x7FFE1A4000ull
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#define MME3_ACC_SPMU_MAX_OFFSET 0x1000
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#define MME3_ACC_SPMU_SECTION 0x1000
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#define mmMME3_ACC_CTI0_BASE 0x7FFE1A5000ull
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#define MME3_ACC_CTI0_MAX_OFFSET 0x1000
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#define MME3_ACC_CTI0_SECTION 0x1000
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|
#define mmMME3_ACC_CTI1_BASE 0x7FFE1A6000ull
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#define MME3_ACC_CTI1_MAX_OFFSET 0x1000
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#define MME3_ACC_CTI1_SECTION 0x1000
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#define mmMME3_ACC_BMON0_BASE 0x7FFE1A7000ull
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#define MME3_ACC_BMON0_MAX_OFFSET 0x1000
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#define MME3_ACC_BMON0_SECTION 0x9000
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#define mmMME3_ACC_FUNNEL_BASE 0x7FFE1B0000ull
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#define MME3_ACC_FUNNEL_MAX_OFFSET 0x1000
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#define MME3_ACC_FUNNEL_SECTION 0x11000
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#define mmMME3_SBAB_STM_BASE 0x7FFE1C1000ull
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#define MME3_SBAB_STM_MAX_OFFSET 0x1000
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#define MME3_SBAB_STM_SECTION 0x1000
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|
#define mmMME3_SBAB_CTI_BASE 0x7FFE1C2000ull
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#define MME3_SBAB_CTI_MAX_OFFSET 0x1000
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|
#define MME3_SBAB_CTI_SECTION 0x1000
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|
#define mmMME3_SBAB_ETF_BASE 0x7FFE1C3000ull
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#define MME3_SBAB_ETF_MAX_OFFSET 0x1000
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#define MME3_SBAB_ETF_SECTION 0x1000
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|
#define mmMME3_SBAB_SPMU_BASE 0x7FFE1C4000ull
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#define MME3_SBAB_SPMU_MAX_OFFSET 0x1000
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#define MME3_SBAB_SPMU_SECTION 0x1000
|
|
#define mmMME3_SBAB_CTI0_BASE 0x7FFE1C5000ull
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#define MME3_SBAB_CTI0_MAX_OFFSET 0x1000
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|
#define MME3_SBAB_CTI0_SECTION 0x1000
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|
#define mmMME3_SBAB_CTI1_BASE 0x7FFE1C6000ull
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|
#define MME3_SBAB_CTI1_MAX_OFFSET 0x1000
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|
#define MME3_SBAB_CTI1_SECTION 0x1000
|
|
#define mmMME3_SBAB_BMON0_BASE 0x7FFE1C7000ull
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|
#define MME3_SBAB_BMON0_MAX_OFFSET 0x1000
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|
#define MME3_SBAB_BMON0_SECTION 0x1000
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|
#define mmMME3_SBAB_BMON1_BASE 0x7FFE1C8000ull
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|
#define MME3_SBAB_BMON1_MAX_OFFSET 0x1000
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|
#define MME3_SBAB_BMON1_SECTION 0x19000
|
|
#define mmMME3_CTRL_STM_BASE 0x7FFE1E1000ull
|
|
#define MME3_CTRL_STM_MAX_OFFSET 0x1000
|
|
#define MME3_CTRL_STM_SECTION 0x1000
|
|
#define mmMME3_CTRL_CTI_BASE 0x7FFE1E2000ull
|
|
#define MME3_CTRL_CTI_MAX_OFFSET 0x1000
|
|
#define MME3_CTRL_CTI_SECTION 0x1000
|
|
#define mmMME3_CTRL_ETF_BASE 0x7FFE1E3000ull
|
|
#define MME3_CTRL_ETF_MAX_OFFSET 0x1000
|
|
#define MME3_CTRL_ETF_SECTION 0x1000
|
|
#define mmMME3_CTRL_SPMU_BASE 0x7FFE1E4000ull
|
|
#define MME3_CTRL_SPMU_MAX_OFFSET 0x1000
|
|
#define MME3_CTRL_SPMU_SECTION 0x1000
|
|
#define mmMME3_CTRL_CTI0_BASE 0x7FFE1E5000ull
|
|
#define MME3_CTRL_CTI0_MAX_OFFSET 0x1000
|
|
#define MME3_CTRL_CTI0_SECTION 0x1000
|
|
#define mmMME3_CTRL_CTI1_BASE 0x7FFE1E6000ull
|
|
#define MME3_CTRL_CTI1_MAX_OFFSET 0x1000
|
|
#define MME3_CTRL_CTI1_SECTION 0x1000
|
|
#define mmMME3_CTRL_BMON0_BASE 0x7FFE1E7000ull
|
|
#define MME3_CTRL_BMON0_MAX_OFFSET 0x1000
|
|
#define MME3_CTRL_BMON0_SECTION 0x1000
|
|
#define mmMME3_CTRL_BMON1_BASE 0x7FFE1E8000ull
|
|
#define MME3_CTRL_BMON1_MAX_OFFSET 0x1000
|
|
#define MME3_CTRL_BMON1_SECTION 0x18000
|
|
#define mmIC_ROM_TABLE_BASE 0x7FFE200000ull
|
|
#define IC_ROM_TABLE_MAX_OFFSET 0x1000
|
|
#define IC_ROM_TABLE_SECTION 0x1000
|
|
#define mmSRAM_Y0_X0_FUNNEL_BASE 0x7FFE201000ull
|
|
#define SRAM_Y0_X0_FUNNEL_MAX_OFFSET 0x1000
|
|
#define SRAM_Y0_X0_FUNNEL_SECTION 0x8000
|
|
#define mmSRAM_Y0_X1_FUNNEL_BASE 0x7FFE209000ull
|
|
#define SRAM_Y0_X1_FUNNEL_MAX_OFFSET 0x1000
|
|
#define SRAM_Y0_X1_FUNNEL_SECTION 0x8000
|
|
#define mmSRAM_Y0_X2_FUNNEL_BASE 0x7FFE211000ull
|
|
#define SRAM_Y0_X2_FUNNEL_MAX_OFFSET 0x1000
|
|
#define SRAM_Y0_X2_FUNNEL_SECTION 0x8000
|
|
#define mmSRAM_Y0_X3_FUNNEL_BASE 0x7FFE219000ull
|
|
#define SRAM_Y0_X3_FUNNEL_MAX_OFFSET 0x1000
|
|
#define SRAM_Y0_X3_FUNNEL_SECTION 0x8000
|
|
#define mmSRAM_Y0_X4_FUNNEL_BASE 0x7FFE221000ull
|
|
#define SRAM_Y0_X4_FUNNEL_MAX_OFFSET 0x1000
|
|
#define SRAM_Y0_X4_FUNNEL_SECTION 0x8000
|
|
#define mmSRAM_Y0_X5_FUNNEL_BASE 0x7FFE229000ull
|
|
#define SRAM_Y0_X5_FUNNEL_MAX_OFFSET 0x1000
|
|
#define SRAM_Y0_X5_FUNNEL_SECTION 0x8000
|
|
#define mmSRAM_Y0_X6_FUNNEL_BASE 0x7FFE231000ull
|
|
#define SRAM_Y0_X6_FUNNEL_MAX_OFFSET 0x1000
|
|
#define SRAM_Y0_X6_FUNNEL_SECTION 0x8000
|
|
#define mmSRAM_Y0_X7_FUNNEL_BASE 0x7FFE239000ull
|
|
#define SRAM_Y0_X7_FUNNEL_MAX_OFFSET 0x1000
|
|
#define SRAM_Y0_X7_FUNNEL_SECTION 0x8000
|
|
#define mmSRAM_Y1_X0_FUNNEL_BASE 0x7FFE241000ull
|
|
#define SRAM_Y1_X0_FUNNEL_MAX_OFFSET 0x1000
|
|
#define SRAM_Y1_X0_FUNNEL_SECTION 0x8000
|
|
#define mmSRAM_Y1_X1_FUNNEL_BASE 0x7FFE249000ull
|
|
#define SRAM_Y1_X1_FUNNEL_MAX_OFFSET 0x1000
|
|
#define SRAM_Y1_X1_FUNNEL_SECTION 0x8000
|
|
#define mmSRAM_Y1_X2_FUNNEL_BASE 0x7FFE251000ull
|
|
#define SRAM_Y1_X2_FUNNEL_MAX_OFFSET 0x1000
|
|
#define SRAM_Y1_X2_FUNNEL_SECTION 0x8000
|
|
#define mmSRAM_Y1_X3_FUNNEL_BASE 0x7FFE259000ull
|
|
#define SRAM_Y1_X3_FUNNEL_MAX_OFFSET 0x1000
|
|
#define SRAM_Y1_X3_FUNNEL_SECTION 0x8000
|
|
#define mmSRAM_Y1_X4_FUNNEL_BASE 0x7FFE261000ull
|
|
#define SRAM_Y1_X4_FUNNEL_MAX_OFFSET 0x1000
|
|
#define SRAM_Y1_X4_FUNNEL_SECTION 0x8000
|
|
#define mmSRAM_Y1_X5_FUNNEL_BASE 0x7FFE269000ull
|
|
#define SRAM_Y1_X5_FUNNEL_MAX_OFFSET 0x1000
|
|
#define SRAM_Y1_X5_FUNNEL_SECTION 0x8000
|
|
#define mmSRAM_Y1_X6_FUNNEL_BASE 0x7FFE271000ull
|
|
#define SRAM_Y1_X6_FUNNEL_MAX_OFFSET 0x1000
|
|
#define SRAM_Y1_X6_FUNNEL_SECTION 0x8000
|
|
#define mmSRAM_Y1_X7_FUNNEL_BASE 0x7FFE279000ull
|
|
#define SRAM_Y1_X7_FUNNEL_MAX_OFFSET 0x1000
|
|
#define SRAM_Y1_X7_FUNNEL_SECTION 0x8000
|
|
#define mmSRAM_Y2_X0_FUNNEL_BASE 0x7FFE281000ull
|
|
#define SRAM_Y2_X0_FUNNEL_MAX_OFFSET 0x1000
|
|
#define SRAM_Y2_X0_FUNNEL_SECTION 0x8000
|
|
#define mmSRAM_Y2_X1_FUNNEL_BASE 0x7FFE289000ull
|
|
#define SRAM_Y2_X1_FUNNEL_MAX_OFFSET 0x1000
|
|
#define SRAM_Y2_X1_FUNNEL_SECTION 0x8000
|
|
#define mmSRAM_Y2_X2_FUNNEL_BASE 0x7FFE291000ull
|
|
#define SRAM_Y2_X2_FUNNEL_MAX_OFFSET 0x1000
|
|
#define SRAM_Y2_X2_FUNNEL_SECTION 0x8000
|
|
#define mmSRAM_Y2_X3_FUNNEL_BASE 0x7FFE299000ull
|
|
#define SRAM_Y2_X3_FUNNEL_MAX_OFFSET 0x1000
|
|
#define SRAM_Y2_X3_FUNNEL_SECTION 0x8000
|
|
#define mmSRAM_Y2_X4_FUNNEL_BASE 0x7FFE2A1000ull
|
|
#define SRAM_Y2_X4_FUNNEL_MAX_OFFSET 0x1000
|
|
#define SRAM_Y2_X4_FUNNEL_SECTION 0x8000
|
|
#define mmSRAM_Y2_X5_FUNNEL_BASE 0x7FFE2A9000ull
|
|
#define SRAM_Y2_X5_FUNNEL_MAX_OFFSET 0x1000
|
|
#define SRAM_Y2_X5_FUNNEL_SECTION 0x8000
|
|
#define mmSRAM_Y2_X6_FUNNEL_BASE 0x7FFE2B1000ull
|
|
#define SRAM_Y2_X6_FUNNEL_MAX_OFFSET 0x1000
|
|
#define SRAM_Y2_X6_FUNNEL_SECTION 0x8000
|
|
#define mmSRAM_Y2_X7_FUNNEL_BASE 0x7FFE2B9000ull
|
|
#define SRAM_Y2_X7_FUNNEL_MAX_OFFSET 0x1000
|
|
#define SRAM_Y2_X7_FUNNEL_SECTION 0x8000
|
|
#define mmSRAM_Y3_X0_FUNNEL_BASE 0x7FFE2C1000ull
|
|
#define SRAM_Y3_X0_FUNNEL_MAX_OFFSET 0x1000
|
|
#define SRAM_Y3_X0_FUNNEL_SECTION 0x8000
|
|
#define mmSRAM_Y3_X1_FUNNEL_BASE 0x7FFE2C9000ull
|
|
#define SRAM_Y3_X1_FUNNEL_MAX_OFFSET 0x1000
|
|
#define SRAM_Y3_X1_FUNNEL_SECTION 0x8000
|
|
#define mmSRAM_Y3_X2_FUNNEL_BASE 0x7FFE2D1000ull
|
|
#define SRAM_Y3_X2_FUNNEL_MAX_OFFSET 0x1000
|
|
#define SRAM_Y3_X2_FUNNEL_SECTION 0x8000
|
|
#define mmSRAM_Y3_X4_FUNNEL_BASE 0x7FFE2D9000ull
|
|
#define SRAM_Y3_X4_FUNNEL_MAX_OFFSET 0x1000
|
|
#define SRAM_Y3_X4_FUNNEL_SECTION 0x8000
|
|
#define mmSRAM_Y3_X3_FUNNEL_BASE 0x7FFE2E1000ull
|
|
#define SRAM_Y3_X3_FUNNEL_MAX_OFFSET 0x1000
|
|
#define SRAM_Y3_X3_FUNNEL_SECTION 0x8000
|
|
#define mmSRAM_Y3_X5_FUNNEL_BASE 0x7FFE2E9000ull
|
|
#define SRAM_Y3_X5_FUNNEL_MAX_OFFSET 0x1000
|
|
#define SRAM_Y3_X5_FUNNEL_SECTION 0x8000
|
|
#define mmSRAM_Y3_X6_FUNNEL_BASE 0x7FFE2F1000ull
|
|
#define SRAM_Y3_X6_FUNNEL_MAX_OFFSET 0x1000
|
|
#define SRAM_Y3_X6_FUNNEL_SECTION 0x8000
|
|
#define mmSRAM_Y3_X7_FUNNEL_BASE 0x7FFE2F9000ull
|
|
#define SRAM_Y3_X7_FUNNEL_MAX_OFFSET 0x1000
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#define SRAM_Y3_X7_FUNNEL_SECTION 0x7000
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#define mmIF_ROM_TABLE_BASE 0x7FFE300000ull
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#define IF_ROM_TABLE_MAX_OFFSET 0x1000
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#define IF_ROM_TABLE_SECTION 0x1000
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#define mmSIF_FUNNEL_0_BASE 0x7FFE301000ull
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#define SIF_FUNNEL_0_MAX_OFFSET 0x1000
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#define SIF_FUNNEL_0_SECTION 0x10000
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#define mmSIF_FUNNEL_1_BASE 0x7FFE311000ull
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#define SIF_FUNNEL_1_MAX_OFFSET 0x1000
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#define SIF_FUNNEL_1_SECTION 0x10000
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#define mmSIF_FUNNEL_2_BASE 0x7FFE321000ull
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#define SIF_FUNNEL_2_MAX_OFFSET 0x1000
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#define SIF_FUNNEL_2_SECTION 0x10000
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#define mmSIF_FUNNEL_3_BASE 0x7FFE331000ull
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#define SIF_FUNNEL_3_MAX_OFFSET 0x1000
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#define SIF_FUNNEL_3_SECTION 0x10000
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#define mmSIF_FUNNEL_4_BASE 0x7FFE341000ull
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#define SIF_FUNNEL_4_MAX_OFFSET 0x1000
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#define SIF_FUNNEL_4_SECTION 0x10000
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#define mmSIF_FUNNEL_5_BASE 0x7FFE351000ull
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#define SIF_FUNNEL_5_MAX_OFFSET 0x1000
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#define SIF_FUNNEL_5_SECTION 0x10000
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#define mmSIF_FUNNEL_6_BASE 0x7FFE361000ull
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#define SIF_FUNNEL_6_MAX_OFFSET 0x1000
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#define SIF_FUNNEL_6_SECTION 0x10000
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#define mmSIF_FUNNEL_7_BASE 0x7FFE371000ull
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#define SIF_FUNNEL_7_MAX_OFFSET 0x1000
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#define SIF_FUNNEL_7_SECTION 0x10000
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#define mmNIF_FUNNEL_0_BASE 0x7FFE381000ull
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#define NIF_FUNNEL_0_MAX_OFFSET 0x1000
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#define NIF_FUNNEL_0_SECTION 0x10000
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#define mmNIF_FUNNEL_1_BASE 0x7FFE391000ull
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#define NIF_FUNNEL_1_MAX_OFFSET 0x1000
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#define NIF_FUNNEL_1_SECTION 0x10000
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#define mmNIF_FUNNEL_2_BASE 0x7FFE3A1000ull
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#define NIF_FUNNEL_2_MAX_OFFSET 0x1000
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#define NIF_FUNNEL_2_SECTION 0x10000
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#define mmNIF_FUNNEL_3_BASE 0x7FFE3B1000ull
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#define NIF_FUNNEL_3_MAX_OFFSET 0x1000
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#define NIF_FUNNEL_3_SECTION 0x10000
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#define mmNIF_FUNNEL_4_BASE 0x7FFE3C1000ull
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#define NIF_FUNNEL_4_MAX_OFFSET 0x1000
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#define NIF_FUNNEL_4_SECTION 0x10000
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#define mmNIF_FUNNEL_5_BASE 0x7FFE3D1000ull
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#define NIF_FUNNEL_5_MAX_OFFSET 0x1000
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#define NIF_FUNNEL_5_SECTION 0x10000
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#define mmNIF_FUNNEL_6_BASE 0x7FFE3E1000ull
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#define NIF_FUNNEL_6_MAX_OFFSET 0x1000
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#define NIF_FUNNEL_6_SECTION 0x10000
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#define mmNIF_FUNNEL_7_BASE 0x7FFE3F1000ull
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#define NIF_FUNNEL_7_MAX_OFFSET 0x1000
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#define NIF_FUNNEL_7_SECTION 0xF000
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#define mmDMA_IF_ROM_TABLE_BASE 0x7FFE400000ull
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#define DMA_IF_ROM_TABLE_MAX_OFFSET 0x1000
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#define DMA_IF_ROM_TABLE_SECTION 0x1000
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|
#define mmDMA_IF_W_S_STM_BASE 0x7FFE401000ull
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#define DMA_IF_W_S_STM_MAX_OFFSET 0x1000
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#define DMA_IF_W_S_STM_SECTION 0x1000
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#define mmDMA_IF_W_S_CTI_BASE 0x7FFE402000ull
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#define DMA_IF_W_S_CTI_MAX_OFFSET 0x1000
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#define DMA_IF_W_S_CTI_SECTION 0x1000
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|
#define mmDMA_IF_W_S_ETF_BASE 0x7FFE403000ull
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#define DMA_IF_W_S_ETF_MAX_OFFSET 0x1000
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#define DMA_IF_W_S_ETF_SECTION 0x2000
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|
#define mmDMA_IF_W_S_BMON0_CTI_BASE 0x7FFE405000ull
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#define DMA_IF_W_S_BMON0_CTI_MAX_OFFSET 0x1000
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|
#define DMA_IF_W_S_BMON0_CTI_SECTION 0x1000
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|
#define mmDMA_IF_W_S_BMON1_CTI_BASE 0x7FFE406000ull
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#define DMA_IF_W_S_BMON1_CTI_MAX_OFFSET 0x1000
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#define DMA_IF_W_S_BMON1_CTI_SECTION 0x1000
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#define mmDMA_IF_W_S_HBM0_WR_BMON_BASE 0x7FFE407000ull
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#define DMA_IF_W_S_HBM0_WR_BMON_MAX_OFFSET 0x1000
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#define DMA_IF_W_S_HBM0_WR_BMON_SECTION 0x1000
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#define mmDMA_IF_W_S_HBM0_RD_BMON_BASE 0x7FFE408000ull
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#define DMA_IF_W_S_HBM0_RD_BMON_MAX_OFFSET 0x1000
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#define DMA_IF_W_S_HBM0_RD_BMON_SECTION 0x1000
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|
#define mmDMA_IF_W_S_HBM1_WR_BMON_BASE 0x7FFE409000ull
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#define DMA_IF_W_S_HBM1_WR_BMON_MAX_OFFSET 0x1000
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|
#define DMA_IF_W_S_HBM1_WR_BMON_SECTION 0x1000
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|
#define mmDMA_IF_W_S_HBM1_RD_BMON_BASE 0x7FFE40A000ull
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#define DMA_IF_W_S_HBM1_RD_BMON_MAX_OFFSET 0x1000
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|
#define DMA_IF_W_S_HBM1_RD_BMON_SECTION 0x1000
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|
#define mmDMA_IF_W_S_SOB_WR_BMON_BASE 0x7FFE40B000ull
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#define DMA_IF_W_S_SOB_WR_BMON_MAX_OFFSET 0x1000
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|
#define DMA_IF_W_S_SOB_WR_BMON_SECTION 0x4000
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|
#define mmDMA_IF_W_S_FUNNEL_BASE 0x7FFE40F000ull
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|
#define DMA_IF_W_S_FUNNEL_MAX_OFFSET 0x1000
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|
#define DMA_IF_W_S_FUNNEL_SECTION 0x12000
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|
#define mmDMA_IF_E_S_STM_BASE 0x7FFE421000ull
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|
#define DMA_IF_E_S_STM_MAX_OFFSET 0x1000
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|
#define DMA_IF_E_S_STM_SECTION 0x1000
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|
#define mmDMA_IF_E_S_CTI_BASE 0x7FFE422000ull
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|
#define DMA_IF_E_S_CTI_MAX_OFFSET 0x1000
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|
#define DMA_IF_E_S_CTI_SECTION 0x1000
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|
#define mmDMA_IF_E_S_ETF_BASE 0x7FFE423000ull
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|
#define DMA_IF_E_S_ETF_MAX_OFFSET 0x1000
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|
#define DMA_IF_E_S_ETF_SECTION 0x2000
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|
#define mmDMA_IF_E_S_BMON0_CTI_BASE 0x7FFE425000ull
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#define DMA_IF_E_S_BMON0_CTI_MAX_OFFSET 0x1000
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#define DMA_IF_E_S_BMON0_CTI_SECTION 0x1000
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|
#define mmDMA_IF_E_S_BMON1_CTI_BASE 0x7FFE426000ull
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|
#define DMA_IF_E_S_BMON1_CTI_MAX_OFFSET 0x1000
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|
#define DMA_IF_E_S_BMON1_CTI_SECTION 0x1000
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|
#define mmDMA_IF_E_S_HBM0_WR_BMON_BASE 0x7FFE427000ull
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|
#define DMA_IF_E_S_HBM0_WR_BMON_MAX_OFFSET 0x1000
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|
#define DMA_IF_E_S_HBM0_WR_BMON_SECTION 0x1000
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|
#define mmDMA_IF_E_S_HBM0_RD_BMON_BASE 0x7FFE428000ull
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|
#define DMA_IF_E_S_HBM0_RD_BMON_MAX_OFFSET 0x1000
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|
#define DMA_IF_E_S_HBM0_RD_BMON_SECTION 0x1000
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|
#define mmDMA_IF_E_S_HBM1_WR_BMON_BASE 0x7FFE429000ull
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|
#define DMA_IF_E_S_HBM1_WR_BMON_MAX_OFFSET 0x1000
|
|
#define DMA_IF_E_S_HBM1_WR_BMON_SECTION 0x1000
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|
#define mmDMA_IF_E_S_HBM1_RD_BMON_BASE 0x7FFE42A000ull
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|
#define DMA_IF_E_S_HBM1_RD_BMON_MAX_OFFSET 0x1000
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|
#define DMA_IF_E_S_HBM1_RD_BMON_SECTION 0x1000
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|
#define mmDMA_IF_E_S_SOB_WR_BMON_BASE 0x7FFE42B000ull
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|
#define DMA_IF_E_S_SOB_WR_BMON_MAX_OFFSET 0x1000
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|
#define DMA_IF_E_S_SOB_WR_BMON_SECTION 0x4000
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|
#define mmDMA_IF_E_S_FUNNEL_BASE 0x7FFE42F000ull
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|
#define DMA_IF_E_S_FUNNEL_MAX_OFFSET 0x1000
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|
#define DMA_IF_E_S_FUNNEL_SECTION 0x12000
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|
#define mmDMA_IF_W_N_STM_BASE 0x7FFE441000ull
|
|
#define DMA_IF_W_N_STM_MAX_OFFSET 0x1000
|
|
#define DMA_IF_W_N_STM_SECTION 0x1000
|
|
#define mmDMA_IF_W_N_CTI_BASE 0x7FFE442000ull
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|
#define DMA_IF_W_N_CTI_MAX_OFFSET 0x1000
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|
#define DMA_IF_W_N_CTI_SECTION 0x1000
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|
#define mmDMA_IF_W_N_ETF_BASE 0x7FFE443000ull
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|
#define DMA_IF_W_N_ETF_MAX_OFFSET 0x1000
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|
#define DMA_IF_W_N_ETF_SECTION 0x2000
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|
#define mmDMA_IF_W_N_BMON0_CTI_BASE 0x7FFE445000ull
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|
#define DMA_IF_W_N_BMON0_CTI_MAX_OFFSET 0x1000
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|
#define DMA_IF_W_N_BMON0_CTI_SECTION 0x1000
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|
#define mmDMA_IF_W_N_BMON1_CTI_BASE 0x7FFE446000ull
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#define DMA_IF_W_N_BMON1_CTI_MAX_OFFSET 0x1000
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|
#define DMA_IF_W_N_BMON1_CTI_SECTION 0x1000
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|
#define mmDMA_IF_W_N_HBM0_WR_BMON_BASE 0x7FFE447000ull
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|
#define DMA_IF_W_N_HBM0_WR_BMON_MAX_OFFSET 0x1000
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|
#define DMA_IF_W_N_HBM0_WR_BMON_SECTION 0x1000
|
|
#define mmDMA_IF_W_N_HBM0_RD_BMON_BASE 0x7FFE448000ull
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|
#define DMA_IF_W_N_HBM0_RD_BMON_MAX_OFFSET 0x1000
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|
#define DMA_IF_W_N_HBM0_RD_BMON_SECTION 0x1000
|
|
#define mmDMA_IF_W_N_HBM1_WR_BMON_BASE 0x7FFE449000ull
|
|
#define DMA_IF_W_N_HBM1_WR_BMON_MAX_OFFSET 0x1000
|
|
#define DMA_IF_W_N_HBM1_WR_BMON_SECTION 0x1000
|
|
#define mmDMA_IF_W_N_HBM1_RD_BMON_BASE 0x7FFE44A000ull
|
|
#define DMA_IF_W_N_HBM1_RD_BMON_MAX_OFFSET 0x1000
|
|
#define DMA_IF_W_N_HBM1_RD_BMON_SECTION 0x1000
|
|
#define mmDMA_IF_W_N_SOB_WR_BMON_BASE 0x7FFE44B000ull
|
|
#define DMA_IF_W_N_SOB_WR_BMON_MAX_OFFSET 0x1000
|
|
#define DMA_IF_W_N_SOB_WR_BMON_SECTION 0x4000
|
|
#define mmDMA_IF_W_N_FUNNEL_BASE 0x7FFE44F000ull
|
|
#define DMA_IF_W_N_FUNNEL_MAX_OFFSET 0x1000
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|
#define DMA_IF_W_N_FUNNEL_SECTION 0x12000
|
|
#define mmDMA_IF_E_N_STM_BASE 0x7FFE461000ull
|
|
#define DMA_IF_E_N_STM_MAX_OFFSET 0x1000
|
|
#define DMA_IF_E_N_STM_SECTION 0x1000
|
|
#define mmDMA_IF_E_N_CTI_BASE 0x7FFE462000ull
|
|
#define DMA_IF_E_N_CTI_MAX_OFFSET 0x1000
|
|
#define DMA_IF_E_N_CTI_SECTION 0x1000
|
|
#define mmDMA_IF_E_N_ETF_BASE 0x7FFE463000ull
|
|
#define DMA_IF_E_N_ETF_MAX_OFFSET 0x1000
|
|
#define DMA_IF_E_N_ETF_SECTION 0x2000
|
|
#define mmDMA_IF_E_N_BMON0_CTI_BASE 0x7FFE465000ull
|
|
#define DMA_IF_E_N_BMON0_CTI_MAX_OFFSET 0x1000
|
|
#define DMA_IF_E_N_BMON0_CTI_SECTION 0x1000
|
|
#define mmDMA_IF_E_N_BMON1_CTI_BASE 0x7FFE466000ull
|
|
#define DMA_IF_E_N_BMON1_CTI_MAX_OFFSET 0x1000
|
|
#define DMA_IF_E_N_BMON1_CTI_SECTION 0x1000
|
|
#define mmDMA_IF_E_N_HBM0_WR_BMON_BASE 0x7FFE467000ull
|
|
#define DMA_IF_E_N_HBM0_WR_BMON_MAX_OFFSET 0x1000
|
|
#define DMA_IF_E_N_HBM0_WR_BMON_SECTION 0x1000
|
|
#define mmDMA_IF_E_N_HBM0_RD_BMON_BASE 0x7FFE468000ull
|
|
#define DMA_IF_E_N_HBM0_RD_BMON_MAX_OFFSET 0x1000
|
|
#define DMA_IF_E_N_HBM0_RD_BMON_SECTION 0x1000
|
|
#define mmDMA_IF_E_N_HBM1_WR_BMON_BASE 0x7FFE469000ull
|
|
#define DMA_IF_E_N_HBM1_WR_BMON_MAX_OFFSET 0x1000
|
|
#define DMA_IF_E_N_HBM1_WR_BMON_SECTION 0x1000
|
|
#define mmDMA_IF_E_N_HBM1_RD_BMON_BASE 0x7FFE46A000ull
|
|
#define DMA_IF_E_N_HBM1_RD_BMON_MAX_OFFSET 0x1000
|
|
#define DMA_IF_E_N_HBM1_RD_BMON_SECTION 0x1000
|
|
#define mmDMA_IF_E_N_SOB_WR_BMON_BASE 0x7FFE46B000ull
|
|
#define DMA_IF_E_N_SOB_WR_BMON_MAX_OFFSET 0x1000
|
|
#define DMA_IF_E_N_SOB_WR_BMON_SECTION 0x4000
|
|
#define mmDMA_IF_E_N_FUNNEL_BASE 0x7FFE46F000ull
|
|
#define DMA_IF_E_N_FUNNEL_MAX_OFFSET 0x1000
|
|
#define DMA_IF_E_N_FUNNEL_SECTION 0x11000
|
|
#define mmCPU_ROM_TABLE_BASE 0x7FFE480000ull
|
|
#define CPU_ROM_TABLE_MAX_OFFSET 0x1000
|
|
#define CPU_ROM_TABLE_SECTION 0x1000
|
|
#define mmCPU_ETF_0_BASE 0x7FFE481000ull
|
|
#define CPU_ETF_0_MAX_OFFSET 0x1000
|
|
#define CPU_ETF_0_SECTION 0x1000
|
|
#define mmCPU_ETF_1_BASE 0x7FFE482000ull
|
|
#define CPU_ETF_1_MAX_OFFSET 0x1000
|
|
#define CPU_ETF_1_SECTION 0x2000
|
|
#define mmCPU_CTI_BASE 0x7FFE484000ull
|
|
#define CPU_CTI_MAX_OFFSET 0x1000
|
|
#define CPU_CTI_SECTION 0x1000
|
|
#define mmCPU_FUNNEL_BASE 0x7FFE485000ull
|
|
#define CPU_FUNNEL_MAX_OFFSET 0x1000
|
|
#define CPU_FUNNEL_SECTION 0x1000
|
|
#define mmCPU_STM_BASE 0x7FFE486000ull
|
|
#define CPU_STM_MAX_OFFSET 0x1000
|
|
#define CPU_STM_SECTION 0x1000
|
|
#define mmCPU_CTI_TRACE_BASE 0x7FFE487000ull
|
|
#define CPU_CTI_TRACE_MAX_OFFSET 0x1000
|
|
#define CPU_CTI_TRACE_SECTION 0x1000
|
|
#define mmCPU_ETF_TRACE_BASE 0x7FFE488000ull
|
|
#define CPU_ETF_TRACE_MAX_OFFSET 0x1000
|
|
#define CPU_ETF_TRACE_SECTION 0x1000
|
|
#define mmCPU_WR_BMON_BASE 0x7FFE489000ull
|
|
#define CPU_WR_BMON_MAX_OFFSET 0x1000
|
|
#define CPU_WR_BMON_SECTION 0x1000
|
|
#define mmCPU_RD_BMON_BASE 0x7FFE48A000ull
|
|
#define CPU_RD_BMON_MAX_OFFSET 0x1000
|
|
#define CPU_RD_BMON_SECTION 0x76000
|
|
#define mmDMA_ROM_TABLE_BASE 0x7FFE500000ull
|
|
#define DMA_ROM_TABLE_MAX_OFFSET 0x1000
|
|
#define DMA_ROM_TABLE_SECTION 0x1000
|
|
#define mmDMA_CH_0_CS_STM_BASE 0x7FFE501000ull
|
|
#define DMA_CH_0_CS_STM_MAX_OFFSET 0x1000
|
|
#define DMA_CH_0_CS_STM_SECTION 0x1000
|
|
#define mmDMA_CH_0_CS_CTI_BASE 0x7FFE502000ull
|
|
#define DMA_CH_0_CS_CTI_MAX_OFFSET 0x1000
|
|
#define DMA_CH_0_CS_CTI_SECTION 0x1000
|
|
#define mmDMA_CH_0_CS_ETF_BASE 0x7FFE503000ull
|
|
#define DMA_CH_0_CS_ETF_MAX_OFFSET 0x1000
|
|
#define DMA_CH_0_CS_ETF_SECTION 0x1000
|
|
#define mmDMA_CH_0_CS_SPMU_BASE 0x7FFE504000ull
|
|
#define DMA_CH_0_CS_SPMU_MAX_OFFSET 0x1000
|
|
#define DMA_CH_0_CS_SPMU_SECTION 0x1000
|
|
#define mmDMA_CH_0_BMON_CTI_BASE 0x7FFE505000ull
|
|
#define DMA_CH_0_BMON_CTI_MAX_OFFSET 0x1000
|
|
#define DMA_CH_0_BMON_CTI_SECTION 0x1000
|
|
#define mmDMA_CH_0_USER_CTI_BASE 0x7FFE506000ull
|
|
#define DMA_CH_0_USER_CTI_MAX_OFFSET 0x1000
|
|
#define DMA_CH_0_USER_CTI_SECTION 0x1000
|
|
#define mmDMA_CH_0_BMON_0_BASE 0x7FFE507000ull
|
|
#define DMA_CH_0_BMON_0_MAX_OFFSET 0x1000
|
|
#define DMA_CH_0_BMON_0_SECTION 0x1000
|
|
#define mmDMA_CH_0_BMON_1_BASE 0x7FFE508000ull
|
|
#define DMA_CH_0_BMON_1_MAX_OFFSET 0x1000
|
|
#define DMA_CH_0_BMON_1_SECTION 0x19000
|
|
#define mmDMA_CH_1_CS_STM_BASE 0x7FFE521000ull
|
|
#define DMA_CH_1_CS_STM_MAX_OFFSET 0x1000
|
|
#define DMA_CH_1_CS_STM_SECTION 0x1000
|
|
#define mmDMA_CH_1_CS_CTI_BASE 0x7FFE522000ull
|
|
#define DMA_CH_1_CS_CTI_MAX_OFFSET 0x1000
|
|
#define DMA_CH_1_CS_CTI_SECTION 0x1000
|
|
#define mmDMA_CH_1_CS_ETF_BASE 0x7FFE523000ull
|
|
#define DMA_CH_1_CS_ETF_MAX_OFFSET 0x1000
|
|
#define DMA_CH_1_CS_ETF_SECTION 0x1000
|
|
#define mmDMA_CH_1_CS_SPMU_BASE 0x7FFE524000ull
|
|
#define DMA_CH_1_CS_SPMU_MAX_OFFSET 0x1000
|
|
#define DMA_CH_1_CS_SPMU_SECTION 0x1000
|
|
#define mmDMA_CH_1_BMON_CTI_BASE 0x7FFE525000ull
|
|
#define DMA_CH_1_BMON_CTI_MAX_OFFSET 0x1000
|
|
#define DMA_CH_1_BMON_CTI_SECTION 0x1000
|
|
#define mmDMA_CH_1_USER_CTI_BASE 0x7FFE526000ull
|
|
#define DMA_CH_1_USER_CTI_MAX_OFFSET 0x1000
|
|
#define DMA_CH_1_USER_CTI_SECTION 0x1000
|
|
#define mmDMA_CH_1_BMON_0_BASE 0x7FFE527000ull
|
|
#define DMA_CH_1_BMON_0_MAX_OFFSET 0x1000
|
|
#define DMA_CH_1_BMON_0_SECTION 0x1000
|
|
#define mmDMA_CH_1_BMON_1_BASE 0x7FFE528000ull
|
|
#define DMA_CH_1_BMON_1_MAX_OFFSET 0x1000
|
|
#define DMA_CH_1_BMON_1_SECTION 0x19000
|
|
#define mmDMA_CH_2_CS_STM_BASE 0x7FFE541000ull
|
|
#define DMA_CH_2_CS_STM_MAX_OFFSET 0x1000
|
|
#define DMA_CH_2_CS_STM_SECTION 0x1000
|
|
#define mmDMA_CH_2_CS_CTI_BASE 0x7FFE542000ull
|
|
#define DMA_CH_2_CS_CTI_MAX_OFFSET 0x1000
|
|
#define DMA_CH_2_CS_CTI_SECTION 0x1000
|
|
#define mmDMA_CH_2_CS_ETF_BASE 0x7FFE543000ull
|
|
#define DMA_CH_2_CS_ETF_MAX_OFFSET 0x1000
|
|
#define DMA_CH_2_CS_ETF_SECTION 0x1000
|
|
#define mmDMA_CH_2_CS_SPMU_BASE 0x7FFE544000ull
|
|
#define DMA_CH_2_CS_SPMU_MAX_OFFSET 0x1000
|
|
#define DMA_CH_2_CS_SPMU_SECTION 0x1000
|
|
#define mmDMA_CH_2_BMON_CTI_BASE 0x7FFE545000ull
|
|
#define DMA_CH_2_BMON_CTI_MAX_OFFSET 0x1000
|
|
#define DMA_CH_2_BMON_CTI_SECTION 0x1000
|
|
#define mmDMA_CH_2_USER_CTI_BASE 0x7FFE546000ull
|
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#define DMA_CH_2_USER_CTI_MAX_OFFSET 0x1000
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#define DMA_CH_2_USER_CTI_SECTION 0x1000
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#define mmDMA_CH_2_BMON_0_BASE 0x7FFE547000ull
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#define DMA_CH_2_BMON_0_MAX_OFFSET 0x1000
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#define DMA_CH_2_BMON_0_SECTION 0x1000
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#define mmDMA_CH_2_BMON_1_BASE 0x7FFE548000ull
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#define DMA_CH_2_BMON_1_MAX_OFFSET 0x1000
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#define DMA_CH_2_BMON_1_SECTION 0x19000
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#define mmDMA_CH_3_CS_STM_BASE 0x7FFE561000ull
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#define DMA_CH_3_CS_STM_MAX_OFFSET 0x1000
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#define DMA_CH_3_CS_STM_SECTION 0x1000
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#define mmDMA_CH_3_CS_CTI_BASE 0x7FFE562000ull
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#define DMA_CH_3_CS_CTI_MAX_OFFSET 0x1000
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#define DMA_CH_3_CS_CTI_SECTION 0x1000
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#define mmDMA_CH_3_CS_ETF_BASE 0x7FFE563000ull
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#define DMA_CH_3_CS_ETF_MAX_OFFSET 0x1000
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#define DMA_CH_3_CS_ETF_SECTION 0x1000
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#define mmDMA_CH_3_CS_SPMU_BASE 0x7FFE564000ull
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#define DMA_CH_3_CS_SPMU_MAX_OFFSET 0x1000
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#define DMA_CH_3_CS_SPMU_SECTION 0x1000
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#define mmDMA_CH_3_BMON_CTI_BASE 0x7FFE565000ull
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#define DMA_CH_3_BMON_CTI_MAX_OFFSET 0x1000
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#define DMA_CH_3_BMON_CTI_SECTION 0x1000
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#define mmDMA_CH_3_USER_CTI_BASE 0x7FFE566000ull
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#define DMA_CH_3_USER_CTI_MAX_OFFSET 0x1000
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#define DMA_CH_3_USER_CTI_SECTION 0x1000
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#define mmDMA_CH_3_BMON_0_BASE 0x7FFE567000ull
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#define DMA_CH_3_BMON_0_MAX_OFFSET 0x1000
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#define DMA_CH_3_BMON_0_SECTION 0x1000
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#define mmDMA_CH_3_BMON_1_BASE 0x7FFE568000ull
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#define DMA_CH_3_BMON_1_MAX_OFFSET 0x1000
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#define DMA_CH_3_BMON_1_SECTION 0x19000
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#define mmDMA_CH_4_CS_STM_BASE 0x7FFE581000ull
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#define DMA_CH_4_CS_STM_MAX_OFFSET 0x1000
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#define DMA_CH_4_CS_STM_SECTION 0x1000
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#define mmDMA_CH_4_CS_CTI_BASE 0x7FFE582000ull
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#define DMA_CH_4_CS_CTI_MAX_OFFSET 0x1000
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#define DMA_CH_4_CS_CTI_SECTION 0x1000
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#define mmDMA_CH_4_CS_ETF_BASE 0x7FFE583000ull
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#define DMA_CH_4_CS_ETF_MAX_OFFSET 0x1000
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#define DMA_CH_4_CS_ETF_SECTION 0x1000
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#define mmDMA_CH_4_CS_SPMU_BASE 0x7FFE584000ull
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#define DMA_CH_4_CS_SPMU_MAX_OFFSET 0x1000
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#define DMA_CH_4_CS_SPMU_SECTION 0x1000
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#define mmDMA_CH_4_BMON_CTI_BASE 0x7FFE585000ull
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#define DMA_CH_4_BMON_CTI_MAX_OFFSET 0x1000
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#define DMA_CH_4_BMON_CTI_SECTION 0x1000
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#define mmDMA_CH_4_USER_CTI_BASE 0x7FFE586000ull
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#define DMA_CH_4_USER_CTI_MAX_OFFSET 0x1000
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#define DMA_CH_4_USER_CTI_SECTION 0x1000
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#define mmDMA_CH_4_BMON_0_BASE 0x7FFE587000ull
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#define DMA_CH_4_BMON_0_MAX_OFFSET 0x1000
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#define DMA_CH_4_BMON_0_SECTION 0x1000
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#define mmDMA_CH_4_BMON_1_BASE 0x7FFE588000ull
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#define DMA_CH_4_BMON_1_MAX_OFFSET 0x1000
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#define DMA_CH_4_BMON_1_SECTION 0x19000
|
|
#define mmDMA_CH_5_CS_STM_BASE 0x7FFE5A1000ull
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#define DMA_CH_5_CS_STM_MAX_OFFSET 0x1000
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#define DMA_CH_5_CS_STM_SECTION 0x1000
|
|
#define mmDMA_CH_5_CS_CTI_BASE 0x7FFE5A2000ull
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#define DMA_CH_5_CS_CTI_MAX_OFFSET 0x1000
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|
#define DMA_CH_5_CS_CTI_SECTION 0x1000
|
|
#define mmDMA_CH_5_CS_ETF_BASE 0x7FFE5A3000ull
|
|
#define DMA_CH_5_CS_ETF_MAX_OFFSET 0x1000
|
|
#define DMA_CH_5_CS_ETF_SECTION 0x1000
|
|
#define mmDMA_CH_5_CS_SPMU_BASE 0x7FFE5A4000ull
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|
#define DMA_CH_5_CS_SPMU_MAX_OFFSET 0x1000
|
|
#define DMA_CH_5_CS_SPMU_SECTION 0x1000
|
|
#define mmDMA_CH_5_BMON_CTI_BASE 0x7FFE5A5000ull
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|
#define DMA_CH_5_BMON_CTI_MAX_OFFSET 0x1000
|
|
#define DMA_CH_5_BMON_CTI_SECTION 0x1000
|
|
#define mmDMA_CH_5_USER_CTI_BASE 0x7FFE5A6000ull
|
|
#define DMA_CH_5_USER_CTI_MAX_OFFSET 0x1000
|
|
#define DMA_CH_5_USER_CTI_SECTION 0x1000
|
|
#define mmDMA_CH_5_BMON_0_BASE 0x7FFE5A7000ull
|
|
#define DMA_CH_5_BMON_0_MAX_OFFSET 0x1000
|
|
#define DMA_CH_5_BMON_0_SECTION 0x1000
|
|
#define mmDMA_CH_5_BMON_1_BASE 0x7FFE5A8000ull
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|
#define DMA_CH_5_BMON_1_MAX_OFFSET 0x1000
|
|
#define DMA_CH_5_BMON_1_SECTION 0x19000
|
|
#define mmDMA_CH_6_CS_STM_BASE 0x7FFE5C1000ull
|
|
#define DMA_CH_6_CS_STM_MAX_OFFSET 0x1000
|
|
#define DMA_CH_6_CS_STM_SECTION 0x1000
|
|
#define mmDMA_CH_6_CS_CTI_BASE 0x7FFE5C2000ull
|
|
#define DMA_CH_6_CS_CTI_MAX_OFFSET 0x1000
|
|
#define DMA_CH_6_CS_CTI_SECTION 0x1000
|
|
#define mmDMA_CH_6_CS_ETF_BASE 0x7FFE5C3000ull
|
|
#define DMA_CH_6_CS_ETF_MAX_OFFSET 0x1000
|
|
#define DMA_CH_6_CS_ETF_SECTION 0x1000
|
|
#define mmDMA_CH_6_CS_SPMU_BASE 0x7FFE5C4000ull
|
|
#define DMA_CH_6_CS_SPMU_MAX_OFFSET 0x1000
|
|
#define DMA_CH_6_CS_SPMU_SECTION 0x1000
|
|
#define mmDMA_CH_6_BMON_CTI_BASE 0x7FFE5C5000ull
|
|
#define DMA_CH_6_BMON_CTI_MAX_OFFSET 0x1000
|
|
#define DMA_CH_6_BMON_CTI_SECTION 0x1000
|
|
#define mmDMA_CH_6_USER_CTI_BASE 0x7FFE5C6000ull
|
|
#define DMA_CH_6_USER_CTI_MAX_OFFSET 0x1000
|
|
#define DMA_CH_6_USER_CTI_SECTION 0x1000
|
|
#define mmDMA_CH_6_BMON_0_BASE 0x7FFE5C7000ull
|
|
#define DMA_CH_6_BMON_0_MAX_OFFSET 0x1000
|
|
#define DMA_CH_6_BMON_0_SECTION 0x1000
|
|
#define mmDMA_CH_6_BMON_1_BASE 0x7FFE5C8000ull
|
|
#define DMA_CH_6_BMON_1_MAX_OFFSET 0x1000
|
|
#define DMA_CH_6_BMON_1_SECTION 0x19000
|
|
#define mmDMA_CH_7_CS_STM_BASE 0x7FFE5E1000ull
|
|
#define DMA_CH_7_CS_STM_MAX_OFFSET 0x1000
|
|
#define DMA_CH_7_CS_STM_SECTION 0x1000
|
|
#define mmDMA_CH_7_CS_CTI_BASE 0x7FFE5E2000ull
|
|
#define DMA_CH_7_CS_CTI_MAX_OFFSET 0x1000
|
|
#define DMA_CH_7_CS_CTI_SECTION 0x1000
|
|
#define mmDMA_CH_7_CS_ETF_BASE 0x7FFE5E3000ull
|
|
#define DMA_CH_7_CS_ETF_MAX_OFFSET 0x1000
|
|
#define DMA_CH_7_CS_ETF_SECTION 0x1000
|
|
#define mmDMA_CH_7_CS_SPMU_BASE 0x7FFE5E4000ull
|
|
#define DMA_CH_7_CS_SPMU_MAX_OFFSET 0x1000
|
|
#define DMA_CH_7_CS_SPMU_SECTION 0x1000
|
|
#define mmDMA_CH_7_BMON_CTI_BASE 0x7FFE5E5000ull
|
|
#define DMA_CH_7_BMON_CTI_MAX_OFFSET 0x1000
|
|
#define DMA_CH_7_BMON_CTI_SECTION 0x1000
|
|
#define mmDMA_CH_7_USER_CTI_BASE 0x7FFE5E6000ull
|
|
#define DMA_CH_7_USER_CTI_MAX_OFFSET 0x1000
|
|
#define DMA_CH_7_USER_CTI_SECTION 0x1000
|
|
#define mmDMA_CH_7_BMON_0_BASE 0x7FFE5E7000ull
|
|
#define DMA_CH_7_BMON_0_MAX_OFFSET 0x1000
|
|
#define DMA_CH_7_BMON_0_SECTION 0x1000
|
|
#define mmDMA_CH_7_BMON_1_BASE 0x7FFE5E8000ull
|
|
#define DMA_CH_7_BMON_1_MAX_OFFSET 0x1000
|
|
#define DMA_CH_7_BMON_1_SECTION 0x18000
|
|
#define mmNIC_TPC_FUNNEL_W_S_BASE 0x7FFE600000ull
|
|
#define NIC_TPC_FUNNEL_W_S_MAX_OFFSET 0x1000
|
|
#define NIC_TPC_FUNNEL_W_S_SECTION 0x80000
|
|
#define mmNIC_TPC_FUNNEL_E_S_BASE 0x7FFE680000ull
|
|
#define NIC_TPC_FUNNEL_E_S_MAX_OFFSET 0x1000
|
|
#define NIC_TPC_FUNNEL_E_S_SECTION 0x80000
|
|
#define mmNIC_TPC_FUNNEL_W_N_BASE 0x7FFE700000ull
|
|
#define NIC_TPC_FUNNEL_W_N_MAX_OFFSET 0x1000
|
|
#define NIC_TPC_FUNNEL_W_N_SECTION 0x80000
|
|
#define mmNIC_TPC_FUNNEL_E_N_BASE 0x7FFE780000ull
|
|
#define NIC_TPC_FUNNEL_E_N_MAX_OFFSET 0x1000
|
|
#define NIC_TPC_FUNNEL_E_N_SECTION 0x80000
|
|
#define mmCA53_BASE 0x7FFE800000ull
|
|
#define CA53_MAX_OFFSET 0x141000
|
|
#define CA53_SECTION 0x400000
|
|
#define mmPCI_ROM_TABLE_BASE 0x7FFEC00000ull
|
|
#define PCI_ROM_TABLE_MAX_OFFSET 0x1000
|
|
#define PCI_ROM_TABLE_SECTION 0x1000
|
|
#define mmPCIE_STM_BASE 0x7FFEC01000ull
|
|
#define PCIE_STM_MAX_OFFSET 0x1000
|
|
#define PCIE_STM_SECTION 0x1000
|
|
#define mmPCIE_ETF_BASE 0x7FFEC02000ull
|
|
#define PCIE_ETF_MAX_OFFSET 0x1000
|
|
#define PCIE_ETF_SECTION 0x1000
|
|
#define mmPCIE_CTI_0_BASE 0x7FFEC03000ull
|
|
#define PCIE_CTI_0_MAX_OFFSET 0x1000
|
|
#define PCIE_CTI_0_SECTION 0x1000
|
|
#define mmPCIE_SPMU_BASE 0x7FFEC04000ull
|
|
#define PCIE_SPMU_MAX_OFFSET 0x1000
|
|
#define PCIE_SPMU_SECTION 0x1000
|
|
#define mmPCIE_CTI_1_BASE 0x7FFEC05000ull
|
|
#define PCIE_CTI_1_MAX_OFFSET 0x1000
|
|
#define PCIE_CTI_1_SECTION 0x1000
|
|
#define mmPCIE_FUNNEL_BASE 0x7FFEC06000ull
|
|
#define PCIE_FUNNEL_MAX_OFFSET 0x1000
|
|
#define PCIE_FUNNEL_SECTION 0x1000
|
|
#define mmPCIE_BMON_MSTR_WR_BASE 0x7FFEC07000ull
|
|
#define PCIE_BMON_MSTR_WR_MAX_OFFSET 0x1000
|
|
#define PCIE_BMON_MSTR_WR_SECTION 0x1000
|
|
#define mmPCIE_BMON_MSTR_RD_BASE 0x7FFEC08000ull
|
|
#define PCIE_BMON_MSTR_RD_MAX_OFFSET 0x1000
|
|
#define PCIE_BMON_MSTR_RD_SECTION 0x1000
|
|
#define mmPCIE_BMON_SLV_WR_BASE 0x7FFEC09000ull
|
|
#define PCIE_BMON_SLV_WR_MAX_OFFSET 0x1000
|
|
#define PCIE_BMON_SLV_WR_SECTION 0x1000
|
|
#define mmPCIE_BMON_SLV_RD_BASE 0x7FFEC0A000ull
|
|
#define PCIE_BMON_SLV_RD_MAX_OFFSET 0x1000
|
|
#define PCIE_BMON_SLV_RD_SECTION 0x7000
|
|
#define mmMMU_CS_STM_BASE 0x7FFEC11000ull
|
|
#define MMU_CS_STM_MAX_OFFSET 0x1000
|
|
#define MMU_CS_STM_SECTION 0x1000
|
|
#define mmMMU_CS_CTI_BASE 0x7FFEC12000ull
|
|
#define MMU_CS_CTI_MAX_OFFSET 0x1000
|
|
#define MMU_CS_CTI_SECTION 0x1000
|
|
#define mmMMU_CS_ETF_BASE 0x7FFEC13000ull
|
|
#define MMU_CS_ETF_MAX_OFFSET 0x1000
|
|
#define MMU_CS_ETF_SECTION 0x1000
|
|
#define mmMMU_CS_SPMU_BASE 0x7FFEC14000ull
|
|
#define MMU_CS_SPMU_MAX_OFFSET 0x1000
|
|
#define MMU_CS_SPMU_SECTION 0x1000
|
|
#define mmMMU_BMON_CTI_BASE 0x7FFEC15000ull
|
|
#define MMU_BMON_CTI_MAX_OFFSET 0x1000
|
|
#define MMU_BMON_CTI_SECTION 0x1000
|
|
#define mmMMU_USER_CTI_BASE 0x7FFEC16000ull
|
|
#define MMU_USER_CTI_MAX_OFFSET 0x1000
|
|
#define MMU_USER_CTI_SECTION 0x1000
|
|
#define mmMMU_BMON_0_BASE 0x7FFEC17000ull
|
|
#define MMU_BMON_0_MAX_OFFSET 0x1000
|
|
#define MMU_BMON_0_SECTION 0x1000
|
|
#define mmMMU_BMON_1_BASE 0x7FFEC18000ull
|
|
#define MMU_BMON_1_MAX_OFFSET 0x1000
|
|
#define MMU_BMON_1_SECTION 0x28000
|
|
#define mmPSOC_CTI_BASE 0x7FFEC40000ull
|
|
#define PSOC_CTI_MAX_OFFSET 0x1000
|
|
#define PSOC_CTI_SECTION 0x1000
|
|
#define mmPSOC_STM_BASE 0x7FFEC41000ull
|
|
#define PSOC_STM_MAX_OFFSET 0x1000
|
|
#define PSOC_STM_SECTION 0x1000
|
|
#define mmPSOC_FUNNEL_BASE 0x7FFEC42000ull
|
|
#define PSOC_FUNNEL_MAX_OFFSET 0x1000
|
|
#define PSOC_FUNNEL_SECTION 0x1000
|
|
#define mmPSOC_ETR_BASE 0x7FFEC43000ull
|
|
#define PSOC_ETR_MAX_OFFSET 0x1000
|
|
#define PSOC_ETR_SECTION 0x1000
|
|
#define mmPSOC_ETF_BASE 0x7FFEC44000ull
|
|
#define PSOC_ETF_MAX_OFFSET 0x1000
|
|
#define PSOC_ETF_SECTION 0x1000
|
|
#define mmPSOC_TS_CTI_BASE 0x7FFEC45000ull
|
|
#define PSOC_TS_CTI_MAX_OFFSET 0x1000
|
|
#define PSOC_TS_CTI_SECTION 0xB000
|
|
#define mmTOP_ROM_TABLE_BASE 0x7FFEC50000ull
|
|
#define TOP_ROM_TABLE_MAX_OFFSET 0x1000
|
|
#define TOP_ROM_TABLE_SECTION 0x70000
|
|
#define mmNIC0_ROM_TABLE_BASE 0x7FFECC0000ull
|
|
#define NIC0_ROM_TABLE_MAX_OFFSET 0x1000
|
|
#define NIC0_ROM_TABLE_SECTION 0x1000
|
|
#define mmSTM_0_NIC0_DBG_BASE 0x7FFECC1000ull
|
|
#define STM_0_NIC0_DBG_MAX_OFFSET 0x21000
|
|
#define STM_0_NIC0_DBG_SECTION 0x1000
|
|
#define mmCTI_0_NIC0_DBG_BASE 0x7FFECC2000ull
|
|
#define CTI_0_NIC0_DBG_MAX_OFFSET 0x1000
|
|
#define CTI_0_NIC0_DBG_SECTION 0x1000
|
|
#define mmETF_0_NIC0_DBG_BASE 0x7FFECC3000ull
|
|
#define ETF_0_NIC0_DBG_MAX_OFFSET 0x1000
|
|
#define ETF_0_NIC0_DBG_SECTION 0x1000
|
|
#define mmSPMU_0_NIC0_DBG_BASE 0x7FFECC4000ull
|
|
#define SPMU_0_NIC0_DBG_MAX_OFFSET 0x1000
|
|
#define SPMU_0_NIC0_DBG_SECTION 0x2000
|
|
#define mmUSER_CTI_0_NIC0_DBG_BASE 0x7FFECC6000ull
|
|
#define USER_CTI_0_NIC0_DBG_MAX_OFFSET 0x1000
|
|
#define USER_CTI_0_NIC0_DBG_SECTION 0xB000
|
|
#define mmSTM_1_NIC0_DBG_BASE 0x7FFECD1000ull
|
|
#define STM_1_NIC0_DBG_MAX_OFFSET 0x1000
|
|
#define STM_1_NIC0_DBG_SECTION 0x1000
|
|
#define mmCTI_1_NIC0_DBG_BASE 0x7FFECD2000ull
|
|
#define CTI_1_NIC0_DBG_MAX_OFFSET 0x1000
|
|
#define CTI_1_NIC0_DBG_SECTION 0x1000
|
|
#define mmETF_1_NIC0_DBG_BASE 0x7FFECD3000ull
|
|
#define ETF_1_NIC0_DBG_MAX_OFFSET 0x1000
|
|
#define ETF_1_NIC0_DBG_SECTION 0x1000
|
|
#define mmSPMU_1_NIC0_DBG_BASE 0x7FFECD4000ull
|
|
#define SPMU_1_NIC0_DBG_MAX_OFFSET 0x1000
|
|
#define SPMU_1_NIC0_DBG_SECTION 0x1000
|
|
#define mmBMON_CTI_NIC0_DBG_BASE 0x7FFECD5000ull
|
|
#define BMON_CTI_NIC0_DBG_MAX_OFFSET 0x1000
|
|
#define BMON_CTI_NIC0_DBG_SECTION 0x1000
|
|
#define mmUSER_CTI_1_NIC0_DBG_BASE 0x7FFECD6000ull
|
|
#define USER_CTI_1_NIC0_DBG_MAX_OFFSET 0x1000
|
|
#define USER_CTI_1_NIC0_DBG_SECTION 0x1000
|
|
#define mmBMON0_NIC0_DBG_BASE 0x7FFECD7000ull
|
|
#define BMON0_NIC0_DBG_MAX_OFFSET 0x1000
|
|
#define BMON0_NIC0_DBG_SECTION 0x1000
|
|
#define mmBMON1_NIC0_DBG_BASE 0x7FFECD8000ull
|
|
#define BMON1_NIC0_DBG_MAX_OFFSET 0x1000
|
|
#define BMON1_NIC0_DBG_SECTION 0x1000
|
|
#define mmBMON2_NIC0_DBG_BASE 0x7FFECD9000ull
|
|
#define BMON2_NIC0_DBG_MAX_OFFSET 0x1000
|
|
#define BMON2_NIC0_DBG_SECTION 0x1000
|
|
#define mmBMON3_NIC0_DBG_BASE 0x7FFECDA000ull
|
|
#define BMON3_NIC0_DBG_MAX_OFFSET 0x1000
|
|
#define BMON3_NIC0_DBG_SECTION 0x1000
|
|
#define mmBMON4_NIC0_DBG_BASE 0x7FFECDB000ull
|
|
#define BMON4_NIC0_DBG_MAX_OFFSET 0x1000
|
|
#define BMON4_NIC0_DBG_SECTION 0x6000
|
|
#define mmFUNNEL_NIC0_DBG_BASE 0x7FFECE1000ull
|
|
#define FUNNEL_NIC0_DBG_MAX_OFFSET 0x1000
|
|
#define FUNNEL_NIC0_DBG_SECTION 0x1F000
|
|
#define mmNIC1_ROM_TABLE_BASE 0x7FFED00000ull
|
|
#define NIC1_ROM_TABLE_MAX_OFFSET 0x1000
|
|
#define NIC1_ROM_TABLE_SECTION 0x1000
|
|
#define mmSTM_0_NIC1_DBG_BASE 0x7FFED01000ull
|
|
#define STM_0_NIC1_DBG_MAX_OFFSET 0x21000
|
|
#define STM_0_NIC1_DBG_SECTION 0x1000
|
|
#define mmCTI_0_NIC1_DBG_BASE 0x7FFED02000ull
|
|
#define CTI_0_NIC1_DBG_MAX_OFFSET 0x1000
|
|
#define CTI_0_NIC1_DBG_SECTION 0x1000
|
|
#define mmETF_0_NIC1_DBG_BASE 0x7FFED03000ull
|
|
#define ETF_0_NIC1_DBG_MAX_OFFSET 0x1000
|
|
#define ETF_0_NIC1_DBG_SECTION 0x1000
|
|
#define mmSPMU_0_NIC1_DBG_BASE 0x7FFED04000ull
|
|
#define SPMU_0_NIC1_DBG_MAX_OFFSET 0x1000
|
|
#define SPMU_0_NIC1_DBG_SECTION 0x2000
|
|
#define mmUSER_CTI_0_NIC1_DBG_BASE 0x7FFED06000ull
|
|
#define USER_CTI_0_NIC1_DBG_MAX_OFFSET 0x1000
|
|
#define USER_CTI_0_NIC1_DBG_SECTION 0xB000
|
|
#define mmSTM_1_NIC1_DBG_BASE 0x7FFED11000ull
|
|
#define STM_1_NIC1_DBG_MAX_OFFSET 0x1000
|
|
#define STM_1_NIC1_DBG_SECTION 0x1000
|
|
#define mmCTI_1_NIC1_DBG_BASE 0x7FFED12000ull
|
|
#define CTI_1_NIC1_DBG_MAX_OFFSET 0x1000
|
|
#define CTI_1_NIC1_DBG_SECTION 0x1000
|
|
#define mmETF_1_NIC1_DBG_BASE 0x7FFED13000ull
|
|
#define ETF_1_NIC1_DBG_MAX_OFFSET 0x1000
|
|
#define ETF_1_NIC1_DBG_SECTION 0x1000
|
|
#define mmSPMU_1_NIC1_DBG_BASE 0x7FFED14000ull
|
|
#define SPMU_1_NIC1_DBG_MAX_OFFSET 0x1000
|
|
#define SPMU_1_NIC1_DBG_SECTION 0x1000
|
|
#define mmBMON_CTI_NIC1_DBG_BASE 0x7FFED15000ull
|
|
#define BMON_CTI_NIC1_DBG_MAX_OFFSET 0x1000
|
|
#define BMON_CTI_NIC1_DBG_SECTION 0x1000
|
|
#define mmUSER_CTI_1_NIC1_DBG_BASE 0x7FFED16000ull
|
|
#define USER_CTI_1_NIC1_DBG_MAX_OFFSET 0x1000
|
|
#define USER_CTI_1_NIC1_DBG_SECTION 0x1000
|
|
#define mmBMON0_NIC1_DBG_BASE 0x7FFED17000ull
|
|
#define BMON0_NIC1_DBG_MAX_OFFSET 0x1000
|
|
#define BMON0_NIC1_DBG_SECTION 0x1000
|
|
#define mmBMON1_NIC1_DBG_BASE 0x7FFED18000ull
|
|
#define BMON1_NIC1_DBG_MAX_OFFSET 0x1000
|
|
#define BMON1_NIC1_DBG_SECTION 0x1000
|
|
#define mmBMON2_NIC1_DBG_BASE 0x7FFED19000ull
|
|
#define BMON2_NIC1_DBG_MAX_OFFSET 0x1000
|
|
#define BMON2_NIC1_DBG_SECTION 0x1000
|
|
#define mmBMON3_NIC1_DBG_BASE 0x7FFED1A000ull
|
|
#define BMON3_NIC1_DBG_MAX_OFFSET 0x1000
|
|
#define BMON3_NIC1_DBG_SECTION 0x1000
|
|
#define mmBMON4_NIC1_DBG_BASE 0x7FFED1B000ull
|
|
#define BMON4_NIC1_DBG_MAX_OFFSET 0x1000
|
|
#define BMON4_NIC1_DBG_SECTION 0x6000
|
|
#define mmFUNNEL_NIC1_DBG_BASE 0x7FFED21000ull
|
|
#define FUNNEL_NIC1_DBG_MAX_OFFSET 0x1000
|
|
#define FUNNEL_NIC1_DBG_SECTION 0x1F000
|
|
#define mmNIC2_ROM_TABLE_BASE 0x7FFED40000ull
|
|
#define NIC2_ROM_TABLE_MAX_OFFSET 0x1000
|
|
#define NIC2_ROM_TABLE_SECTION 0x1000
|
|
#define mmSTM_0_NIC2_DBG_BASE 0x7FFED41000ull
|
|
#define STM_0_NIC2_DBG_MAX_OFFSET 0x21000
|
|
#define STM_0_NIC2_DBG_SECTION 0x1000
|
|
#define mmCTI_0_NIC2_DBG_BASE 0x7FFED42000ull
|
|
#define CTI_0_NIC2_DBG_MAX_OFFSET 0x1000
|
|
#define CTI_0_NIC2_DBG_SECTION 0x1000
|
|
#define mmETF_0_NIC2_DBG_BASE 0x7FFED43000ull
|
|
#define ETF_0_NIC2_DBG_MAX_OFFSET 0x1000
|
|
#define ETF_0_NIC2_DBG_SECTION 0x1000
|
|
#define mmSPMU_0_NIC2_DBG_BASE 0x7FFED44000ull
|
|
#define SPMU_0_NIC2_DBG_MAX_OFFSET 0x1000
|
|
#define SPMU_0_NIC2_DBG_SECTION 0x2000
|
|
#define mmUSER_CTI_0_NIC2_DBG_BASE 0x7FFED46000ull
|
|
#define USER_CTI_0_NIC2_DBG_MAX_OFFSET 0x1000
|
|
#define USER_CTI_0_NIC2_DBG_SECTION 0xB000
|
|
#define mmSTM_1_NIC2_DBG_BASE 0x7FFED51000ull
|
|
#define STM_1_NIC2_DBG_MAX_OFFSET 0x1000
|
|
#define STM_1_NIC2_DBG_SECTION 0x1000
|
|
#define mmCTI_1_NIC2_DBG_BASE 0x7FFED52000ull
|
|
#define CTI_1_NIC2_DBG_MAX_OFFSET 0x1000
|
|
#define CTI_1_NIC2_DBG_SECTION 0x1000
|
|
#define mmETF_1_NIC2_DBG_BASE 0x7FFED53000ull
|
|
#define ETF_1_NIC2_DBG_MAX_OFFSET 0x1000
|
|
#define ETF_1_NIC2_DBG_SECTION 0x1000
|
|
#define mmSPMU_1_NIC2_DBG_BASE 0x7FFED54000ull
|
|
#define SPMU_1_NIC2_DBG_MAX_OFFSET 0x1000
|
|
#define SPMU_1_NIC2_DBG_SECTION 0x1000
|
|
#define mmBMON_CTI_NIC2_DBG_BASE 0x7FFED55000ull
|
|
#define BMON_CTI_NIC2_DBG_MAX_OFFSET 0x1000
|
|
#define BMON_CTI_NIC2_DBG_SECTION 0x1000
|
|
#define mmUSER_CTI_1_NIC2_DBG_BASE 0x7FFED56000ull
|
|
#define USER_CTI_1_NIC2_DBG_MAX_OFFSET 0x1000
|
|
#define USER_CTI_1_NIC2_DBG_SECTION 0x1000
|
|
#define mmBMON0_NIC2_DBG_BASE 0x7FFED57000ull
|
|
#define BMON0_NIC2_DBG_MAX_OFFSET 0x1000
|
|
#define BMON0_NIC2_DBG_SECTION 0x1000
|
|
#define mmBMON1_NIC2_DBG_BASE 0x7FFED58000ull
|
|
#define BMON1_NIC2_DBG_MAX_OFFSET 0x1000
|
|
#define BMON1_NIC2_DBG_SECTION 0x1000
|
|
#define mmBMON2_NIC2_DBG_BASE 0x7FFED59000ull
|
|
#define BMON2_NIC2_DBG_MAX_OFFSET 0x1000
|
|
#define BMON2_NIC2_DBG_SECTION 0x1000
|
|
#define mmBMON3_NIC2_DBG_BASE 0x7FFED5A000ull
|
|
#define BMON3_NIC2_DBG_MAX_OFFSET 0x1000
|
|
#define BMON3_NIC2_DBG_SECTION 0x1000
|
|
#define mmBMON4_NIC2_DBG_BASE 0x7FFED5B000ull
|
|
#define BMON4_NIC2_DBG_MAX_OFFSET 0x1000
|
|
#define BMON4_NIC2_DBG_SECTION 0x6000
|
|
#define mmFUNNEL_NIC2_DBG_BASE 0x7FFED61000ull
|
|
#define FUNNEL_NIC2_DBG_MAX_OFFSET 0x1000
|
|
#define FUNNEL_NIC2_DBG_SECTION 0x1F000
|
|
#define mmNIC3_ROM_TABLE_BASE 0x7FFED80000ull
|
|
#define NIC3_ROM_TABLE_MAX_OFFSET 0x1000
|
|
#define NIC3_ROM_TABLE_SECTION 0x1000
|
|
#define mmSTM_0_NIC3_DBG_BASE 0x7FFED81000ull
|
|
#define STM_0_NIC3_DBG_MAX_OFFSET 0x21000
|
|
#define STM_0_NIC3_DBG_SECTION 0x1000
|
|
#define mmCTI_0_NIC3_DBG_BASE 0x7FFED82000ull
|
|
#define CTI_0_NIC3_DBG_MAX_OFFSET 0x1000
|
|
#define CTI_0_NIC3_DBG_SECTION 0x1000
|
|
#define mmETF_0_NIC3_DBG_BASE 0x7FFED83000ull
|
|
#define ETF_0_NIC3_DBG_MAX_OFFSET 0x1000
|
|
#define ETF_0_NIC3_DBG_SECTION 0x1000
|
|
#define mmSPMU_0_NIC3_DBG_BASE 0x7FFED84000ull
|
|
#define SPMU_0_NIC3_DBG_MAX_OFFSET 0x1000
|
|
#define SPMU_0_NIC3_DBG_SECTION 0x2000
|
|
#define mmUSER_CTI_0_NIC3_DBG_BASE 0x7FFED86000ull
|
|
#define USER_CTI_0_NIC3_DBG_MAX_OFFSET 0x1000
|
|
#define USER_CTI_0_NIC3_DBG_SECTION 0xB000
|
|
#define mmSTM_1_NIC3_DBG_BASE 0x7FFED91000ull
|
|
#define STM_1_NIC3_DBG_MAX_OFFSET 0x1000
|
|
#define STM_1_NIC3_DBG_SECTION 0x1000
|
|
#define mmCTI_1_NIC3_DBG_BASE 0x7FFED92000ull
|
|
#define CTI_1_NIC3_DBG_MAX_OFFSET 0x1000
|
|
#define CTI_1_NIC3_DBG_SECTION 0x1000
|
|
#define mmETF_1_NIC3_DBG_BASE 0x7FFED93000ull
|
|
#define ETF_1_NIC3_DBG_MAX_OFFSET 0x1000
|
|
#define ETF_1_NIC3_DBG_SECTION 0x1000
|
|
#define mmSPMU_1_NIC3_DBG_BASE 0x7FFED94000ull
|
|
#define SPMU_1_NIC3_DBG_MAX_OFFSET 0x1000
|
|
#define SPMU_1_NIC3_DBG_SECTION 0x1000
|
|
#define mmBMON_CTI_NIC3_DBG_BASE 0x7FFED95000ull
|
|
#define BMON_CTI_NIC3_DBG_MAX_OFFSET 0x1000
|
|
#define BMON_CTI_NIC3_DBG_SECTION 0x1000
|
|
#define mmUSER_CTI_1_NIC3_DBG_BASE 0x7FFED96000ull
|
|
#define USER_CTI_1_NIC3_DBG_MAX_OFFSET 0x1000
|
|
#define USER_CTI_1_NIC3_DBG_SECTION 0x1000
|
|
#define mmBMON0_NIC3_DBG_BASE 0x7FFED97000ull
|
|
#define BMON0_NIC3_DBG_MAX_OFFSET 0x1000
|
|
#define BMON0_NIC3_DBG_SECTION 0x1000
|
|
#define mmBMON1_NIC3_DBG_BASE 0x7FFED98000ull
|
|
#define BMON1_NIC3_DBG_MAX_OFFSET 0x1000
|
|
#define BMON1_NIC3_DBG_SECTION 0x1000
|
|
#define mmBMON2_NIC3_DBG_BASE 0x7FFED99000ull
|
|
#define BMON2_NIC3_DBG_MAX_OFFSET 0x1000
|
|
#define BMON2_NIC3_DBG_SECTION 0x1000
|
|
#define mmBMON3_NIC3_DBG_BASE 0x7FFED9A000ull
|
|
#define BMON3_NIC3_DBG_MAX_OFFSET 0x1000
|
|
#define BMON3_NIC3_DBG_SECTION 0x1000
|
|
#define mmBMON4_NIC3_DBG_BASE 0x7FFED9B000ull
|
|
#define BMON4_NIC3_DBG_MAX_OFFSET 0x1000
|
|
#define BMON4_NIC3_DBG_SECTION 0x6000
|
|
#define mmFUNNEL_NIC3_DBG_BASE 0x7FFEDA1000ull
|
|
#define FUNNEL_NIC3_DBG_MAX_OFFSET 0x1000
|
|
#define FUNNEL_NIC3_DBG_SECTION 0x1F000
|
|
#define mmNIC4_ROM_TABLE_BASE 0x7FFEDC0000ull
|
|
#define NIC4_ROM_TABLE_MAX_OFFSET 0x1000
|
|
#define NIC4_ROM_TABLE_SECTION 0x1000
|
|
#define mmSTM_0_NIC4_DBG_BASE 0x7FFEDC1000ull
|
|
#define STM_0_NIC4_DBG_MAX_OFFSET 0x21000
|
|
#define STM_0_NIC4_DBG_SECTION 0x1000
|
|
#define mmCTI_0_NIC4_DBG_BASE 0x7FFEDC2000ull
|
|
#define CTI_0_NIC4_DBG_MAX_OFFSET 0x1000
|
|
#define CTI_0_NIC4_DBG_SECTION 0x1000
|
|
#define mmETF_0_NIC4_DBG_BASE 0x7FFEDC3000ull
|
|
#define ETF_0_NIC4_DBG_MAX_OFFSET 0x1000
|
|
#define ETF_0_NIC4_DBG_SECTION 0x1000
|
|
#define mmSPMU_0_NIC4_DBG_BASE 0x7FFEDC4000ull
|
|
#define SPMU_0_NIC4_DBG_MAX_OFFSET 0x1000
|
|
#define SPMU_0_NIC4_DBG_SECTION 0x2000
|
|
#define mmUSER_CTI_0_NIC4_DBG_BASE 0x7FFEDC6000ull
|
|
#define USER_CTI_0_NIC4_DBG_MAX_OFFSET 0x1000
|
|
#define USER_CTI_0_NIC4_DBG_SECTION 0xB000
|
|
#define mmSTM_1_NIC4_DBG_BASE 0x7FFEDD1000ull
|
|
#define STM_1_NIC4_DBG_MAX_OFFSET 0x1000
|
|
#define STM_1_NIC4_DBG_SECTION 0x1000
|
|
#define mmCTI_1_NIC4_DBG_BASE 0x7FFEDD2000ull
|
|
#define CTI_1_NIC4_DBG_MAX_OFFSET 0x1000
|
|
#define CTI_1_NIC4_DBG_SECTION 0x1000
|
|
#define mmETF_1_NIC4_DBG_BASE 0x7FFEDD3000ull
|
|
#define ETF_1_NIC4_DBG_MAX_OFFSET 0x1000
|
|
#define ETF_1_NIC4_DBG_SECTION 0x1000
|
|
#define mmSPMU_1_NIC4_DBG_BASE 0x7FFEDD4000ull
|
|
#define SPMU_1_NIC4_DBG_MAX_OFFSET 0x1000
|
|
#define SPMU_1_NIC4_DBG_SECTION 0x1000
|
|
#define mmBMON_CTI_NIC4_DBG_BASE 0x7FFEDD5000ull
|
|
#define BMON_CTI_NIC4_DBG_MAX_OFFSET 0x1000
|
|
#define BMON_CTI_NIC4_DBG_SECTION 0x1000
|
|
#define mmUSER_CTI_1_NIC4_DBG_BASE 0x7FFEDD6000ull
|
|
#define USER_CTI_1_NIC4_DBG_MAX_OFFSET 0x1000
|
|
#define USER_CTI_1_NIC4_DBG_SECTION 0x1000
|
|
#define mmBMON0_NIC4_DBG_BASE 0x7FFEDD7000ull
|
|
#define BMON0_NIC4_DBG_MAX_OFFSET 0x1000
|
|
#define BMON0_NIC4_DBG_SECTION 0x1000
|
|
#define mmBMON1_NIC4_DBG_BASE 0x7FFEDD8000ull
|
|
#define BMON1_NIC4_DBG_MAX_OFFSET 0x1000
|
|
#define BMON1_NIC4_DBG_SECTION 0x1000
|
|
#define mmBMON2_NIC4_DBG_BASE 0x7FFEDD9000ull
|
|
#define BMON2_NIC4_DBG_MAX_OFFSET 0x1000
|
|
#define BMON2_NIC4_DBG_SECTION 0x1000
|
|
#define mmBMON3_NIC4_DBG_BASE 0x7FFEDDA000ull
|
|
#define BMON3_NIC4_DBG_MAX_OFFSET 0x1000
|
|
#define BMON3_NIC4_DBG_SECTION 0x1000
|
|
#define mmBMON4_NIC4_DBG_BASE 0x7FFEDDB000ull
|
|
#define BMON4_NIC4_DBG_MAX_OFFSET 0x1000
|
|
#define BMON4_NIC4_DBG_SECTION 0x6000
|
|
#define mmFUNNEL_NIC4_DBG_BASE 0x7FFEDE1000ull
|
|
#define FUNNEL_NIC4_DBG_MAX_OFFSET 0x1000
|
|
#define FUNNEL_NIC4_DBG_SECTION 0x21F000
|
|
#define mmTPC0_ROM_TABLE_BASE 0x7FFF000000ull
|
|
#define TPC0_ROM_TABLE_MAX_OFFSET 0x1000
|
|
#define TPC0_ROM_TABLE_SECTION 0x1000
|
|
#define mmTPC0_EML_SPMU_BASE 0x7FFF001000ull
|
|
#define TPC0_EML_SPMU_MAX_OFFSET 0x1000
|
|
#define TPC0_EML_SPMU_SECTION 0x1000
|
|
#define mmTPC0_EML_ETF_BASE 0x7FFF002000ull
|
|
#define TPC0_EML_ETF_MAX_OFFSET 0x1000
|
|
#define TPC0_EML_ETF_SECTION 0x1000
|
|
#define mmTPC0_EML_STM_BASE 0x7FFF003000ull
|
|
#define TPC0_EML_STM_MAX_OFFSET 0x1000
|
|
#define TPC0_EML_STM_SECTION 0x2000
|
|
#define mmTPC0_EML_CTI_BASE 0x7FFF005000ull
|
|
#define TPC0_EML_CTI_MAX_OFFSET 0x1000
|
|
#define TPC0_EML_CTI_SECTION 0x1000
|
|
#define mmTPC0_EML_FUNNEL_BASE 0x7FFF006000ull
|
|
#define TPC0_EML_FUNNEL_MAX_OFFSET 0x1000
|
|
#define TPC0_EML_FUNNEL_SECTION 0x1000
|
|
#define mmTPC0_EML_BUSMON_0_BASE 0x7FFF007000ull
|
|
#define TPC0_EML_BUSMON_0_MAX_OFFSET 0x1000
|
|
#define TPC0_EML_BUSMON_0_SECTION 0x1000
|
|
#define mmTPC0_EML_BUSMON_1_BASE 0x7FFF008000ull
|
|
#define TPC0_EML_BUSMON_1_MAX_OFFSET 0x1000
|
|
#define TPC0_EML_BUSMON_1_SECTION 0x1000
|
|
#define mmTPC0_EML_BUSMON_2_BASE 0x7FFF009000ull
|
|
#define TPC0_EML_BUSMON_2_MAX_OFFSET 0x1000
|
|
#define TPC0_EML_BUSMON_2_SECTION 0x1000
|
|
#define mmTPC0_EML_BUSMON_3_BASE 0x7FFF00A000ull
|
|
#define TPC0_EML_BUSMON_3_MAX_OFFSET 0x1000
|
|
#define TPC0_EML_BUSMON_3_SECTION 0x36000
|
|
#define mmTPC0_EML_CFG_BASE 0x7FFF040000ull
|
|
#define TPC0_EML_CFG_MAX_OFFSET 0x3380
|
|
#define TPC0_EML_CFG_SECTION 0x1000
|
|
#define mmTPC0_EML_TPC_CFG_BASE 0x7FFF041000ull
|
|
#define TPC0_EML_TPC_CFG_MAX_OFFSET 0xE400
|
|
#define TPC0_EML_TPC_CFG_SECTION 0x4000
|
|
#define mmKERNEL_TENSOR_0_TPC0_EML_TPC_CFG_BASE 0x7FFF041400ull
|
|
#define KERNEL_TENSOR_0_TPC0_EML_TPC_CFG_MAX_OFFSET 0x3800
|
|
#define KERNEL_TENSOR_0_TPC0_EML_TPC_CFG_SECTION 0x3800
|
|
#define mmKERNEL_TENSOR_1_TPC0_EML_TPC_CFG_BASE 0x7FFF041438ull
|
|
#define KERNEL_TENSOR_1_TPC0_EML_TPC_CFG_MAX_OFFSET 0x3800
|
|
#define KERNEL_TENSOR_1_TPC0_EML_TPC_CFG_SECTION 0x3800
|
|
#define mmKERNEL_TENSOR_2_TPC0_EML_TPC_CFG_BASE 0x7FFF041470ull
|
|
#define KERNEL_TENSOR_2_TPC0_EML_TPC_CFG_MAX_OFFSET 0x3800
|
|
#define KERNEL_TENSOR_2_TPC0_EML_TPC_CFG_SECTION 0x3800
|
|
#define mmKERNEL_TENSOR_3_TPC0_EML_TPC_CFG_BASE 0x7FFF0414A8ull
|
|
#define KERNEL_TENSOR_3_TPC0_EML_TPC_CFG_MAX_OFFSET 0x3800
|
|
#define KERNEL_TENSOR_3_TPC0_EML_TPC_CFG_SECTION 0x3800
|
|
#define mmKERNEL_TENSOR_4_TPC0_EML_TPC_CFG_BASE 0x7FFF0414E0ull
|
|
#define KERNEL_TENSOR_4_TPC0_EML_TPC_CFG_MAX_OFFSET 0x3800
|
|
#define KERNEL_TENSOR_4_TPC0_EML_TPC_CFG_SECTION 0x3800
|
|
#define mmKERNEL_TENSOR_5_TPC0_EML_TPC_CFG_BASE 0x7FFF041518ull
|
|
#define KERNEL_TENSOR_5_TPC0_EML_TPC_CFG_MAX_OFFSET 0x3800
|
|
#define KERNEL_TENSOR_5_TPC0_EML_TPC_CFG_SECTION 0x3800
|
|
#define mmKERNEL_TENSOR_6_TPC0_EML_TPC_CFG_BASE 0x7FFF041550ull
|
|
#define KERNEL_TENSOR_6_TPC0_EML_TPC_CFG_MAX_OFFSET 0x3800
|
|
#define KERNEL_TENSOR_6_TPC0_EML_TPC_CFG_SECTION 0x3800
|
|
#define mmKERNEL_TENSOR_7_TPC0_EML_TPC_CFG_BASE 0x7FFF041588ull
|
|
#define KERNEL_TENSOR_7_TPC0_EML_TPC_CFG_MAX_OFFSET 0x3800
|
|
#define KERNEL_TENSOR_7_TPC0_EML_TPC_CFG_SECTION 0x3800
|
|
#define mmKERNEL_TENSOR_8_TPC0_EML_TPC_CFG_BASE 0x7FFF0415C0ull
|
|
#define KERNEL_TENSOR_8_TPC0_EML_TPC_CFG_MAX_OFFSET 0x3800
|
|
#define KERNEL_TENSOR_8_TPC0_EML_TPC_CFG_SECTION 0x3800
|
|
#define mmKERNEL_TENSOR_9_TPC0_EML_TPC_CFG_BASE 0x7FFF0415F8ull
|
|
#define KERNEL_TENSOR_9_TPC0_EML_TPC_CFG_MAX_OFFSET 0x3800
|
|
#define KERNEL_TENSOR_9_TPC0_EML_TPC_CFG_SECTION 0x3800
|
|
#define mmKERNEL_TENSOR_10_TPC0_EML_TPC_CFG_BASE 0x7FFF041630ull
|
|
#define KERNEL_TENSOR_10_TPC0_EML_TPC_CFG_MAX_OFFSET 0x3800
|
|
#define KERNEL_TENSOR_10_TPC0_EML_TPC_CFG_SECTION 0x3800
|
|
#define mmKERNEL_TENSOR_11_TPC0_EML_TPC_CFG_BASE 0x7FFF041668ull
|
|
#define KERNEL_TENSOR_11_TPC0_EML_TPC_CFG_MAX_OFFSET 0x3800
|
|
#define KERNEL_TENSOR_11_TPC0_EML_TPC_CFG_SECTION 0x3800
|
|
#define mmKERNEL_TENSOR_12_TPC0_EML_TPC_CFG_BASE 0x7FFF0416A0ull
|
|
#define KERNEL_TENSOR_12_TPC0_EML_TPC_CFG_MAX_OFFSET 0x3800
|
|
#define KERNEL_TENSOR_12_TPC0_EML_TPC_CFG_SECTION 0x3800
|
|
#define mmKERNEL_TENSOR_13_TPC0_EML_TPC_CFG_BASE 0x7FFF0416D8ull
|
|
#define KERNEL_TENSOR_13_TPC0_EML_TPC_CFG_MAX_OFFSET 0x3800
|
|
#define KERNEL_TENSOR_13_TPC0_EML_TPC_CFG_SECTION 0x3800
|
|
#define mmKERNEL_TENSOR_14_TPC0_EML_TPC_CFG_BASE 0x7FFF041710ull
|
|
#define KERNEL_TENSOR_14_TPC0_EML_TPC_CFG_MAX_OFFSET 0x3800
|
|
#define KERNEL_TENSOR_14_TPC0_EML_TPC_CFG_SECTION 0x3800
|
|
#define mmKERNEL_TENSOR_15_TPC0_EML_TPC_CFG_BASE 0x7FFF041748ull
|
|
#define KERNEL_TENSOR_15_TPC0_EML_TPC_CFG_MAX_OFFSET 0x3800
|
|
#define KERNEL_TENSOR_15_TPC0_EML_TPC_CFG_SECTION 0x3800
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#define mmKERNEL_SYNC_OBJECT_TPC0_EML_TPC_CFG_BASE 0x7FFF041780ull
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#define KERNEL_SYNC_OBJECT_TPC0_EML_TPC_CFG_MAX_OFFSET 0x8000
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#define KERNEL_SYNC_OBJECT_TPC0_EML_TPC_CFG_SECTION 0x8000
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#define mmKERNEL_TPC0_EML_TPC_CFG_BASE 0x7FFF041788ull
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#define KERNEL_TPC0_EML_TPC_CFG_MAX_OFFSET 0xB800
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#define KERNEL_TPC0_EML_TPC_CFG_SECTION 0x2780
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#define mmQM_TENSOR_0_TPC0_EML_TPC_CFG_BASE 0x7FFF041A00ull
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#define QM_TENSOR_0_TPC0_EML_TPC_CFG_MAX_OFFSET 0x3800
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#define QM_TENSOR_0_TPC0_EML_TPC_CFG_SECTION 0x3800
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#define mmQM_TENSOR_1_TPC0_EML_TPC_CFG_BASE 0x7FFF041A38ull
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#define QM_TENSOR_1_TPC0_EML_TPC_CFG_MAX_OFFSET 0x3800
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#define QM_TENSOR_1_TPC0_EML_TPC_CFG_SECTION 0x3800
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#define mmQM_TENSOR_2_TPC0_EML_TPC_CFG_BASE 0x7FFF041A70ull
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#define QM_TENSOR_2_TPC0_EML_TPC_CFG_MAX_OFFSET 0x3800
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#define QM_TENSOR_2_TPC0_EML_TPC_CFG_SECTION 0x3800
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#define mmQM_TENSOR_3_TPC0_EML_TPC_CFG_BASE 0x7FFF041AA8ull
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#define QM_TENSOR_3_TPC0_EML_TPC_CFG_MAX_OFFSET 0x3800
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#define QM_TENSOR_3_TPC0_EML_TPC_CFG_SECTION 0x3800
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#define mmQM_TENSOR_4_TPC0_EML_TPC_CFG_BASE 0x7FFF041AE0ull
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#define QM_TENSOR_4_TPC0_EML_TPC_CFG_MAX_OFFSET 0x3800
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#define QM_TENSOR_4_TPC0_EML_TPC_CFG_SECTION 0x3800
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#define mmQM_TENSOR_5_TPC0_EML_TPC_CFG_BASE 0x7FFF041B18ull
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#define QM_TENSOR_5_TPC0_EML_TPC_CFG_MAX_OFFSET 0x3800
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#define QM_TENSOR_5_TPC0_EML_TPC_CFG_SECTION 0x3800
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#define mmQM_TENSOR_6_TPC0_EML_TPC_CFG_BASE 0x7FFF041B50ull
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#define QM_TENSOR_6_TPC0_EML_TPC_CFG_MAX_OFFSET 0x3800
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#define QM_TENSOR_6_TPC0_EML_TPC_CFG_SECTION 0x3800
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#define mmQM_TENSOR_7_TPC0_EML_TPC_CFG_BASE 0x7FFF041B88ull
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#define QM_TENSOR_7_TPC0_EML_TPC_CFG_MAX_OFFSET 0x3800
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#define QM_TENSOR_7_TPC0_EML_TPC_CFG_SECTION 0x3800
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#define mmQM_TENSOR_8_TPC0_EML_TPC_CFG_BASE 0x7FFF041BC0ull
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#define QM_TENSOR_8_TPC0_EML_TPC_CFG_MAX_OFFSET 0x3800
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#define QM_TENSOR_8_TPC0_EML_TPC_CFG_SECTION 0x3800
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#define mmQM_TENSOR_9_TPC0_EML_TPC_CFG_BASE 0x7FFF041BF8ull
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#define QM_TENSOR_9_TPC0_EML_TPC_CFG_MAX_OFFSET 0x3800
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#define QM_TENSOR_9_TPC0_EML_TPC_CFG_SECTION 0x3800
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#define mmQM_TENSOR_10_TPC0_EML_TPC_CFG_BASE 0x7FFF041C30ull
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#define QM_TENSOR_10_TPC0_EML_TPC_CFG_MAX_OFFSET 0x3800
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#define QM_TENSOR_10_TPC0_EML_TPC_CFG_SECTION 0x3800
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#define mmQM_TENSOR_11_TPC0_EML_TPC_CFG_BASE 0x7FFF041C68ull
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#define QM_TENSOR_11_TPC0_EML_TPC_CFG_MAX_OFFSET 0x3800
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#define QM_TENSOR_11_TPC0_EML_TPC_CFG_SECTION 0x3800
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#define mmQM_TENSOR_12_TPC0_EML_TPC_CFG_BASE 0x7FFF041CA0ull
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#define QM_TENSOR_12_TPC0_EML_TPC_CFG_MAX_OFFSET 0x3800
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#define QM_TENSOR_12_TPC0_EML_TPC_CFG_SECTION 0x3800
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#define mmQM_TENSOR_13_TPC0_EML_TPC_CFG_BASE 0x7FFF041CD8ull
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#define QM_TENSOR_13_TPC0_EML_TPC_CFG_MAX_OFFSET 0x3800
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#define QM_TENSOR_13_TPC0_EML_TPC_CFG_SECTION 0x3800
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#define mmQM_TENSOR_14_TPC0_EML_TPC_CFG_BASE 0x7FFF041D10ull
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#define QM_TENSOR_14_TPC0_EML_TPC_CFG_MAX_OFFSET 0x3800
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#define QM_TENSOR_14_TPC0_EML_TPC_CFG_SECTION 0x3800
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#define mmQM_TENSOR_15_TPC0_EML_TPC_CFG_BASE 0x7FFF041D48ull
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#define QM_TENSOR_15_TPC0_EML_TPC_CFG_MAX_OFFSET 0x3800
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#define QM_TENSOR_15_TPC0_EML_TPC_CFG_SECTION 0x3800
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#define mmQM_SYNC_OBJECT_TPC0_EML_TPC_CFG_BASE 0x7FFF041D80ull
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#define QM_SYNC_OBJECT_TPC0_EML_TPC_CFG_MAX_OFFSET 0x8000
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#define QM_SYNC_OBJECT_TPC0_EML_TPC_CFG_SECTION 0x8000
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#define mmQM_TPC0_EML_TPC_CFG_BASE 0x7FFF041D88ull
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#define QM_TPC0_EML_TPC_CFG_MAX_OFFSET 0xB800
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#define QM_TPC0_EML_TPC_CFG_SECTION 0x2780
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#define mmTPC0_EML_TPC_QM_BASE 0x7FFF042000ull
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#define TPC0_EML_TPC_QM_MAX_OFFSET 0xD040
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#define TPC0_EML_TPC_QM_SECTION 0x1BD000
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#define mmTPC0_EML_CS_BASE 0x7FFF1FF000ull
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#define TPC0_EML_CS_MAX_OFFSET 0x1000
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#define TPC0_EML_CS_SECTION 0x1000
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#define mmTPC1_ROM_TABLE_BASE 0x7FFF200000ull
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#define TPC1_ROM_TABLE_MAX_OFFSET 0x1000
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#define TPC1_ROM_TABLE_SECTION 0x1000
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#define mmTPC1_EML_SPMU_BASE 0x7FFF201000ull
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#define TPC1_EML_SPMU_MAX_OFFSET 0x1000
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#define TPC1_EML_SPMU_SECTION 0x1000
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#define mmTPC1_EML_ETF_BASE 0x7FFF202000ull
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#define TPC1_EML_ETF_MAX_OFFSET 0x1000
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#define TPC1_EML_ETF_SECTION 0x1000
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#define mmTPC1_EML_STM_BASE 0x7FFF203000ull
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#define TPC1_EML_STM_MAX_OFFSET 0x1000
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#define TPC1_EML_STM_SECTION 0x2000
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#define mmTPC1_EML_CTI_BASE 0x7FFF205000ull
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#define TPC1_EML_CTI_MAX_OFFSET 0x1000
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#define TPC1_EML_CTI_SECTION 0x1000
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#define mmTPC1_EML_FUNNEL_BASE 0x7FFF206000ull
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#define TPC1_EML_FUNNEL_MAX_OFFSET 0x1000
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#define TPC1_EML_FUNNEL_SECTION 0x1000
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#define mmTPC1_EML_BUSMON_0_BASE 0x7FFF207000ull
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#define TPC1_EML_BUSMON_0_MAX_OFFSET 0x1000
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#define TPC1_EML_BUSMON_0_SECTION 0x1000
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#define mmTPC1_EML_BUSMON_1_BASE 0x7FFF208000ull
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#define TPC1_EML_BUSMON_1_MAX_OFFSET 0x1000
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#define TPC1_EML_BUSMON_1_SECTION 0x1000
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#define mmTPC1_EML_BUSMON_2_BASE 0x7FFF209000ull
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#define TPC1_EML_BUSMON_2_MAX_OFFSET 0x1000
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#define TPC1_EML_BUSMON_2_SECTION 0x1000
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#define mmTPC1_EML_BUSMON_3_BASE 0x7FFF20A000ull
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#define TPC1_EML_BUSMON_3_MAX_OFFSET 0x1000
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#define TPC1_EML_BUSMON_3_SECTION 0x36000
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#define mmTPC1_EML_CFG_BASE 0x7FFF240000ull
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#define TPC1_EML_CFG_MAX_OFFSET 0x3380
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#define TPC1_EML_CFG_SECTION 0x1000
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#define mmTPC1_EML_TPC_CFG_BASE 0x7FFF241000ull
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#define TPC1_EML_TPC_CFG_MAX_OFFSET 0xE400
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#define TPC1_EML_TPC_CFG_SECTION 0x4000
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#define mmKERNEL_TENSOR_0_TPC1_EML_TPC_CFG_BASE 0x7FFF241400ull
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#define KERNEL_TENSOR_0_TPC1_EML_TPC_CFG_MAX_OFFSET 0x3800
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#define KERNEL_TENSOR_0_TPC1_EML_TPC_CFG_SECTION 0x3800
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#define mmKERNEL_TENSOR_1_TPC1_EML_TPC_CFG_BASE 0x7FFF241438ull
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#define KERNEL_TENSOR_1_TPC1_EML_TPC_CFG_MAX_OFFSET 0x3800
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#define KERNEL_TENSOR_1_TPC1_EML_TPC_CFG_SECTION 0x3800
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#define mmKERNEL_TENSOR_2_TPC1_EML_TPC_CFG_BASE 0x7FFF241470ull
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#define KERNEL_TENSOR_2_TPC1_EML_TPC_CFG_MAX_OFFSET 0x3800
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#define KERNEL_TENSOR_2_TPC1_EML_TPC_CFG_SECTION 0x3800
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#define mmKERNEL_TENSOR_3_TPC1_EML_TPC_CFG_BASE 0x7FFF2414A8ull
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#define KERNEL_TENSOR_3_TPC1_EML_TPC_CFG_MAX_OFFSET 0x3800
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#define KERNEL_TENSOR_3_TPC1_EML_TPC_CFG_SECTION 0x3800
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#define mmKERNEL_TENSOR_4_TPC1_EML_TPC_CFG_BASE 0x7FFF2414E0ull
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#define KERNEL_TENSOR_4_TPC1_EML_TPC_CFG_MAX_OFFSET 0x3800
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#define KERNEL_TENSOR_4_TPC1_EML_TPC_CFG_SECTION 0x3800
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#define mmKERNEL_TENSOR_5_TPC1_EML_TPC_CFG_BASE 0x7FFF241518ull
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#define KERNEL_TENSOR_5_TPC1_EML_TPC_CFG_MAX_OFFSET 0x3800
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#define KERNEL_TENSOR_5_TPC1_EML_TPC_CFG_SECTION 0x3800
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#define mmKERNEL_TENSOR_6_TPC1_EML_TPC_CFG_BASE 0x7FFF241550ull
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#define KERNEL_TENSOR_6_TPC1_EML_TPC_CFG_MAX_OFFSET 0x3800
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#define KERNEL_TENSOR_6_TPC1_EML_TPC_CFG_SECTION 0x3800
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#define mmKERNEL_TENSOR_7_TPC1_EML_TPC_CFG_BASE 0x7FFF241588ull
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#define KERNEL_TENSOR_7_TPC1_EML_TPC_CFG_MAX_OFFSET 0x3800
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#define KERNEL_TENSOR_7_TPC1_EML_TPC_CFG_SECTION 0x3800
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#define mmKERNEL_TENSOR_8_TPC1_EML_TPC_CFG_BASE 0x7FFF2415C0ull
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#define KERNEL_TENSOR_8_TPC1_EML_TPC_CFG_MAX_OFFSET 0x3800
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#define KERNEL_TENSOR_8_TPC1_EML_TPC_CFG_SECTION 0x3800
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#define mmKERNEL_TENSOR_9_TPC1_EML_TPC_CFG_BASE 0x7FFF2415F8ull
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#define KERNEL_TENSOR_9_TPC1_EML_TPC_CFG_MAX_OFFSET 0x3800
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#define KERNEL_TENSOR_9_TPC1_EML_TPC_CFG_SECTION 0x3800
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#define mmKERNEL_TENSOR_10_TPC1_EML_TPC_CFG_BASE 0x7FFF241630ull
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#define KERNEL_TENSOR_10_TPC1_EML_TPC_CFG_MAX_OFFSET 0x3800
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#define KERNEL_TENSOR_10_TPC1_EML_TPC_CFG_SECTION 0x3800
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#define mmKERNEL_TENSOR_11_TPC1_EML_TPC_CFG_BASE 0x7FFF241668ull
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#define KERNEL_TENSOR_11_TPC1_EML_TPC_CFG_MAX_OFFSET 0x3800
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#define KERNEL_TENSOR_11_TPC1_EML_TPC_CFG_SECTION 0x3800
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#define mmKERNEL_TENSOR_12_TPC1_EML_TPC_CFG_BASE 0x7FFF2416A0ull
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#define KERNEL_TENSOR_12_TPC1_EML_TPC_CFG_MAX_OFFSET 0x3800
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#define KERNEL_TENSOR_12_TPC1_EML_TPC_CFG_SECTION 0x3800
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#define mmKERNEL_TENSOR_13_TPC1_EML_TPC_CFG_BASE 0x7FFF2416D8ull
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#define KERNEL_TENSOR_13_TPC1_EML_TPC_CFG_MAX_OFFSET 0x3800
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#define KERNEL_TENSOR_13_TPC1_EML_TPC_CFG_SECTION 0x3800
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#define mmKERNEL_TENSOR_14_TPC1_EML_TPC_CFG_BASE 0x7FFF241710ull
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#define KERNEL_TENSOR_14_TPC1_EML_TPC_CFG_MAX_OFFSET 0x3800
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#define KERNEL_TENSOR_14_TPC1_EML_TPC_CFG_SECTION 0x3800
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#define mmKERNEL_TENSOR_15_TPC1_EML_TPC_CFG_BASE 0x7FFF241748ull
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#define KERNEL_TENSOR_15_TPC1_EML_TPC_CFG_MAX_OFFSET 0x3800
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#define KERNEL_TENSOR_15_TPC1_EML_TPC_CFG_SECTION 0x3800
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#define mmKERNEL_SYNC_OBJECT_TPC1_EML_TPC_CFG_BASE 0x7FFF241780ull
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#define KERNEL_SYNC_OBJECT_TPC1_EML_TPC_CFG_MAX_OFFSET 0x8000
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#define KERNEL_SYNC_OBJECT_TPC1_EML_TPC_CFG_SECTION 0x8000
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#define mmKERNEL_TPC1_EML_TPC_CFG_BASE 0x7FFF241788ull
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#define KERNEL_TPC1_EML_TPC_CFG_MAX_OFFSET 0xB800
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#define KERNEL_TPC1_EML_TPC_CFG_SECTION 0x2780
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#define mmQM_TENSOR_0_TPC1_EML_TPC_CFG_BASE 0x7FFF241A00ull
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#define QM_TENSOR_0_TPC1_EML_TPC_CFG_MAX_OFFSET 0x3800
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#define QM_TENSOR_0_TPC1_EML_TPC_CFG_SECTION 0x3800
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#define mmQM_TENSOR_1_TPC1_EML_TPC_CFG_BASE 0x7FFF241A38ull
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#define QM_TENSOR_1_TPC1_EML_TPC_CFG_MAX_OFFSET 0x3800
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#define QM_TENSOR_1_TPC1_EML_TPC_CFG_SECTION 0x3800
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#define mmQM_TENSOR_2_TPC1_EML_TPC_CFG_BASE 0x7FFF241A70ull
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#define QM_TENSOR_2_TPC1_EML_TPC_CFG_MAX_OFFSET 0x3800
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#define QM_TENSOR_2_TPC1_EML_TPC_CFG_SECTION 0x3800
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#define mmQM_TENSOR_3_TPC1_EML_TPC_CFG_BASE 0x7FFF241AA8ull
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#define QM_TENSOR_3_TPC1_EML_TPC_CFG_MAX_OFFSET 0x3800
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#define QM_TENSOR_3_TPC1_EML_TPC_CFG_SECTION 0x3800
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#define mmQM_TENSOR_4_TPC1_EML_TPC_CFG_BASE 0x7FFF241AE0ull
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#define QM_TENSOR_4_TPC1_EML_TPC_CFG_MAX_OFFSET 0x3800
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#define QM_TENSOR_4_TPC1_EML_TPC_CFG_SECTION 0x3800
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#define mmQM_TENSOR_5_TPC1_EML_TPC_CFG_BASE 0x7FFF241B18ull
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#define QM_TENSOR_5_TPC1_EML_TPC_CFG_MAX_OFFSET 0x3800
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#define QM_TENSOR_5_TPC1_EML_TPC_CFG_SECTION 0x3800
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#define mmQM_TENSOR_6_TPC1_EML_TPC_CFG_BASE 0x7FFF241B50ull
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#define QM_TENSOR_6_TPC1_EML_TPC_CFG_MAX_OFFSET 0x3800
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#define QM_TENSOR_6_TPC1_EML_TPC_CFG_SECTION 0x3800
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#define mmQM_TENSOR_7_TPC1_EML_TPC_CFG_BASE 0x7FFF241B88ull
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#define QM_TENSOR_7_TPC1_EML_TPC_CFG_MAX_OFFSET 0x3800
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#define QM_TENSOR_7_TPC1_EML_TPC_CFG_SECTION 0x3800
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#define mmQM_TENSOR_8_TPC1_EML_TPC_CFG_BASE 0x7FFF241BC0ull
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#define QM_TENSOR_8_TPC1_EML_TPC_CFG_MAX_OFFSET 0x3800
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#define QM_TENSOR_8_TPC1_EML_TPC_CFG_SECTION 0x3800
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#define mmQM_TENSOR_9_TPC1_EML_TPC_CFG_BASE 0x7FFF241BF8ull
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#define QM_TENSOR_9_TPC1_EML_TPC_CFG_MAX_OFFSET 0x3800
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#define QM_TENSOR_9_TPC1_EML_TPC_CFG_SECTION 0x3800
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#define mmQM_TENSOR_10_TPC1_EML_TPC_CFG_BASE 0x7FFF241C30ull
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#define QM_TENSOR_10_TPC1_EML_TPC_CFG_MAX_OFFSET 0x3800
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#define QM_TENSOR_10_TPC1_EML_TPC_CFG_SECTION 0x3800
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#define mmQM_TENSOR_11_TPC1_EML_TPC_CFG_BASE 0x7FFF241C68ull
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#define QM_TENSOR_11_TPC1_EML_TPC_CFG_MAX_OFFSET 0x3800
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#define QM_TENSOR_11_TPC1_EML_TPC_CFG_SECTION 0x3800
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#define mmQM_TENSOR_12_TPC1_EML_TPC_CFG_BASE 0x7FFF241CA0ull
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#define QM_TENSOR_12_TPC1_EML_TPC_CFG_MAX_OFFSET 0x3800
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#define QM_TENSOR_12_TPC1_EML_TPC_CFG_SECTION 0x3800
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#define mmQM_TENSOR_13_TPC1_EML_TPC_CFG_BASE 0x7FFF241CD8ull
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#define QM_TENSOR_13_TPC1_EML_TPC_CFG_MAX_OFFSET 0x3800
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#define QM_TENSOR_13_TPC1_EML_TPC_CFG_SECTION 0x3800
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#define mmQM_TENSOR_14_TPC1_EML_TPC_CFG_BASE 0x7FFF241D10ull
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#define QM_TENSOR_14_TPC1_EML_TPC_CFG_MAX_OFFSET 0x3800
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#define QM_TENSOR_14_TPC1_EML_TPC_CFG_SECTION 0x3800
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#define mmQM_TENSOR_15_TPC1_EML_TPC_CFG_BASE 0x7FFF241D48ull
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#define QM_TENSOR_15_TPC1_EML_TPC_CFG_MAX_OFFSET 0x3800
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#define QM_TENSOR_15_TPC1_EML_TPC_CFG_SECTION 0x3800
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#define mmQM_SYNC_OBJECT_TPC1_EML_TPC_CFG_BASE 0x7FFF241D80ull
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#define QM_SYNC_OBJECT_TPC1_EML_TPC_CFG_MAX_OFFSET 0x8000
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#define QM_SYNC_OBJECT_TPC1_EML_TPC_CFG_SECTION 0x8000
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#define mmQM_TPC1_EML_TPC_CFG_BASE 0x7FFF241D88ull
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#define QM_TPC1_EML_TPC_CFG_MAX_OFFSET 0xB800
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#define QM_TPC1_EML_TPC_CFG_SECTION 0x2780
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#define mmTPC1_EML_TPC_QM_BASE 0x7FFF242000ull
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#define TPC1_EML_TPC_QM_MAX_OFFSET 0xD040
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#define TPC1_EML_TPC_QM_SECTION 0x1BD000
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#define mmTPC1_EML_CS_BASE 0x7FFF3FF000ull
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#define TPC1_EML_CS_MAX_OFFSET 0x1000
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#define TPC1_EML_CS_SECTION 0x1000
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#define mmTPC2_ROM_TABLE_BASE 0x7FFF400000ull
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#define TPC2_ROM_TABLE_MAX_OFFSET 0x1000
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#define TPC2_ROM_TABLE_SECTION 0x1000
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#define mmTPC2_EML_SPMU_BASE 0x7FFF401000ull
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#define TPC2_EML_SPMU_MAX_OFFSET 0x1000
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#define TPC2_EML_SPMU_SECTION 0x1000
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#define mmTPC2_EML_ETF_BASE 0x7FFF402000ull
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#define TPC2_EML_ETF_MAX_OFFSET 0x1000
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#define TPC2_EML_ETF_SECTION 0x1000
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#define mmTPC2_EML_STM_BASE 0x7FFF403000ull
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#define TPC2_EML_STM_MAX_OFFSET 0x1000
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#define TPC2_EML_STM_SECTION 0x2000
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#define mmTPC2_EML_CTI_BASE 0x7FFF405000ull
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#define TPC2_EML_CTI_MAX_OFFSET 0x1000
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#define TPC2_EML_CTI_SECTION 0x1000
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#define mmTPC2_EML_FUNNEL_BASE 0x7FFF406000ull
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#define TPC2_EML_FUNNEL_MAX_OFFSET 0x1000
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#define TPC2_EML_FUNNEL_SECTION 0x1000
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#define mmTPC2_EML_BUSMON_0_BASE 0x7FFF407000ull
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#define TPC2_EML_BUSMON_0_MAX_OFFSET 0x1000
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#define TPC2_EML_BUSMON_0_SECTION 0x1000
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#define mmTPC2_EML_BUSMON_1_BASE 0x7FFF408000ull
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#define TPC2_EML_BUSMON_1_MAX_OFFSET 0x1000
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#define TPC2_EML_BUSMON_1_SECTION 0x1000
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#define mmTPC2_EML_BUSMON_2_BASE 0x7FFF409000ull
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#define TPC2_EML_BUSMON_2_MAX_OFFSET 0x1000
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#define TPC2_EML_BUSMON_2_SECTION 0x1000
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#define mmTPC2_EML_BUSMON_3_BASE 0x7FFF40A000ull
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#define TPC2_EML_BUSMON_3_MAX_OFFSET 0x1000
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#define TPC2_EML_BUSMON_3_SECTION 0x36000
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#define mmTPC2_EML_CFG_BASE 0x7FFF440000ull
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#define TPC2_EML_CFG_MAX_OFFSET 0x3380
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#define TPC2_EML_CFG_SECTION 0x1000
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#define mmTPC2_EML_TPC_CFG_BASE 0x7FFF441000ull
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#define TPC2_EML_TPC_CFG_MAX_OFFSET 0xE400
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#define TPC2_EML_TPC_CFG_SECTION 0x4000
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#define mmKERNEL_TENSOR_0_TPC2_EML_TPC_CFG_BASE 0x7FFF441400ull
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#define KERNEL_TENSOR_0_TPC2_EML_TPC_CFG_MAX_OFFSET 0x3800
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#define KERNEL_TENSOR_0_TPC2_EML_TPC_CFG_SECTION 0x3800
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#define mmKERNEL_TENSOR_1_TPC2_EML_TPC_CFG_BASE 0x7FFF441438ull
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#define KERNEL_TENSOR_1_TPC2_EML_TPC_CFG_MAX_OFFSET 0x3800
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#define KERNEL_TENSOR_1_TPC2_EML_TPC_CFG_SECTION 0x3800
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#define mmKERNEL_TENSOR_2_TPC2_EML_TPC_CFG_BASE 0x7FFF441470ull
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#define KERNEL_TENSOR_2_TPC2_EML_TPC_CFG_MAX_OFFSET 0x3800
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#define KERNEL_TENSOR_2_TPC2_EML_TPC_CFG_SECTION 0x3800
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#define mmKERNEL_TENSOR_3_TPC2_EML_TPC_CFG_BASE 0x7FFF4414A8ull
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#define KERNEL_TENSOR_3_TPC2_EML_TPC_CFG_MAX_OFFSET 0x3800
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#define KERNEL_TENSOR_3_TPC2_EML_TPC_CFG_SECTION 0x3800
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#define mmKERNEL_TENSOR_4_TPC2_EML_TPC_CFG_BASE 0x7FFF4414E0ull
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#define KERNEL_TENSOR_4_TPC2_EML_TPC_CFG_MAX_OFFSET 0x3800
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#define KERNEL_TENSOR_4_TPC2_EML_TPC_CFG_SECTION 0x3800
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#define mmKERNEL_TENSOR_5_TPC2_EML_TPC_CFG_BASE 0x7FFF441518ull
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#define KERNEL_TENSOR_5_TPC2_EML_TPC_CFG_MAX_OFFSET 0x3800
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#define KERNEL_TENSOR_5_TPC2_EML_TPC_CFG_SECTION 0x3800
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#define mmKERNEL_TENSOR_6_TPC2_EML_TPC_CFG_BASE 0x7FFF441550ull
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#define KERNEL_TENSOR_6_TPC2_EML_TPC_CFG_MAX_OFFSET 0x3800
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#define KERNEL_TENSOR_6_TPC2_EML_TPC_CFG_SECTION 0x3800
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#define mmKERNEL_TENSOR_7_TPC2_EML_TPC_CFG_BASE 0x7FFF441588ull
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#define KERNEL_TENSOR_7_TPC2_EML_TPC_CFG_MAX_OFFSET 0x3800
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#define KERNEL_TENSOR_7_TPC2_EML_TPC_CFG_SECTION 0x3800
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#define mmKERNEL_TENSOR_8_TPC2_EML_TPC_CFG_BASE 0x7FFF4415C0ull
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#define KERNEL_TENSOR_8_TPC2_EML_TPC_CFG_MAX_OFFSET 0x3800
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#define KERNEL_TENSOR_8_TPC2_EML_TPC_CFG_SECTION 0x3800
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#define mmKERNEL_TENSOR_9_TPC2_EML_TPC_CFG_BASE 0x7FFF4415F8ull
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#define KERNEL_TENSOR_9_TPC2_EML_TPC_CFG_MAX_OFFSET 0x3800
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#define KERNEL_TENSOR_9_TPC2_EML_TPC_CFG_SECTION 0x3800
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#define mmKERNEL_TENSOR_10_TPC2_EML_TPC_CFG_BASE 0x7FFF441630ull
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#define KERNEL_TENSOR_10_TPC2_EML_TPC_CFG_MAX_OFFSET 0x3800
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#define KERNEL_TENSOR_10_TPC2_EML_TPC_CFG_SECTION 0x3800
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#define mmKERNEL_TENSOR_11_TPC2_EML_TPC_CFG_BASE 0x7FFF441668ull
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#define KERNEL_TENSOR_11_TPC2_EML_TPC_CFG_MAX_OFFSET 0x3800
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#define KERNEL_TENSOR_11_TPC2_EML_TPC_CFG_SECTION 0x3800
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#define mmKERNEL_TENSOR_12_TPC2_EML_TPC_CFG_BASE 0x7FFF4416A0ull
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#define KERNEL_TENSOR_12_TPC2_EML_TPC_CFG_MAX_OFFSET 0x3800
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#define KERNEL_TENSOR_12_TPC2_EML_TPC_CFG_SECTION 0x3800
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#define mmKERNEL_TENSOR_13_TPC2_EML_TPC_CFG_BASE 0x7FFF4416D8ull
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#define KERNEL_TENSOR_13_TPC2_EML_TPC_CFG_MAX_OFFSET 0x3800
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#define KERNEL_TENSOR_13_TPC2_EML_TPC_CFG_SECTION 0x3800
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#define mmKERNEL_TENSOR_14_TPC2_EML_TPC_CFG_BASE 0x7FFF441710ull
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#define KERNEL_TENSOR_14_TPC2_EML_TPC_CFG_MAX_OFFSET 0x3800
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#define KERNEL_TENSOR_14_TPC2_EML_TPC_CFG_SECTION 0x3800
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#define mmKERNEL_TENSOR_15_TPC2_EML_TPC_CFG_BASE 0x7FFF441748ull
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#define KERNEL_TENSOR_15_TPC2_EML_TPC_CFG_MAX_OFFSET 0x3800
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#define KERNEL_TENSOR_15_TPC2_EML_TPC_CFG_SECTION 0x3800
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#define mmKERNEL_SYNC_OBJECT_TPC2_EML_TPC_CFG_BASE 0x7FFF441780ull
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#define KERNEL_SYNC_OBJECT_TPC2_EML_TPC_CFG_MAX_OFFSET 0x8000
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#define KERNEL_SYNC_OBJECT_TPC2_EML_TPC_CFG_SECTION 0x8000
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#define mmKERNEL_TPC2_EML_TPC_CFG_BASE 0x7FFF441788ull
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#define KERNEL_TPC2_EML_TPC_CFG_MAX_OFFSET 0xB800
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#define KERNEL_TPC2_EML_TPC_CFG_SECTION 0x2780
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#define mmQM_TENSOR_0_TPC2_EML_TPC_CFG_BASE 0x7FFF441A00ull
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#define QM_TENSOR_0_TPC2_EML_TPC_CFG_MAX_OFFSET 0x3800
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#define QM_TENSOR_0_TPC2_EML_TPC_CFG_SECTION 0x3800
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#define mmQM_TENSOR_1_TPC2_EML_TPC_CFG_BASE 0x7FFF441A38ull
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#define QM_TENSOR_1_TPC2_EML_TPC_CFG_MAX_OFFSET 0x3800
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#define QM_TENSOR_1_TPC2_EML_TPC_CFG_SECTION 0x3800
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#define mmQM_TENSOR_2_TPC2_EML_TPC_CFG_BASE 0x7FFF441A70ull
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#define QM_TENSOR_2_TPC2_EML_TPC_CFG_MAX_OFFSET 0x3800
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#define QM_TENSOR_2_TPC2_EML_TPC_CFG_SECTION 0x3800
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#define mmQM_TENSOR_3_TPC2_EML_TPC_CFG_BASE 0x7FFF441AA8ull
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#define QM_TENSOR_3_TPC2_EML_TPC_CFG_MAX_OFFSET 0x3800
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#define QM_TENSOR_3_TPC2_EML_TPC_CFG_SECTION 0x3800
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#define mmQM_TENSOR_4_TPC2_EML_TPC_CFG_BASE 0x7FFF441AE0ull
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#define QM_TENSOR_4_TPC2_EML_TPC_CFG_MAX_OFFSET 0x3800
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#define QM_TENSOR_4_TPC2_EML_TPC_CFG_SECTION 0x3800
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#define mmQM_TENSOR_5_TPC2_EML_TPC_CFG_BASE 0x7FFF441B18ull
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#define QM_TENSOR_5_TPC2_EML_TPC_CFG_MAX_OFFSET 0x3800
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#define QM_TENSOR_5_TPC2_EML_TPC_CFG_SECTION 0x3800
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#define mmQM_TENSOR_6_TPC2_EML_TPC_CFG_BASE 0x7FFF441B50ull
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#define QM_TENSOR_6_TPC2_EML_TPC_CFG_MAX_OFFSET 0x3800
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#define QM_TENSOR_6_TPC2_EML_TPC_CFG_SECTION 0x3800
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#define mmQM_TENSOR_7_TPC2_EML_TPC_CFG_BASE 0x7FFF441B88ull
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#define QM_TENSOR_7_TPC2_EML_TPC_CFG_MAX_OFFSET 0x3800
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#define QM_TENSOR_7_TPC2_EML_TPC_CFG_SECTION 0x3800
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#define mmQM_TENSOR_8_TPC2_EML_TPC_CFG_BASE 0x7FFF441BC0ull
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#define QM_TENSOR_8_TPC2_EML_TPC_CFG_MAX_OFFSET 0x3800
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#define QM_TENSOR_8_TPC2_EML_TPC_CFG_SECTION 0x3800
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#define mmQM_TENSOR_9_TPC2_EML_TPC_CFG_BASE 0x7FFF441BF8ull
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#define QM_TENSOR_9_TPC2_EML_TPC_CFG_MAX_OFFSET 0x3800
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#define QM_TENSOR_9_TPC2_EML_TPC_CFG_SECTION 0x3800
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#define mmQM_TENSOR_10_TPC2_EML_TPC_CFG_BASE 0x7FFF441C30ull
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#define QM_TENSOR_10_TPC2_EML_TPC_CFG_MAX_OFFSET 0x3800
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#define QM_TENSOR_10_TPC2_EML_TPC_CFG_SECTION 0x3800
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#define mmQM_TENSOR_11_TPC2_EML_TPC_CFG_BASE 0x7FFF441C68ull
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#define QM_TENSOR_11_TPC2_EML_TPC_CFG_MAX_OFFSET 0x3800
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#define QM_TENSOR_11_TPC2_EML_TPC_CFG_SECTION 0x3800
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#define mmQM_TENSOR_12_TPC2_EML_TPC_CFG_BASE 0x7FFF441CA0ull
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#define QM_TENSOR_12_TPC2_EML_TPC_CFG_MAX_OFFSET 0x3800
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#define QM_TENSOR_12_TPC2_EML_TPC_CFG_SECTION 0x3800
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#define mmQM_TENSOR_13_TPC2_EML_TPC_CFG_BASE 0x7FFF441CD8ull
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#define QM_TENSOR_13_TPC2_EML_TPC_CFG_MAX_OFFSET 0x3800
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#define QM_TENSOR_13_TPC2_EML_TPC_CFG_SECTION 0x3800
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#define mmQM_TENSOR_14_TPC2_EML_TPC_CFG_BASE 0x7FFF441D10ull
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#define QM_TENSOR_14_TPC2_EML_TPC_CFG_MAX_OFFSET 0x3800
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#define QM_TENSOR_14_TPC2_EML_TPC_CFG_SECTION 0x3800
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#define mmQM_TENSOR_15_TPC2_EML_TPC_CFG_BASE 0x7FFF441D48ull
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#define QM_TENSOR_15_TPC2_EML_TPC_CFG_MAX_OFFSET 0x3800
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#define QM_TENSOR_15_TPC2_EML_TPC_CFG_SECTION 0x3800
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#define mmQM_SYNC_OBJECT_TPC2_EML_TPC_CFG_BASE 0x7FFF441D80ull
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#define QM_SYNC_OBJECT_TPC2_EML_TPC_CFG_MAX_OFFSET 0x8000
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#define QM_SYNC_OBJECT_TPC2_EML_TPC_CFG_SECTION 0x8000
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#define mmQM_TPC2_EML_TPC_CFG_BASE 0x7FFF441D88ull
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#define QM_TPC2_EML_TPC_CFG_MAX_OFFSET 0xB800
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#define QM_TPC2_EML_TPC_CFG_SECTION 0x2780
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#define mmTPC2_EML_TPC_QM_BASE 0x7FFF442000ull
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#define TPC2_EML_TPC_QM_MAX_OFFSET 0xD040
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#define TPC2_EML_TPC_QM_SECTION 0x1BD000
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#define mmTPC2_EML_CS_BASE 0x7FFF5FF000ull
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#define TPC2_EML_CS_MAX_OFFSET 0x1000
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#define TPC2_EML_CS_SECTION 0x1000
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#define mmTPC3_ROM_TABLE_BASE 0x7FFF600000ull
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#define TPC3_ROM_TABLE_MAX_OFFSET 0x1000
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#define TPC3_ROM_TABLE_SECTION 0x1000
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#define mmTPC3_EML_SPMU_BASE 0x7FFF601000ull
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#define TPC3_EML_SPMU_MAX_OFFSET 0x1000
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#define TPC3_EML_SPMU_SECTION 0x1000
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#define mmTPC3_EML_ETF_BASE 0x7FFF602000ull
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#define TPC3_EML_ETF_MAX_OFFSET 0x1000
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#define TPC3_EML_ETF_SECTION 0x1000
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#define mmTPC3_EML_STM_BASE 0x7FFF603000ull
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#define TPC3_EML_STM_MAX_OFFSET 0x1000
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#define TPC3_EML_STM_SECTION 0x2000
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#define mmTPC3_EML_CTI_BASE 0x7FFF605000ull
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#define TPC3_EML_CTI_MAX_OFFSET 0x1000
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#define TPC3_EML_CTI_SECTION 0x1000
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#define mmTPC3_EML_FUNNEL_BASE 0x7FFF606000ull
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#define TPC3_EML_FUNNEL_MAX_OFFSET 0x1000
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#define TPC3_EML_FUNNEL_SECTION 0x1000
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#define mmTPC3_EML_BUSMON_0_BASE 0x7FFF607000ull
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#define TPC3_EML_BUSMON_0_MAX_OFFSET 0x1000
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#define TPC3_EML_BUSMON_0_SECTION 0x1000
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#define mmTPC3_EML_BUSMON_1_BASE 0x7FFF608000ull
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#define TPC3_EML_BUSMON_1_MAX_OFFSET 0x1000
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#define TPC3_EML_BUSMON_1_SECTION 0x1000
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#define mmTPC3_EML_BUSMON_2_BASE 0x7FFF609000ull
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#define TPC3_EML_BUSMON_2_MAX_OFFSET 0x1000
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#define TPC3_EML_BUSMON_2_SECTION 0x1000
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#define mmTPC3_EML_BUSMON_3_BASE 0x7FFF60A000ull
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#define TPC3_EML_BUSMON_3_MAX_OFFSET 0x1000
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#define TPC3_EML_BUSMON_3_SECTION 0x36000
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#define mmTPC3_EML_CFG_BASE 0x7FFF640000ull
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#define TPC3_EML_CFG_MAX_OFFSET 0x3380
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#define TPC3_EML_CFG_SECTION 0x1000
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#define mmTPC3_EML_TPC_CFG_BASE 0x7FFF641000ull
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#define TPC3_EML_TPC_CFG_MAX_OFFSET 0xE400
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#define TPC3_EML_TPC_CFG_SECTION 0x4000
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#define mmKERNEL_TENSOR_0_TPC3_EML_TPC_CFG_BASE 0x7FFF641400ull
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#define KERNEL_TENSOR_0_TPC3_EML_TPC_CFG_MAX_OFFSET 0x3800
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#define KERNEL_TENSOR_0_TPC3_EML_TPC_CFG_SECTION 0x3800
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#define mmKERNEL_TENSOR_1_TPC3_EML_TPC_CFG_BASE 0x7FFF641438ull
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#define KERNEL_TENSOR_1_TPC3_EML_TPC_CFG_MAX_OFFSET 0x3800
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#define KERNEL_TENSOR_1_TPC3_EML_TPC_CFG_SECTION 0x3800
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#define mmKERNEL_TENSOR_2_TPC3_EML_TPC_CFG_BASE 0x7FFF641470ull
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#define KERNEL_TENSOR_2_TPC3_EML_TPC_CFG_MAX_OFFSET 0x3800
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#define KERNEL_TENSOR_2_TPC3_EML_TPC_CFG_SECTION 0x3800
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#define mmKERNEL_TENSOR_3_TPC3_EML_TPC_CFG_BASE 0x7FFF6414A8ull
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#define KERNEL_TENSOR_3_TPC3_EML_TPC_CFG_MAX_OFFSET 0x3800
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#define KERNEL_TENSOR_3_TPC3_EML_TPC_CFG_SECTION 0x3800
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#define mmKERNEL_TENSOR_4_TPC3_EML_TPC_CFG_BASE 0x7FFF6414E0ull
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#define KERNEL_TENSOR_4_TPC3_EML_TPC_CFG_MAX_OFFSET 0x3800
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#define KERNEL_TENSOR_4_TPC3_EML_TPC_CFG_SECTION 0x3800
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#define mmKERNEL_TENSOR_5_TPC3_EML_TPC_CFG_BASE 0x7FFF641518ull
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#define KERNEL_TENSOR_5_TPC3_EML_TPC_CFG_MAX_OFFSET 0x3800
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#define KERNEL_TENSOR_5_TPC3_EML_TPC_CFG_SECTION 0x3800
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|
#define mmKERNEL_TENSOR_6_TPC3_EML_TPC_CFG_BASE 0x7FFF641550ull
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|
#define KERNEL_TENSOR_6_TPC3_EML_TPC_CFG_MAX_OFFSET 0x3800
|
|
#define KERNEL_TENSOR_6_TPC3_EML_TPC_CFG_SECTION 0x3800
|
|
#define mmKERNEL_TENSOR_7_TPC3_EML_TPC_CFG_BASE 0x7FFF641588ull
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#define KERNEL_TENSOR_7_TPC3_EML_TPC_CFG_MAX_OFFSET 0x3800
|
|
#define KERNEL_TENSOR_7_TPC3_EML_TPC_CFG_SECTION 0x3800
|
|
#define mmKERNEL_TENSOR_8_TPC3_EML_TPC_CFG_BASE 0x7FFF6415C0ull
|
|
#define KERNEL_TENSOR_8_TPC3_EML_TPC_CFG_MAX_OFFSET 0x3800
|
|
#define KERNEL_TENSOR_8_TPC3_EML_TPC_CFG_SECTION 0x3800
|
|
#define mmKERNEL_TENSOR_9_TPC3_EML_TPC_CFG_BASE 0x7FFF6415F8ull
|
|
#define KERNEL_TENSOR_9_TPC3_EML_TPC_CFG_MAX_OFFSET 0x3800
|
|
#define KERNEL_TENSOR_9_TPC3_EML_TPC_CFG_SECTION 0x3800
|
|
#define mmKERNEL_TENSOR_10_TPC3_EML_TPC_CFG_BASE 0x7FFF641630ull
|
|
#define KERNEL_TENSOR_10_TPC3_EML_TPC_CFG_MAX_OFFSET 0x3800
|
|
#define KERNEL_TENSOR_10_TPC3_EML_TPC_CFG_SECTION 0x3800
|
|
#define mmKERNEL_TENSOR_11_TPC3_EML_TPC_CFG_BASE 0x7FFF641668ull
|
|
#define KERNEL_TENSOR_11_TPC3_EML_TPC_CFG_MAX_OFFSET 0x3800
|
|
#define KERNEL_TENSOR_11_TPC3_EML_TPC_CFG_SECTION 0x3800
|
|
#define mmKERNEL_TENSOR_12_TPC3_EML_TPC_CFG_BASE 0x7FFF6416A0ull
|
|
#define KERNEL_TENSOR_12_TPC3_EML_TPC_CFG_MAX_OFFSET 0x3800
|
|
#define KERNEL_TENSOR_12_TPC3_EML_TPC_CFG_SECTION 0x3800
|
|
#define mmKERNEL_TENSOR_13_TPC3_EML_TPC_CFG_BASE 0x7FFF6416D8ull
|
|
#define KERNEL_TENSOR_13_TPC3_EML_TPC_CFG_MAX_OFFSET 0x3800
|
|
#define KERNEL_TENSOR_13_TPC3_EML_TPC_CFG_SECTION 0x3800
|
|
#define mmKERNEL_TENSOR_14_TPC3_EML_TPC_CFG_BASE 0x7FFF641710ull
|
|
#define KERNEL_TENSOR_14_TPC3_EML_TPC_CFG_MAX_OFFSET 0x3800
|
|
#define KERNEL_TENSOR_14_TPC3_EML_TPC_CFG_SECTION 0x3800
|
|
#define mmKERNEL_TENSOR_15_TPC3_EML_TPC_CFG_BASE 0x7FFF641748ull
|
|
#define KERNEL_TENSOR_15_TPC3_EML_TPC_CFG_MAX_OFFSET 0x3800
|
|
#define KERNEL_TENSOR_15_TPC3_EML_TPC_CFG_SECTION 0x3800
|
|
#define mmKERNEL_SYNC_OBJECT_TPC3_EML_TPC_CFG_BASE 0x7FFF641780ull
|
|
#define KERNEL_SYNC_OBJECT_TPC3_EML_TPC_CFG_MAX_OFFSET 0x8000
|
|
#define KERNEL_SYNC_OBJECT_TPC3_EML_TPC_CFG_SECTION 0x8000
|
|
#define mmKERNEL_TPC3_EML_TPC_CFG_BASE 0x7FFF641788ull
|
|
#define KERNEL_TPC3_EML_TPC_CFG_MAX_OFFSET 0xB800
|
|
#define KERNEL_TPC3_EML_TPC_CFG_SECTION 0x2780
|
|
#define mmQM_TENSOR_0_TPC3_EML_TPC_CFG_BASE 0x7FFF641A00ull
|
|
#define QM_TENSOR_0_TPC3_EML_TPC_CFG_MAX_OFFSET 0x3800
|
|
#define QM_TENSOR_0_TPC3_EML_TPC_CFG_SECTION 0x3800
|
|
#define mmQM_TENSOR_1_TPC3_EML_TPC_CFG_BASE 0x7FFF641A38ull
|
|
#define QM_TENSOR_1_TPC3_EML_TPC_CFG_MAX_OFFSET 0x3800
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#define QM_TENSOR_1_TPC3_EML_TPC_CFG_SECTION 0x3800
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#define mmQM_TENSOR_2_TPC3_EML_TPC_CFG_BASE 0x7FFF641A70ull
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#define QM_TENSOR_2_TPC3_EML_TPC_CFG_MAX_OFFSET 0x3800
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#define QM_TENSOR_2_TPC3_EML_TPC_CFG_SECTION 0x3800
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#define mmQM_TENSOR_3_TPC3_EML_TPC_CFG_BASE 0x7FFF641AA8ull
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#define QM_TENSOR_3_TPC3_EML_TPC_CFG_MAX_OFFSET 0x3800
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#define QM_TENSOR_3_TPC3_EML_TPC_CFG_SECTION 0x3800
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#define mmQM_TENSOR_4_TPC3_EML_TPC_CFG_BASE 0x7FFF641AE0ull
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#define QM_TENSOR_4_TPC3_EML_TPC_CFG_MAX_OFFSET 0x3800
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#define QM_TENSOR_4_TPC3_EML_TPC_CFG_SECTION 0x3800
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#define mmQM_TENSOR_5_TPC3_EML_TPC_CFG_BASE 0x7FFF641B18ull
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#define QM_TENSOR_5_TPC3_EML_TPC_CFG_MAX_OFFSET 0x3800
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#define QM_TENSOR_5_TPC3_EML_TPC_CFG_SECTION 0x3800
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#define mmQM_TENSOR_6_TPC3_EML_TPC_CFG_BASE 0x7FFF641B50ull
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#define QM_TENSOR_6_TPC3_EML_TPC_CFG_MAX_OFFSET 0x3800
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#define QM_TENSOR_6_TPC3_EML_TPC_CFG_SECTION 0x3800
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#define mmQM_TENSOR_7_TPC3_EML_TPC_CFG_BASE 0x7FFF641B88ull
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#define QM_TENSOR_7_TPC3_EML_TPC_CFG_MAX_OFFSET 0x3800
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#define QM_TENSOR_7_TPC3_EML_TPC_CFG_SECTION 0x3800
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#define mmQM_TENSOR_8_TPC3_EML_TPC_CFG_BASE 0x7FFF641BC0ull
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#define QM_TENSOR_8_TPC3_EML_TPC_CFG_MAX_OFFSET 0x3800
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#define QM_TENSOR_8_TPC3_EML_TPC_CFG_SECTION 0x3800
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#define mmQM_TENSOR_9_TPC3_EML_TPC_CFG_BASE 0x7FFF641BF8ull
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#define QM_TENSOR_9_TPC3_EML_TPC_CFG_MAX_OFFSET 0x3800
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#define QM_TENSOR_9_TPC3_EML_TPC_CFG_SECTION 0x3800
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#define mmQM_TENSOR_10_TPC3_EML_TPC_CFG_BASE 0x7FFF641C30ull
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#define QM_TENSOR_10_TPC3_EML_TPC_CFG_MAX_OFFSET 0x3800
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#define QM_TENSOR_10_TPC3_EML_TPC_CFG_SECTION 0x3800
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#define mmQM_TENSOR_11_TPC3_EML_TPC_CFG_BASE 0x7FFF641C68ull
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#define QM_TENSOR_11_TPC3_EML_TPC_CFG_MAX_OFFSET 0x3800
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#define QM_TENSOR_11_TPC3_EML_TPC_CFG_SECTION 0x3800
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#define mmQM_TENSOR_12_TPC3_EML_TPC_CFG_BASE 0x7FFF641CA0ull
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#define QM_TENSOR_12_TPC3_EML_TPC_CFG_MAX_OFFSET 0x3800
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#define QM_TENSOR_12_TPC3_EML_TPC_CFG_SECTION 0x3800
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#define mmQM_TENSOR_13_TPC3_EML_TPC_CFG_BASE 0x7FFF641CD8ull
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#define QM_TENSOR_13_TPC3_EML_TPC_CFG_MAX_OFFSET 0x3800
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#define QM_TENSOR_13_TPC3_EML_TPC_CFG_SECTION 0x3800
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#define mmQM_TENSOR_14_TPC3_EML_TPC_CFG_BASE 0x7FFF641D10ull
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#define QM_TENSOR_14_TPC3_EML_TPC_CFG_MAX_OFFSET 0x3800
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#define QM_TENSOR_14_TPC3_EML_TPC_CFG_SECTION 0x3800
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#define mmQM_TENSOR_15_TPC3_EML_TPC_CFG_BASE 0x7FFF641D48ull
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#define QM_TENSOR_15_TPC3_EML_TPC_CFG_MAX_OFFSET 0x3800
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#define QM_TENSOR_15_TPC3_EML_TPC_CFG_SECTION 0x3800
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#define mmQM_SYNC_OBJECT_TPC3_EML_TPC_CFG_BASE 0x7FFF641D80ull
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#define QM_SYNC_OBJECT_TPC3_EML_TPC_CFG_MAX_OFFSET 0x8000
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#define QM_SYNC_OBJECT_TPC3_EML_TPC_CFG_SECTION 0x8000
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#define mmQM_TPC3_EML_TPC_CFG_BASE 0x7FFF641D88ull
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#define QM_TPC3_EML_TPC_CFG_MAX_OFFSET 0xB800
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#define QM_TPC3_EML_TPC_CFG_SECTION 0x2780
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#define mmTPC3_EML_TPC_QM_BASE 0x7FFF642000ull
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#define TPC3_EML_TPC_QM_MAX_OFFSET 0xD040
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#define TPC3_EML_TPC_QM_SECTION 0x1BD000
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#define mmTPC3_EML_CS_BASE 0x7FFF7FF000ull
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#define TPC3_EML_CS_MAX_OFFSET 0x1000
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#define TPC3_EML_CS_SECTION 0x1000
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#define mmTPC4_ROM_TABLE_BASE 0x7FFF800000ull
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#define TPC4_ROM_TABLE_MAX_OFFSET 0x1000
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#define TPC4_ROM_TABLE_SECTION 0x1000
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#define mmTPC4_EML_SPMU_BASE 0x7FFF801000ull
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#define TPC4_EML_SPMU_MAX_OFFSET 0x1000
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#define TPC4_EML_SPMU_SECTION 0x1000
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#define mmTPC4_EML_ETF_BASE 0x7FFF802000ull
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#define TPC4_EML_ETF_MAX_OFFSET 0x1000
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#define TPC4_EML_ETF_SECTION 0x1000
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#define mmTPC4_EML_STM_BASE 0x7FFF803000ull
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#define TPC4_EML_STM_MAX_OFFSET 0x1000
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#define TPC4_EML_STM_SECTION 0x2000
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#define mmTPC4_EML_CTI_BASE 0x7FFF805000ull
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#define TPC4_EML_CTI_MAX_OFFSET 0x1000
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#define TPC4_EML_CTI_SECTION 0x1000
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#define mmTPC4_EML_FUNNEL_BASE 0x7FFF806000ull
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#define TPC4_EML_FUNNEL_MAX_OFFSET 0x1000
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#define TPC4_EML_FUNNEL_SECTION 0x1000
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#define mmTPC4_EML_BUSMON_0_BASE 0x7FFF807000ull
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#define TPC4_EML_BUSMON_0_MAX_OFFSET 0x1000
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#define TPC4_EML_BUSMON_0_SECTION 0x1000
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#define mmTPC4_EML_BUSMON_1_BASE 0x7FFF808000ull
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#define TPC4_EML_BUSMON_1_MAX_OFFSET 0x1000
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#define TPC4_EML_BUSMON_1_SECTION 0x1000
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#define mmTPC4_EML_BUSMON_2_BASE 0x7FFF809000ull
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#define TPC4_EML_BUSMON_2_MAX_OFFSET 0x1000
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#define TPC4_EML_BUSMON_2_SECTION 0x1000
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#define mmTPC4_EML_BUSMON_3_BASE 0x7FFF80A000ull
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#define TPC4_EML_BUSMON_3_MAX_OFFSET 0x1000
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#define TPC4_EML_BUSMON_3_SECTION 0x36000
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#define mmTPC4_EML_CFG_BASE 0x7FFF840000ull
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#define TPC4_EML_CFG_MAX_OFFSET 0x3380
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#define TPC4_EML_CFG_SECTION 0x1000
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#define mmTPC4_EML_TPC_CFG_BASE 0x7FFF841000ull
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#define TPC4_EML_TPC_CFG_MAX_OFFSET 0xE400
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#define TPC4_EML_TPC_CFG_SECTION 0x4000
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#define mmKERNEL_TENSOR_0_TPC4_EML_TPC_CFG_BASE 0x7FFF841400ull
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#define KERNEL_TENSOR_0_TPC4_EML_TPC_CFG_MAX_OFFSET 0x3800
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#define KERNEL_TENSOR_0_TPC4_EML_TPC_CFG_SECTION 0x3800
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#define mmKERNEL_TENSOR_1_TPC4_EML_TPC_CFG_BASE 0x7FFF841438ull
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#define KERNEL_TENSOR_1_TPC4_EML_TPC_CFG_MAX_OFFSET 0x3800
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#define KERNEL_TENSOR_1_TPC4_EML_TPC_CFG_SECTION 0x3800
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#define mmKERNEL_TENSOR_2_TPC4_EML_TPC_CFG_BASE 0x7FFF841470ull
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#define KERNEL_TENSOR_2_TPC4_EML_TPC_CFG_MAX_OFFSET 0x3800
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#define KERNEL_TENSOR_2_TPC4_EML_TPC_CFG_SECTION 0x3800
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#define mmKERNEL_TENSOR_3_TPC4_EML_TPC_CFG_BASE 0x7FFF8414A8ull
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#define KERNEL_TENSOR_3_TPC4_EML_TPC_CFG_MAX_OFFSET 0x3800
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#define KERNEL_TENSOR_3_TPC4_EML_TPC_CFG_SECTION 0x3800
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#define mmKERNEL_TENSOR_4_TPC4_EML_TPC_CFG_BASE 0x7FFF8414E0ull
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#define KERNEL_TENSOR_4_TPC4_EML_TPC_CFG_MAX_OFFSET 0x3800
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#define KERNEL_TENSOR_4_TPC4_EML_TPC_CFG_SECTION 0x3800
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#define mmKERNEL_TENSOR_5_TPC4_EML_TPC_CFG_BASE 0x7FFF841518ull
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#define KERNEL_TENSOR_5_TPC4_EML_TPC_CFG_MAX_OFFSET 0x3800
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#define KERNEL_TENSOR_5_TPC4_EML_TPC_CFG_SECTION 0x3800
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#define mmKERNEL_TENSOR_6_TPC4_EML_TPC_CFG_BASE 0x7FFF841550ull
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#define KERNEL_TENSOR_6_TPC4_EML_TPC_CFG_MAX_OFFSET 0x3800
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#define KERNEL_TENSOR_6_TPC4_EML_TPC_CFG_SECTION 0x3800
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#define mmKERNEL_TENSOR_7_TPC4_EML_TPC_CFG_BASE 0x7FFF841588ull
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#define KERNEL_TENSOR_7_TPC4_EML_TPC_CFG_MAX_OFFSET 0x3800
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#define KERNEL_TENSOR_7_TPC4_EML_TPC_CFG_SECTION 0x3800
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#define mmKERNEL_TENSOR_8_TPC4_EML_TPC_CFG_BASE 0x7FFF8415C0ull
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#define KERNEL_TENSOR_8_TPC4_EML_TPC_CFG_MAX_OFFSET 0x3800
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#define KERNEL_TENSOR_8_TPC4_EML_TPC_CFG_SECTION 0x3800
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#define mmKERNEL_TENSOR_9_TPC4_EML_TPC_CFG_BASE 0x7FFF8415F8ull
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#define KERNEL_TENSOR_9_TPC4_EML_TPC_CFG_MAX_OFFSET 0x3800
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#define KERNEL_TENSOR_9_TPC4_EML_TPC_CFG_SECTION 0x3800
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#define mmKERNEL_TENSOR_10_TPC4_EML_TPC_CFG_BASE 0x7FFF841630ull
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#define KERNEL_TENSOR_10_TPC4_EML_TPC_CFG_MAX_OFFSET 0x3800
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#define KERNEL_TENSOR_10_TPC4_EML_TPC_CFG_SECTION 0x3800
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#define mmKERNEL_TENSOR_11_TPC4_EML_TPC_CFG_BASE 0x7FFF841668ull
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#define KERNEL_TENSOR_11_TPC4_EML_TPC_CFG_MAX_OFFSET 0x3800
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#define KERNEL_TENSOR_11_TPC4_EML_TPC_CFG_SECTION 0x3800
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#define mmKERNEL_TENSOR_12_TPC4_EML_TPC_CFG_BASE 0x7FFF8416A0ull
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#define KERNEL_TENSOR_12_TPC4_EML_TPC_CFG_MAX_OFFSET 0x3800
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#define KERNEL_TENSOR_12_TPC4_EML_TPC_CFG_SECTION 0x3800
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#define mmKERNEL_TENSOR_13_TPC4_EML_TPC_CFG_BASE 0x7FFF8416D8ull
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#define KERNEL_TENSOR_13_TPC4_EML_TPC_CFG_MAX_OFFSET 0x3800
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#define KERNEL_TENSOR_13_TPC4_EML_TPC_CFG_SECTION 0x3800
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#define mmKERNEL_TENSOR_14_TPC4_EML_TPC_CFG_BASE 0x7FFF841710ull
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#define KERNEL_TENSOR_14_TPC4_EML_TPC_CFG_MAX_OFFSET 0x3800
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#define KERNEL_TENSOR_14_TPC4_EML_TPC_CFG_SECTION 0x3800
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#define mmKERNEL_TENSOR_15_TPC4_EML_TPC_CFG_BASE 0x7FFF841748ull
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#define KERNEL_TENSOR_15_TPC4_EML_TPC_CFG_MAX_OFFSET 0x3800
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#define KERNEL_TENSOR_15_TPC4_EML_TPC_CFG_SECTION 0x3800
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#define mmKERNEL_SYNC_OBJECT_TPC4_EML_TPC_CFG_BASE 0x7FFF841780ull
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#define KERNEL_SYNC_OBJECT_TPC4_EML_TPC_CFG_MAX_OFFSET 0x8000
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#define KERNEL_SYNC_OBJECT_TPC4_EML_TPC_CFG_SECTION 0x8000
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#define mmKERNEL_TPC4_EML_TPC_CFG_BASE 0x7FFF841788ull
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#define KERNEL_TPC4_EML_TPC_CFG_MAX_OFFSET 0xB800
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#define KERNEL_TPC4_EML_TPC_CFG_SECTION 0x2780
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#define mmQM_TENSOR_0_TPC4_EML_TPC_CFG_BASE 0x7FFF841A00ull
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#define QM_TENSOR_0_TPC4_EML_TPC_CFG_MAX_OFFSET 0x3800
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#define QM_TENSOR_0_TPC4_EML_TPC_CFG_SECTION 0x3800
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#define mmQM_TENSOR_1_TPC4_EML_TPC_CFG_BASE 0x7FFF841A38ull
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#define QM_TENSOR_1_TPC4_EML_TPC_CFG_MAX_OFFSET 0x3800
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#define QM_TENSOR_1_TPC4_EML_TPC_CFG_SECTION 0x3800
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#define mmQM_TENSOR_2_TPC4_EML_TPC_CFG_BASE 0x7FFF841A70ull
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#define QM_TENSOR_2_TPC4_EML_TPC_CFG_MAX_OFFSET 0x3800
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#define QM_TENSOR_2_TPC4_EML_TPC_CFG_SECTION 0x3800
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#define mmQM_TENSOR_3_TPC4_EML_TPC_CFG_BASE 0x7FFF841AA8ull
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#define QM_TENSOR_3_TPC4_EML_TPC_CFG_MAX_OFFSET 0x3800
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#define QM_TENSOR_3_TPC4_EML_TPC_CFG_SECTION 0x3800
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#define mmQM_TENSOR_4_TPC4_EML_TPC_CFG_BASE 0x7FFF841AE0ull
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#define QM_TENSOR_4_TPC4_EML_TPC_CFG_MAX_OFFSET 0x3800
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#define QM_TENSOR_4_TPC4_EML_TPC_CFG_SECTION 0x3800
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#define mmQM_TENSOR_5_TPC4_EML_TPC_CFG_BASE 0x7FFF841B18ull
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#define QM_TENSOR_5_TPC4_EML_TPC_CFG_MAX_OFFSET 0x3800
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#define QM_TENSOR_5_TPC4_EML_TPC_CFG_SECTION 0x3800
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#define mmQM_TENSOR_6_TPC4_EML_TPC_CFG_BASE 0x7FFF841B50ull
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#define QM_TENSOR_6_TPC4_EML_TPC_CFG_MAX_OFFSET 0x3800
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#define QM_TENSOR_6_TPC4_EML_TPC_CFG_SECTION 0x3800
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#define mmQM_TENSOR_7_TPC4_EML_TPC_CFG_BASE 0x7FFF841B88ull
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#define QM_TENSOR_7_TPC4_EML_TPC_CFG_MAX_OFFSET 0x3800
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#define QM_TENSOR_7_TPC4_EML_TPC_CFG_SECTION 0x3800
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#define mmQM_TENSOR_8_TPC4_EML_TPC_CFG_BASE 0x7FFF841BC0ull
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#define QM_TENSOR_8_TPC4_EML_TPC_CFG_MAX_OFFSET 0x3800
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#define QM_TENSOR_8_TPC4_EML_TPC_CFG_SECTION 0x3800
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#define mmQM_TENSOR_9_TPC4_EML_TPC_CFG_BASE 0x7FFF841BF8ull
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#define QM_TENSOR_9_TPC4_EML_TPC_CFG_MAX_OFFSET 0x3800
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#define QM_TENSOR_9_TPC4_EML_TPC_CFG_SECTION 0x3800
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#define mmQM_TENSOR_10_TPC4_EML_TPC_CFG_BASE 0x7FFF841C30ull
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#define QM_TENSOR_10_TPC4_EML_TPC_CFG_MAX_OFFSET 0x3800
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#define QM_TENSOR_10_TPC4_EML_TPC_CFG_SECTION 0x3800
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#define mmQM_TENSOR_11_TPC4_EML_TPC_CFG_BASE 0x7FFF841C68ull
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#define QM_TENSOR_11_TPC4_EML_TPC_CFG_MAX_OFFSET 0x3800
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#define QM_TENSOR_11_TPC4_EML_TPC_CFG_SECTION 0x3800
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#define mmQM_TENSOR_12_TPC4_EML_TPC_CFG_BASE 0x7FFF841CA0ull
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#define QM_TENSOR_12_TPC4_EML_TPC_CFG_MAX_OFFSET 0x3800
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#define QM_TENSOR_12_TPC4_EML_TPC_CFG_SECTION 0x3800
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#define mmQM_TENSOR_13_TPC4_EML_TPC_CFG_BASE 0x7FFF841CD8ull
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#define QM_TENSOR_13_TPC4_EML_TPC_CFG_MAX_OFFSET 0x3800
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#define QM_TENSOR_13_TPC4_EML_TPC_CFG_SECTION 0x3800
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#define mmQM_TENSOR_14_TPC4_EML_TPC_CFG_BASE 0x7FFF841D10ull
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#define QM_TENSOR_14_TPC4_EML_TPC_CFG_MAX_OFFSET 0x3800
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#define QM_TENSOR_14_TPC4_EML_TPC_CFG_SECTION 0x3800
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#define mmQM_TENSOR_15_TPC4_EML_TPC_CFG_BASE 0x7FFF841D48ull
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|
#define QM_TENSOR_15_TPC4_EML_TPC_CFG_MAX_OFFSET 0x3800
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|
#define QM_TENSOR_15_TPC4_EML_TPC_CFG_SECTION 0x3800
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#define mmQM_SYNC_OBJECT_TPC4_EML_TPC_CFG_BASE 0x7FFF841D80ull
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|
#define QM_SYNC_OBJECT_TPC4_EML_TPC_CFG_MAX_OFFSET 0x8000
|
|
#define QM_SYNC_OBJECT_TPC4_EML_TPC_CFG_SECTION 0x8000
|
|
#define mmQM_TPC4_EML_TPC_CFG_BASE 0x7FFF841D88ull
|
|
#define QM_TPC4_EML_TPC_CFG_MAX_OFFSET 0xB800
|
|
#define QM_TPC4_EML_TPC_CFG_SECTION 0x2780
|
|
#define mmTPC4_EML_TPC_QM_BASE 0x7FFF842000ull
|
|
#define TPC4_EML_TPC_QM_MAX_OFFSET 0xD040
|
|
#define TPC4_EML_TPC_QM_SECTION 0x1BD000
|
|
#define mmTPC4_EML_CS_BASE 0x7FFF9FF000ull
|
|
#define TPC4_EML_CS_MAX_OFFSET 0x1000
|
|
#define TPC4_EML_CS_SECTION 0x1000
|
|
#define mmTPC5_ROM_TABLE_BASE 0x7FFFA00000ull
|
|
#define TPC5_ROM_TABLE_MAX_OFFSET 0x1000
|
|
#define TPC5_ROM_TABLE_SECTION 0x1000
|
|
#define mmTPC5_EML_SPMU_BASE 0x7FFFA01000ull
|
|
#define TPC5_EML_SPMU_MAX_OFFSET 0x1000
|
|
#define TPC5_EML_SPMU_SECTION 0x1000
|
|
#define mmTPC5_EML_ETF_BASE 0x7FFFA02000ull
|
|
#define TPC5_EML_ETF_MAX_OFFSET 0x1000
|
|
#define TPC5_EML_ETF_SECTION 0x1000
|
|
#define mmTPC5_EML_STM_BASE 0x7FFFA03000ull
|
|
#define TPC5_EML_STM_MAX_OFFSET 0x1000
|
|
#define TPC5_EML_STM_SECTION 0x2000
|
|
#define mmTPC5_EML_CTI_BASE 0x7FFFA05000ull
|
|
#define TPC5_EML_CTI_MAX_OFFSET 0x1000
|
|
#define TPC5_EML_CTI_SECTION 0x1000
|
|
#define mmTPC5_EML_FUNNEL_BASE 0x7FFFA06000ull
|
|
#define TPC5_EML_FUNNEL_MAX_OFFSET 0x1000
|
|
#define TPC5_EML_FUNNEL_SECTION 0x1000
|
|
#define mmTPC5_EML_BUSMON_0_BASE 0x7FFFA07000ull
|
|
#define TPC5_EML_BUSMON_0_MAX_OFFSET 0x1000
|
|
#define TPC5_EML_BUSMON_0_SECTION 0x1000
|
|
#define mmTPC5_EML_BUSMON_1_BASE 0x7FFFA08000ull
|
|
#define TPC5_EML_BUSMON_1_MAX_OFFSET 0x1000
|
|
#define TPC5_EML_BUSMON_1_SECTION 0x1000
|
|
#define mmTPC5_EML_BUSMON_2_BASE 0x7FFFA09000ull
|
|
#define TPC5_EML_BUSMON_2_MAX_OFFSET 0x1000
|
|
#define TPC5_EML_BUSMON_2_SECTION 0x1000
|
|
#define mmTPC5_EML_BUSMON_3_BASE 0x7FFFA0A000ull
|
|
#define TPC5_EML_BUSMON_3_MAX_OFFSET 0x1000
|
|
#define TPC5_EML_BUSMON_3_SECTION 0x36000
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#define mmTPC5_EML_CFG_BASE 0x7FFFA40000ull
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#define TPC5_EML_CFG_MAX_OFFSET 0x3380
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#define TPC5_EML_CFG_SECTION 0x1000
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#define mmTPC5_EML_TPC_CFG_BASE 0x7FFFA41000ull
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#define TPC5_EML_TPC_CFG_MAX_OFFSET 0xE400
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#define TPC5_EML_TPC_CFG_SECTION 0x4000
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#define mmKERNEL_TENSOR_0_TPC5_EML_TPC_CFG_BASE 0x7FFFA41400ull
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#define KERNEL_TENSOR_0_TPC5_EML_TPC_CFG_MAX_OFFSET 0x3800
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#define KERNEL_TENSOR_0_TPC5_EML_TPC_CFG_SECTION 0x3800
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#define mmKERNEL_TENSOR_1_TPC5_EML_TPC_CFG_BASE 0x7FFFA41438ull
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#define KERNEL_TENSOR_1_TPC5_EML_TPC_CFG_MAX_OFFSET 0x3800
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#define KERNEL_TENSOR_1_TPC5_EML_TPC_CFG_SECTION 0x3800
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#define mmKERNEL_TENSOR_2_TPC5_EML_TPC_CFG_BASE 0x7FFFA41470ull
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#define KERNEL_TENSOR_2_TPC5_EML_TPC_CFG_MAX_OFFSET 0x3800
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#define KERNEL_TENSOR_2_TPC5_EML_TPC_CFG_SECTION 0x3800
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#define mmKERNEL_TENSOR_3_TPC5_EML_TPC_CFG_BASE 0x7FFFA414A8ull
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#define KERNEL_TENSOR_3_TPC5_EML_TPC_CFG_MAX_OFFSET 0x3800
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#define KERNEL_TENSOR_3_TPC5_EML_TPC_CFG_SECTION 0x3800
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#define mmKERNEL_TENSOR_4_TPC5_EML_TPC_CFG_BASE 0x7FFFA414E0ull
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#define KERNEL_TENSOR_4_TPC5_EML_TPC_CFG_MAX_OFFSET 0x3800
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#define KERNEL_TENSOR_4_TPC5_EML_TPC_CFG_SECTION 0x3800
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#define mmKERNEL_TENSOR_5_TPC5_EML_TPC_CFG_BASE 0x7FFFA41518ull
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#define KERNEL_TENSOR_5_TPC5_EML_TPC_CFG_MAX_OFFSET 0x3800
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#define KERNEL_TENSOR_5_TPC5_EML_TPC_CFG_SECTION 0x3800
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#define mmKERNEL_TENSOR_6_TPC5_EML_TPC_CFG_BASE 0x7FFFA41550ull
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#define KERNEL_TENSOR_6_TPC5_EML_TPC_CFG_MAX_OFFSET 0x3800
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#define KERNEL_TENSOR_6_TPC5_EML_TPC_CFG_SECTION 0x3800
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#define mmKERNEL_TENSOR_7_TPC5_EML_TPC_CFG_BASE 0x7FFFA41588ull
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#define KERNEL_TENSOR_7_TPC5_EML_TPC_CFG_MAX_OFFSET 0x3800
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#define KERNEL_TENSOR_7_TPC5_EML_TPC_CFG_SECTION 0x3800
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#define mmKERNEL_TENSOR_8_TPC5_EML_TPC_CFG_BASE 0x7FFFA415C0ull
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#define KERNEL_TENSOR_8_TPC5_EML_TPC_CFG_MAX_OFFSET 0x3800
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#define KERNEL_TENSOR_8_TPC5_EML_TPC_CFG_SECTION 0x3800
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#define mmKERNEL_TENSOR_9_TPC5_EML_TPC_CFG_BASE 0x7FFFA415F8ull
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#define KERNEL_TENSOR_9_TPC5_EML_TPC_CFG_MAX_OFFSET 0x3800
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#define KERNEL_TENSOR_9_TPC5_EML_TPC_CFG_SECTION 0x3800
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#define mmKERNEL_TENSOR_10_TPC5_EML_TPC_CFG_BASE 0x7FFFA41630ull
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#define KERNEL_TENSOR_10_TPC5_EML_TPC_CFG_MAX_OFFSET 0x3800
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#define KERNEL_TENSOR_10_TPC5_EML_TPC_CFG_SECTION 0x3800
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#define mmKERNEL_TENSOR_11_TPC5_EML_TPC_CFG_BASE 0x7FFFA41668ull
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#define KERNEL_TENSOR_11_TPC5_EML_TPC_CFG_MAX_OFFSET 0x3800
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#define KERNEL_TENSOR_11_TPC5_EML_TPC_CFG_SECTION 0x3800
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#define mmKERNEL_TENSOR_12_TPC5_EML_TPC_CFG_BASE 0x7FFFA416A0ull
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#define KERNEL_TENSOR_12_TPC5_EML_TPC_CFG_MAX_OFFSET 0x3800
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#define KERNEL_TENSOR_12_TPC5_EML_TPC_CFG_SECTION 0x3800
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#define mmKERNEL_TENSOR_13_TPC5_EML_TPC_CFG_BASE 0x7FFFA416D8ull
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#define KERNEL_TENSOR_13_TPC5_EML_TPC_CFG_MAX_OFFSET 0x3800
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#define KERNEL_TENSOR_13_TPC5_EML_TPC_CFG_SECTION 0x3800
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#define mmKERNEL_TENSOR_14_TPC5_EML_TPC_CFG_BASE 0x7FFFA41710ull
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#define KERNEL_TENSOR_14_TPC5_EML_TPC_CFG_MAX_OFFSET 0x3800
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#define KERNEL_TENSOR_14_TPC5_EML_TPC_CFG_SECTION 0x3800
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#define mmKERNEL_TENSOR_15_TPC5_EML_TPC_CFG_BASE 0x7FFFA41748ull
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#define KERNEL_TENSOR_15_TPC5_EML_TPC_CFG_MAX_OFFSET 0x3800
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#define KERNEL_TENSOR_15_TPC5_EML_TPC_CFG_SECTION 0x3800
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#define mmKERNEL_SYNC_OBJECT_TPC5_EML_TPC_CFG_BASE 0x7FFFA41780ull
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#define KERNEL_SYNC_OBJECT_TPC5_EML_TPC_CFG_MAX_OFFSET 0x8000
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#define KERNEL_SYNC_OBJECT_TPC5_EML_TPC_CFG_SECTION 0x8000
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#define mmKERNEL_TPC5_EML_TPC_CFG_BASE 0x7FFFA41788ull
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#define KERNEL_TPC5_EML_TPC_CFG_MAX_OFFSET 0xB800
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#define KERNEL_TPC5_EML_TPC_CFG_SECTION 0x2780
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#define mmQM_TENSOR_0_TPC5_EML_TPC_CFG_BASE 0x7FFFA41A00ull
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#define QM_TENSOR_0_TPC5_EML_TPC_CFG_MAX_OFFSET 0x3800
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#define QM_TENSOR_0_TPC5_EML_TPC_CFG_SECTION 0x3800
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#define mmQM_TENSOR_1_TPC5_EML_TPC_CFG_BASE 0x7FFFA41A38ull
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#define QM_TENSOR_1_TPC5_EML_TPC_CFG_MAX_OFFSET 0x3800
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#define QM_TENSOR_1_TPC5_EML_TPC_CFG_SECTION 0x3800
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#define mmQM_TENSOR_2_TPC5_EML_TPC_CFG_BASE 0x7FFFA41A70ull
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#define QM_TENSOR_2_TPC5_EML_TPC_CFG_MAX_OFFSET 0x3800
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#define QM_TENSOR_2_TPC5_EML_TPC_CFG_SECTION 0x3800
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#define mmQM_TENSOR_3_TPC5_EML_TPC_CFG_BASE 0x7FFFA41AA8ull
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#define QM_TENSOR_3_TPC5_EML_TPC_CFG_MAX_OFFSET 0x3800
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#define QM_TENSOR_3_TPC5_EML_TPC_CFG_SECTION 0x3800
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#define mmQM_TENSOR_4_TPC5_EML_TPC_CFG_BASE 0x7FFFA41AE0ull
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#define QM_TENSOR_4_TPC5_EML_TPC_CFG_MAX_OFFSET 0x3800
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#define QM_TENSOR_4_TPC5_EML_TPC_CFG_SECTION 0x3800
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#define mmQM_TENSOR_5_TPC5_EML_TPC_CFG_BASE 0x7FFFA41B18ull
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#define QM_TENSOR_5_TPC5_EML_TPC_CFG_MAX_OFFSET 0x3800
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#define QM_TENSOR_5_TPC5_EML_TPC_CFG_SECTION 0x3800
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#define mmQM_TENSOR_6_TPC5_EML_TPC_CFG_BASE 0x7FFFA41B50ull
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#define QM_TENSOR_6_TPC5_EML_TPC_CFG_MAX_OFFSET 0x3800
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#define QM_TENSOR_6_TPC5_EML_TPC_CFG_SECTION 0x3800
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#define mmQM_TENSOR_7_TPC5_EML_TPC_CFG_BASE 0x7FFFA41B88ull
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#define QM_TENSOR_7_TPC5_EML_TPC_CFG_MAX_OFFSET 0x3800
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#define QM_TENSOR_7_TPC5_EML_TPC_CFG_SECTION 0x3800
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#define mmQM_TENSOR_8_TPC5_EML_TPC_CFG_BASE 0x7FFFA41BC0ull
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#define QM_TENSOR_8_TPC5_EML_TPC_CFG_MAX_OFFSET 0x3800
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#define QM_TENSOR_8_TPC5_EML_TPC_CFG_SECTION 0x3800
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#define mmQM_TENSOR_9_TPC5_EML_TPC_CFG_BASE 0x7FFFA41BF8ull
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#define QM_TENSOR_9_TPC5_EML_TPC_CFG_MAX_OFFSET 0x3800
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#define QM_TENSOR_9_TPC5_EML_TPC_CFG_SECTION 0x3800
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#define mmQM_TENSOR_10_TPC5_EML_TPC_CFG_BASE 0x7FFFA41C30ull
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#define QM_TENSOR_10_TPC5_EML_TPC_CFG_MAX_OFFSET 0x3800
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#define QM_TENSOR_10_TPC5_EML_TPC_CFG_SECTION 0x3800
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#define mmQM_TENSOR_11_TPC5_EML_TPC_CFG_BASE 0x7FFFA41C68ull
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#define QM_TENSOR_11_TPC5_EML_TPC_CFG_MAX_OFFSET 0x3800
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#define QM_TENSOR_11_TPC5_EML_TPC_CFG_SECTION 0x3800
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#define mmQM_TENSOR_12_TPC5_EML_TPC_CFG_BASE 0x7FFFA41CA0ull
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#define QM_TENSOR_12_TPC5_EML_TPC_CFG_MAX_OFFSET 0x3800
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#define QM_TENSOR_12_TPC5_EML_TPC_CFG_SECTION 0x3800
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#define mmQM_TENSOR_13_TPC5_EML_TPC_CFG_BASE 0x7FFFA41CD8ull
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#define QM_TENSOR_13_TPC5_EML_TPC_CFG_MAX_OFFSET 0x3800
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#define QM_TENSOR_13_TPC5_EML_TPC_CFG_SECTION 0x3800
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#define mmQM_TENSOR_14_TPC5_EML_TPC_CFG_BASE 0x7FFFA41D10ull
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#define QM_TENSOR_14_TPC5_EML_TPC_CFG_MAX_OFFSET 0x3800
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#define QM_TENSOR_14_TPC5_EML_TPC_CFG_SECTION 0x3800
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#define mmQM_TENSOR_15_TPC5_EML_TPC_CFG_BASE 0x7FFFA41D48ull
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#define QM_TENSOR_15_TPC5_EML_TPC_CFG_MAX_OFFSET 0x3800
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#define QM_TENSOR_15_TPC5_EML_TPC_CFG_SECTION 0x3800
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#define mmQM_SYNC_OBJECT_TPC5_EML_TPC_CFG_BASE 0x7FFFA41D80ull
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#define QM_SYNC_OBJECT_TPC5_EML_TPC_CFG_MAX_OFFSET 0x8000
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#define QM_SYNC_OBJECT_TPC5_EML_TPC_CFG_SECTION 0x8000
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#define mmQM_TPC5_EML_TPC_CFG_BASE 0x7FFFA41D88ull
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#define QM_TPC5_EML_TPC_CFG_MAX_OFFSET 0xB800
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#define QM_TPC5_EML_TPC_CFG_SECTION 0x2780
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#define mmTPC5_EML_TPC_QM_BASE 0x7FFFA42000ull
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#define TPC5_EML_TPC_QM_MAX_OFFSET 0xD040
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#define TPC5_EML_TPC_QM_SECTION 0x1BD000
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#define mmTPC5_EML_CS_BASE 0x7FFFBFF000ull
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#define TPC5_EML_CS_MAX_OFFSET 0x1000
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#define TPC5_EML_CS_SECTION 0x1000
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#define mmTPC6_ROM_TABLE_BASE 0x7FFFC00000ull
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#define TPC6_ROM_TABLE_MAX_OFFSET 0x1000
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#define TPC6_ROM_TABLE_SECTION 0x1000
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#define mmTPC6_EML_SPMU_BASE 0x7FFFC01000ull
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#define TPC6_EML_SPMU_MAX_OFFSET 0x1000
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#define TPC6_EML_SPMU_SECTION 0x1000
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#define mmTPC6_EML_ETF_BASE 0x7FFFC02000ull
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#define TPC6_EML_ETF_MAX_OFFSET 0x1000
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#define TPC6_EML_ETF_SECTION 0x1000
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#define mmTPC6_EML_STM_BASE 0x7FFFC03000ull
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#define TPC6_EML_STM_MAX_OFFSET 0x1000
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#define TPC6_EML_STM_SECTION 0x2000
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#define mmTPC6_EML_CTI_BASE 0x7FFFC05000ull
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#define TPC6_EML_CTI_MAX_OFFSET 0x1000
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#define TPC6_EML_CTI_SECTION 0x1000
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#define mmTPC6_EML_FUNNEL_BASE 0x7FFFC06000ull
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#define TPC6_EML_FUNNEL_MAX_OFFSET 0x1000
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#define TPC6_EML_FUNNEL_SECTION 0x1000
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#define mmTPC6_EML_BUSMON_0_BASE 0x7FFFC07000ull
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#define TPC6_EML_BUSMON_0_MAX_OFFSET 0x1000
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#define TPC6_EML_BUSMON_0_SECTION 0x1000
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#define mmTPC6_EML_BUSMON_1_BASE 0x7FFFC08000ull
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#define TPC6_EML_BUSMON_1_MAX_OFFSET 0x1000
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#define TPC6_EML_BUSMON_1_SECTION 0x1000
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#define mmTPC6_EML_BUSMON_2_BASE 0x7FFFC09000ull
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#define TPC6_EML_BUSMON_2_MAX_OFFSET 0x1000
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#define TPC6_EML_BUSMON_2_SECTION 0x1000
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#define mmTPC6_EML_BUSMON_3_BASE 0x7FFFC0A000ull
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#define TPC6_EML_BUSMON_3_MAX_OFFSET 0x1000
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#define TPC6_EML_BUSMON_3_SECTION 0x36000
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#define mmTPC6_EML_CFG_BASE 0x7FFFC40000ull
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#define TPC6_EML_CFG_MAX_OFFSET 0x3380
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#define TPC6_EML_CFG_SECTION 0x1000
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#define mmTPC6_EML_TPC_CFG_BASE 0x7FFFC41000ull
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#define TPC6_EML_TPC_CFG_MAX_OFFSET 0xE400
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#define TPC6_EML_TPC_CFG_SECTION 0x4000
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#define mmKERNEL_TENSOR_0_TPC6_EML_TPC_CFG_BASE 0x7FFFC41400ull
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#define KERNEL_TENSOR_0_TPC6_EML_TPC_CFG_MAX_OFFSET 0x3800
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#define KERNEL_TENSOR_0_TPC6_EML_TPC_CFG_SECTION 0x3800
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#define mmKERNEL_TENSOR_1_TPC6_EML_TPC_CFG_BASE 0x7FFFC41438ull
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#define KERNEL_TENSOR_1_TPC6_EML_TPC_CFG_MAX_OFFSET 0x3800
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#define KERNEL_TENSOR_1_TPC6_EML_TPC_CFG_SECTION 0x3800
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#define mmKERNEL_TENSOR_2_TPC6_EML_TPC_CFG_BASE 0x7FFFC41470ull
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#define KERNEL_TENSOR_2_TPC6_EML_TPC_CFG_MAX_OFFSET 0x3800
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#define KERNEL_TENSOR_2_TPC6_EML_TPC_CFG_SECTION 0x3800
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#define mmKERNEL_TENSOR_3_TPC6_EML_TPC_CFG_BASE 0x7FFFC414A8ull
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#define KERNEL_TENSOR_3_TPC6_EML_TPC_CFG_MAX_OFFSET 0x3800
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#define KERNEL_TENSOR_3_TPC6_EML_TPC_CFG_SECTION 0x3800
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#define mmKERNEL_TENSOR_4_TPC6_EML_TPC_CFG_BASE 0x7FFFC414E0ull
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#define KERNEL_TENSOR_4_TPC6_EML_TPC_CFG_MAX_OFFSET 0x3800
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#define KERNEL_TENSOR_4_TPC6_EML_TPC_CFG_SECTION 0x3800
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#define mmKERNEL_TENSOR_5_TPC6_EML_TPC_CFG_BASE 0x7FFFC41518ull
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#define KERNEL_TENSOR_5_TPC6_EML_TPC_CFG_MAX_OFFSET 0x3800
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#define KERNEL_TENSOR_5_TPC6_EML_TPC_CFG_SECTION 0x3800
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#define mmKERNEL_TENSOR_6_TPC6_EML_TPC_CFG_BASE 0x7FFFC41550ull
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#define KERNEL_TENSOR_6_TPC6_EML_TPC_CFG_MAX_OFFSET 0x3800
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#define KERNEL_TENSOR_6_TPC6_EML_TPC_CFG_SECTION 0x3800
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#define mmKERNEL_TENSOR_7_TPC6_EML_TPC_CFG_BASE 0x7FFFC41588ull
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#define KERNEL_TENSOR_7_TPC6_EML_TPC_CFG_MAX_OFFSET 0x3800
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#define KERNEL_TENSOR_7_TPC6_EML_TPC_CFG_SECTION 0x3800
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#define mmKERNEL_TENSOR_8_TPC6_EML_TPC_CFG_BASE 0x7FFFC415C0ull
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#define KERNEL_TENSOR_8_TPC6_EML_TPC_CFG_MAX_OFFSET 0x3800
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#define KERNEL_TENSOR_8_TPC6_EML_TPC_CFG_SECTION 0x3800
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#define mmKERNEL_TENSOR_9_TPC6_EML_TPC_CFG_BASE 0x7FFFC415F8ull
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#define KERNEL_TENSOR_9_TPC6_EML_TPC_CFG_MAX_OFFSET 0x3800
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#define KERNEL_TENSOR_9_TPC6_EML_TPC_CFG_SECTION 0x3800
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#define mmKERNEL_TENSOR_10_TPC6_EML_TPC_CFG_BASE 0x7FFFC41630ull
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#define KERNEL_TENSOR_10_TPC6_EML_TPC_CFG_MAX_OFFSET 0x3800
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#define KERNEL_TENSOR_10_TPC6_EML_TPC_CFG_SECTION 0x3800
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#define mmKERNEL_TENSOR_11_TPC6_EML_TPC_CFG_BASE 0x7FFFC41668ull
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#define KERNEL_TENSOR_11_TPC6_EML_TPC_CFG_MAX_OFFSET 0x3800
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#define KERNEL_TENSOR_11_TPC6_EML_TPC_CFG_SECTION 0x3800
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#define mmKERNEL_TENSOR_12_TPC6_EML_TPC_CFG_BASE 0x7FFFC416A0ull
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#define KERNEL_TENSOR_12_TPC6_EML_TPC_CFG_MAX_OFFSET 0x3800
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#define KERNEL_TENSOR_12_TPC6_EML_TPC_CFG_SECTION 0x3800
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#define mmKERNEL_TENSOR_13_TPC6_EML_TPC_CFG_BASE 0x7FFFC416D8ull
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#define KERNEL_TENSOR_13_TPC6_EML_TPC_CFG_MAX_OFFSET 0x3800
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#define KERNEL_TENSOR_13_TPC6_EML_TPC_CFG_SECTION 0x3800
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#define mmKERNEL_TENSOR_14_TPC6_EML_TPC_CFG_BASE 0x7FFFC41710ull
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#define KERNEL_TENSOR_14_TPC6_EML_TPC_CFG_MAX_OFFSET 0x3800
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#define KERNEL_TENSOR_14_TPC6_EML_TPC_CFG_SECTION 0x3800
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#define mmKERNEL_TENSOR_15_TPC6_EML_TPC_CFG_BASE 0x7FFFC41748ull
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#define KERNEL_TENSOR_15_TPC6_EML_TPC_CFG_MAX_OFFSET 0x3800
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#define KERNEL_TENSOR_15_TPC6_EML_TPC_CFG_SECTION 0x3800
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#define mmKERNEL_SYNC_OBJECT_TPC6_EML_TPC_CFG_BASE 0x7FFFC41780ull
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#define KERNEL_SYNC_OBJECT_TPC6_EML_TPC_CFG_MAX_OFFSET 0x8000
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#define KERNEL_SYNC_OBJECT_TPC6_EML_TPC_CFG_SECTION 0x8000
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#define mmKERNEL_TPC6_EML_TPC_CFG_BASE 0x7FFFC41788ull
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#define KERNEL_TPC6_EML_TPC_CFG_MAX_OFFSET 0xB800
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#define KERNEL_TPC6_EML_TPC_CFG_SECTION 0x2780
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#define mmQM_TENSOR_0_TPC6_EML_TPC_CFG_BASE 0x7FFFC41A00ull
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#define QM_TENSOR_0_TPC6_EML_TPC_CFG_MAX_OFFSET 0x3800
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#define QM_TENSOR_0_TPC6_EML_TPC_CFG_SECTION 0x3800
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#define mmQM_TENSOR_1_TPC6_EML_TPC_CFG_BASE 0x7FFFC41A38ull
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#define QM_TENSOR_1_TPC6_EML_TPC_CFG_MAX_OFFSET 0x3800
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#define QM_TENSOR_1_TPC6_EML_TPC_CFG_SECTION 0x3800
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#define mmQM_TENSOR_2_TPC6_EML_TPC_CFG_BASE 0x7FFFC41A70ull
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#define QM_TENSOR_2_TPC6_EML_TPC_CFG_MAX_OFFSET 0x3800
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#define QM_TENSOR_2_TPC6_EML_TPC_CFG_SECTION 0x3800
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#define mmQM_TENSOR_3_TPC6_EML_TPC_CFG_BASE 0x7FFFC41AA8ull
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#define QM_TENSOR_3_TPC6_EML_TPC_CFG_MAX_OFFSET 0x3800
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#define QM_TENSOR_3_TPC6_EML_TPC_CFG_SECTION 0x3800
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#define mmQM_TENSOR_4_TPC6_EML_TPC_CFG_BASE 0x7FFFC41AE0ull
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#define QM_TENSOR_4_TPC6_EML_TPC_CFG_MAX_OFFSET 0x3800
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#define QM_TENSOR_4_TPC6_EML_TPC_CFG_SECTION 0x3800
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#define mmQM_TENSOR_5_TPC6_EML_TPC_CFG_BASE 0x7FFFC41B18ull
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#define QM_TENSOR_5_TPC6_EML_TPC_CFG_MAX_OFFSET 0x3800
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#define QM_TENSOR_5_TPC6_EML_TPC_CFG_SECTION 0x3800
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#define mmQM_TENSOR_6_TPC6_EML_TPC_CFG_BASE 0x7FFFC41B50ull
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#define QM_TENSOR_6_TPC6_EML_TPC_CFG_MAX_OFFSET 0x3800
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#define QM_TENSOR_6_TPC6_EML_TPC_CFG_SECTION 0x3800
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#define mmQM_TENSOR_7_TPC6_EML_TPC_CFG_BASE 0x7FFFC41B88ull
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#define QM_TENSOR_7_TPC6_EML_TPC_CFG_MAX_OFFSET 0x3800
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#define QM_TENSOR_7_TPC6_EML_TPC_CFG_SECTION 0x3800
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#define mmQM_TENSOR_8_TPC6_EML_TPC_CFG_BASE 0x7FFFC41BC0ull
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#define QM_TENSOR_8_TPC6_EML_TPC_CFG_MAX_OFFSET 0x3800
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#define QM_TENSOR_8_TPC6_EML_TPC_CFG_SECTION 0x3800
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#define mmQM_TENSOR_9_TPC6_EML_TPC_CFG_BASE 0x7FFFC41BF8ull
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#define QM_TENSOR_9_TPC6_EML_TPC_CFG_MAX_OFFSET 0x3800
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#define QM_TENSOR_9_TPC6_EML_TPC_CFG_SECTION 0x3800
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#define mmQM_TENSOR_10_TPC6_EML_TPC_CFG_BASE 0x7FFFC41C30ull
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#define QM_TENSOR_10_TPC6_EML_TPC_CFG_MAX_OFFSET 0x3800
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#define QM_TENSOR_10_TPC6_EML_TPC_CFG_SECTION 0x3800
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#define mmQM_TENSOR_11_TPC6_EML_TPC_CFG_BASE 0x7FFFC41C68ull
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#define QM_TENSOR_11_TPC6_EML_TPC_CFG_MAX_OFFSET 0x3800
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#define QM_TENSOR_11_TPC6_EML_TPC_CFG_SECTION 0x3800
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#define mmQM_TENSOR_12_TPC6_EML_TPC_CFG_BASE 0x7FFFC41CA0ull
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#define QM_TENSOR_12_TPC6_EML_TPC_CFG_MAX_OFFSET 0x3800
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#define QM_TENSOR_12_TPC6_EML_TPC_CFG_SECTION 0x3800
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#define mmQM_TENSOR_13_TPC6_EML_TPC_CFG_BASE 0x7FFFC41CD8ull
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#define QM_TENSOR_13_TPC6_EML_TPC_CFG_MAX_OFFSET 0x3800
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#define QM_TENSOR_13_TPC6_EML_TPC_CFG_SECTION 0x3800
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#define mmQM_TENSOR_14_TPC6_EML_TPC_CFG_BASE 0x7FFFC41D10ull
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#define QM_TENSOR_14_TPC6_EML_TPC_CFG_MAX_OFFSET 0x3800
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#define QM_TENSOR_14_TPC6_EML_TPC_CFG_SECTION 0x3800
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#define mmQM_TENSOR_15_TPC6_EML_TPC_CFG_BASE 0x7FFFC41D48ull
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#define QM_TENSOR_15_TPC6_EML_TPC_CFG_MAX_OFFSET 0x3800
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#define QM_TENSOR_15_TPC6_EML_TPC_CFG_SECTION 0x3800
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#define mmQM_SYNC_OBJECT_TPC6_EML_TPC_CFG_BASE 0x7FFFC41D80ull
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#define QM_SYNC_OBJECT_TPC6_EML_TPC_CFG_MAX_OFFSET 0x8000
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#define QM_SYNC_OBJECT_TPC6_EML_TPC_CFG_SECTION 0x8000
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#define mmQM_TPC6_EML_TPC_CFG_BASE 0x7FFFC41D88ull
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#define QM_TPC6_EML_TPC_CFG_MAX_OFFSET 0xB800
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#define QM_TPC6_EML_TPC_CFG_SECTION 0x2780
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#define mmTPC6_EML_TPC_QM_BASE 0x7FFFC42000ull
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#define TPC6_EML_TPC_QM_MAX_OFFSET 0xD040
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#define TPC6_EML_TPC_QM_SECTION 0x1BD000
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#define mmTPC6_EML_CS_BASE 0x7FFFDFF000ull
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#define TPC6_EML_CS_MAX_OFFSET 0x1000
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#define TPC6_EML_CS_SECTION 0x1000
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#define mmTPC7_ROM_TABLE_BASE 0x7FFFE00000ull
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#define TPC7_ROM_TABLE_MAX_OFFSET 0x1000
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#define TPC7_ROM_TABLE_SECTION 0x1000
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#define mmTPC7_EML_SPMU_BASE 0x7FFFE01000ull
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#define TPC7_EML_SPMU_MAX_OFFSET 0x1000
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#define TPC7_EML_SPMU_SECTION 0x1000
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#define mmTPC7_EML_ETF_BASE 0x7FFFE02000ull
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#define TPC7_EML_ETF_MAX_OFFSET 0x1000
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#define TPC7_EML_ETF_SECTION 0x1000
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#define mmTPC7_EML_STM_BASE 0x7FFFE03000ull
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#define TPC7_EML_STM_MAX_OFFSET 0x1000
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#define TPC7_EML_STM_SECTION 0x2000
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#define mmTPC7_EML_CTI_BASE 0x7FFFE05000ull
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#define TPC7_EML_CTI_MAX_OFFSET 0x1000
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#define TPC7_EML_CTI_SECTION 0x1000
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#define mmTPC7_EML_FUNNEL_BASE 0x7FFFE06000ull
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#define TPC7_EML_FUNNEL_MAX_OFFSET 0x1000
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#define TPC7_EML_FUNNEL_SECTION 0x1000
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#define mmTPC7_EML_BUSMON_0_BASE 0x7FFFE07000ull
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#define TPC7_EML_BUSMON_0_MAX_OFFSET 0x1000
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#define TPC7_EML_BUSMON_0_SECTION 0x1000
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#define mmTPC7_EML_BUSMON_1_BASE 0x7FFFE08000ull
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#define TPC7_EML_BUSMON_1_MAX_OFFSET 0x1000
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#define TPC7_EML_BUSMON_1_SECTION 0x1000
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#define mmTPC7_EML_BUSMON_2_BASE 0x7FFFE09000ull
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#define TPC7_EML_BUSMON_2_MAX_OFFSET 0x1000
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#define TPC7_EML_BUSMON_2_SECTION 0x1000
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#define mmTPC7_EML_BUSMON_3_BASE 0x7FFFE0A000ull
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#define TPC7_EML_BUSMON_3_MAX_OFFSET 0x1000
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#define TPC7_EML_BUSMON_3_SECTION 0x36000
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#define mmTPC7_EML_CFG_BASE 0x7FFFE40000ull
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#define TPC7_EML_CFG_MAX_OFFSET 0x3380
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#define TPC7_EML_CFG_SECTION 0x1000
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#define mmTPC7_EML_TPC_CFG_BASE 0x7FFFE41000ull
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#define TPC7_EML_TPC_CFG_MAX_OFFSET 0xE400
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#define TPC7_EML_TPC_CFG_SECTION 0x4000
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#define mmKERNEL_TENSOR_0_TPC7_EML_TPC_CFG_BASE 0x7FFFE41400ull
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#define KERNEL_TENSOR_0_TPC7_EML_TPC_CFG_MAX_OFFSET 0x3800
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#define KERNEL_TENSOR_0_TPC7_EML_TPC_CFG_SECTION 0x3800
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#define mmKERNEL_TENSOR_1_TPC7_EML_TPC_CFG_BASE 0x7FFFE41438ull
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#define KERNEL_TENSOR_1_TPC7_EML_TPC_CFG_MAX_OFFSET 0x3800
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#define KERNEL_TENSOR_1_TPC7_EML_TPC_CFG_SECTION 0x3800
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#define mmKERNEL_TENSOR_2_TPC7_EML_TPC_CFG_BASE 0x7FFFE41470ull
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#define KERNEL_TENSOR_2_TPC7_EML_TPC_CFG_MAX_OFFSET 0x3800
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#define KERNEL_TENSOR_2_TPC7_EML_TPC_CFG_SECTION 0x3800
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#define mmKERNEL_TENSOR_3_TPC7_EML_TPC_CFG_BASE 0x7FFFE414A8ull
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#define KERNEL_TENSOR_3_TPC7_EML_TPC_CFG_MAX_OFFSET 0x3800
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#define KERNEL_TENSOR_3_TPC7_EML_TPC_CFG_SECTION 0x3800
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#define mmKERNEL_TENSOR_4_TPC7_EML_TPC_CFG_BASE 0x7FFFE414E0ull
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#define KERNEL_TENSOR_4_TPC7_EML_TPC_CFG_MAX_OFFSET 0x3800
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#define KERNEL_TENSOR_4_TPC7_EML_TPC_CFG_SECTION 0x3800
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#define mmKERNEL_TENSOR_5_TPC7_EML_TPC_CFG_BASE 0x7FFFE41518ull
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#define KERNEL_TENSOR_5_TPC7_EML_TPC_CFG_MAX_OFFSET 0x3800
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#define KERNEL_TENSOR_5_TPC7_EML_TPC_CFG_SECTION 0x3800
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#define mmKERNEL_TENSOR_6_TPC7_EML_TPC_CFG_BASE 0x7FFFE41550ull
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#define KERNEL_TENSOR_6_TPC7_EML_TPC_CFG_MAX_OFFSET 0x3800
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#define KERNEL_TENSOR_6_TPC7_EML_TPC_CFG_SECTION 0x3800
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#define mmKERNEL_TENSOR_7_TPC7_EML_TPC_CFG_BASE 0x7FFFE41588ull
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#define KERNEL_TENSOR_7_TPC7_EML_TPC_CFG_MAX_OFFSET 0x3800
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#define KERNEL_TENSOR_7_TPC7_EML_TPC_CFG_SECTION 0x3800
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#define mmKERNEL_TENSOR_8_TPC7_EML_TPC_CFG_BASE 0x7FFFE415C0ull
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#define KERNEL_TENSOR_8_TPC7_EML_TPC_CFG_MAX_OFFSET 0x3800
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#define KERNEL_TENSOR_8_TPC7_EML_TPC_CFG_SECTION 0x3800
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#define mmKERNEL_TENSOR_9_TPC7_EML_TPC_CFG_BASE 0x7FFFE415F8ull
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#define KERNEL_TENSOR_9_TPC7_EML_TPC_CFG_MAX_OFFSET 0x3800
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#define KERNEL_TENSOR_9_TPC7_EML_TPC_CFG_SECTION 0x3800
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#define mmKERNEL_TENSOR_10_TPC7_EML_TPC_CFG_BASE 0x7FFFE41630ull
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#define KERNEL_TENSOR_10_TPC7_EML_TPC_CFG_MAX_OFFSET 0x3800
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#define KERNEL_TENSOR_10_TPC7_EML_TPC_CFG_SECTION 0x3800
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#define mmKERNEL_TENSOR_11_TPC7_EML_TPC_CFG_BASE 0x7FFFE41668ull
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#define KERNEL_TENSOR_11_TPC7_EML_TPC_CFG_MAX_OFFSET 0x3800
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#define KERNEL_TENSOR_11_TPC7_EML_TPC_CFG_SECTION 0x3800
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#define mmKERNEL_TENSOR_12_TPC7_EML_TPC_CFG_BASE 0x7FFFE416A0ull
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#define KERNEL_TENSOR_12_TPC7_EML_TPC_CFG_MAX_OFFSET 0x3800
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#define KERNEL_TENSOR_12_TPC7_EML_TPC_CFG_SECTION 0x3800
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#define mmKERNEL_TENSOR_13_TPC7_EML_TPC_CFG_BASE 0x7FFFE416D8ull
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#define KERNEL_TENSOR_13_TPC7_EML_TPC_CFG_MAX_OFFSET 0x3800
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#define KERNEL_TENSOR_13_TPC7_EML_TPC_CFG_SECTION 0x3800
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#define mmKERNEL_TENSOR_14_TPC7_EML_TPC_CFG_BASE 0x7FFFE41710ull
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#define KERNEL_TENSOR_14_TPC7_EML_TPC_CFG_MAX_OFFSET 0x3800
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#define KERNEL_TENSOR_14_TPC7_EML_TPC_CFG_SECTION 0x3800
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#define mmKERNEL_TENSOR_15_TPC7_EML_TPC_CFG_BASE 0x7FFFE41748ull
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#define KERNEL_TENSOR_15_TPC7_EML_TPC_CFG_MAX_OFFSET 0x3800
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#define KERNEL_TENSOR_15_TPC7_EML_TPC_CFG_SECTION 0x3800
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#define mmKERNEL_SYNC_OBJECT_TPC7_EML_TPC_CFG_BASE 0x7FFFE41780ull
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#define KERNEL_SYNC_OBJECT_TPC7_EML_TPC_CFG_MAX_OFFSET 0x8000
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#define KERNEL_SYNC_OBJECT_TPC7_EML_TPC_CFG_SECTION 0x8000
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#define mmKERNEL_TPC7_EML_TPC_CFG_BASE 0x7FFFE41788ull
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#define KERNEL_TPC7_EML_TPC_CFG_MAX_OFFSET 0xB800
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#define KERNEL_TPC7_EML_TPC_CFG_SECTION 0x2780
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#define mmQM_TENSOR_0_TPC7_EML_TPC_CFG_BASE 0x7FFFE41A00ull
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#define QM_TENSOR_0_TPC7_EML_TPC_CFG_MAX_OFFSET 0x3800
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#define QM_TENSOR_0_TPC7_EML_TPC_CFG_SECTION 0x3800
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#define mmQM_TENSOR_1_TPC7_EML_TPC_CFG_BASE 0x7FFFE41A38ull
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#define QM_TENSOR_1_TPC7_EML_TPC_CFG_MAX_OFFSET 0x3800
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#define QM_TENSOR_1_TPC7_EML_TPC_CFG_SECTION 0x3800
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#define mmQM_TENSOR_2_TPC7_EML_TPC_CFG_BASE 0x7FFFE41A70ull
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#define QM_TENSOR_2_TPC7_EML_TPC_CFG_MAX_OFFSET 0x3800
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#define QM_TENSOR_2_TPC7_EML_TPC_CFG_SECTION 0x3800
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#define mmQM_TENSOR_3_TPC7_EML_TPC_CFG_BASE 0x7FFFE41AA8ull
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#define QM_TENSOR_3_TPC7_EML_TPC_CFG_MAX_OFFSET 0x3800
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#define QM_TENSOR_3_TPC7_EML_TPC_CFG_SECTION 0x3800
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#define mmQM_TENSOR_4_TPC7_EML_TPC_CFG_BASE 0x7FFFE41AE0ull
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#define QM_TENSOR_4_TPC7_EML_TPC_CFG_MAX_OFFSET 0x3800
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#define QM_TENSOR_4_TPC7_EML_TPC_CFG_SECTION 0x3800
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#define mmQM_TENSOR_5_TPC7_EML_TPC_CFG_BASE 0x7FFFE41B18ull
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#define QM_TENSOR_5_TPC7_EML_TPC_CFG_MAX_OFFSET 0x3800
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#define QM_TENSOR_5_TPC7_EML_TPC_CFG_SECTION 0x3800
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#define mmQM_TENSOR_6_TPC7_EML_TPC_CFG_BASE 0x7FFFE41B50ull
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#define QM_TENSOR_6_TPC7_EML_TPC_CFG_MAX_OFFSET 0x3800
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#define QM_TENSOR_6_TPC7_EML_TPC_CFG_SECTION 0x3800
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#define mmQM_TENSOR_7_TPC7_EML_TPC_CFG_BASE 0x7FFFE41B88ull
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#define QM_TENSOR_7_TPC7_EML_TPC_CFG_MAX_OFFSET 0x3800
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#define QM_TENSOR_7_TPC7_EML_TPC_CFG_SECTION 0x3800
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#define mmQM_TENSOR_8_TPC7_EML_TPC_CFG_BASE 0x7FFFE41BC0ull
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#define QM_TENSOR_8_TPC7_EML_TPC_CFG_MAX_OFFSET 0x3800
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#define QM_TENSOR_8_TPC7_EML_TPC_CFG_SECTION 0x3800
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#define mmQM_TENSOR_9_TPC7_EML_TPC_CFG_BASE 0x7FFFE41BF8ull
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#define QM_TENSOR_9_TPC7_EML_TPC_CFG_MAX_OFFSET 0x3800
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#define QM_TENSOR_9_TPC7_EML_TPC_CFG_SECTION 0x3800
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#define mmQM_TENSOR_10_TPC7_EML_TPC_CFG_BASE 0x7FFFE41C30ull
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#define QM_TENSOR_10_TPC7_EML_TPC_CFG_MAX_OFFSET 0x3800
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#define QM_TENSOR_10_TPC7_EML_TPC_CFG_SECTION 0x3800
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#define mmQM_TENSOR_11_TPC7_EML_TPC_CFG_BASE 0x7FFFE41C68ull
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#define QM_TENSOR_11_TPC7_EML_TPC_CFG_MAX_OFFSET 0x3800
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#define QM_TENSOR_11_TPC7_EML_TPC_CFG_SECTION 0x3800
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#define mmQM_TENSOR_12_TPC7_EML_TPC_CFG_BASE 0x7FFFE41CA0ull
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#define QM_TENSOR_12_TPC7_EML_TPC_CFG_MAX_OFFSET 0x3800
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#define QM_TENSOR_12_TPC7_EML_TPC_CFG_SECTION 0x3800
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#define mmQM_TENSOR_13_TPC7_EML_TPC_CFG_BASE 0x7FFFE41CD8ull
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#define QM_TENSOR_13_TPC7_EML_TPC_CFG_MAX_OFFSET 0x3800
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#define QM_TENSOR_13_TPC7_EML_TPC_CFG_SECTION 0x3800
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#define mmQM_TENSOR_14_TPC7_EML_TPC_CFG_BASE 0x7FFFE41D10ull
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#define QM_TENSOR_14_TPC7_EML_TPC_CFG_MAX_OFFSET 0x3800
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#define QM_TENSOR_14_TPC7_EML_TPC_CFG_SECTION 0x3800
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#define mmQM_TENSOR_15_TPC7_EML_TPC_CFG_BASE 0x7FFFE41D48ull
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#define QM_TENSOR_15_TPC7_EML_TPC_CFG_MAX_OFFSET 0x3800
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#define QM_TENSOR_15_TPC7_EML_TPC_CFG_SECTION 0x3800
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#define mmQM_SYNC_OBJECT_TPC7_EML_TPC_CFG_BASE 0x7FFFE41D80ull
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#define QM_SYNC_OBJECT_TPC7_EML_TPC_CFG_MAX_OFFSET 0x8000
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#define QM_SYNC_OBJECT_TPC7_EML_TPC_CFG_SECTION 0x8000
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#define mmQM_TPC7_EML_TPC_CFG_BASE 0x7FFFE41D88ull
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#define QM_TPC7_EML_TPC_CFG_MAX_OFFSET 0xB800
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#define QM_TPC7_EML_TPC_CFG_SECTION 0x2780
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#define mmTPC7_EML_TPC_QM_BASE 0x7FFFE42000ull
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#define TPC7_EML_TPC_QM_MAX_OFFSET 0xD040
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#define TPC7_EML_TPC_QM_SECTION 0x1BD000
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#define mmTPC7_EML_CS_BASE 0x7FFFFFF000ull
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#define TPC7_EML_CS_MAX_OFFSET 0x1000
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#endif /* GAUDI_BLOCKS_H_ */
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