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Currently the HMMU page tables reside in the host memory, which will cause host access from the device for every page walk. This can affect PCIe bandwidth in certain scenarios. To prevent that problem, HMMU page tables will be moved to the device memory so the miss transaction will read the hops from there instead of going to the host. Signed-off-by: Farah Kassabri <fkassabri@habana.ai> Reviewed-by: Oded Gabbay <ogabbay@kernel.org> Signed-off-by: Oded Gabbay <ogabbay@kernel.org>
60 lines
1.5 KiB
C
60 lines
1.5 KiB
C
/* SPDX-License-Identifier: GPL-2.0
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*
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* Copyright 2016-2020 HabanaLabs, Ltd.
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* All Rights Reserved.
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*
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*/
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#ifndef INCLUDE_MMU_GENERAL_H_
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#define INCLUDE_MMU_GENERAL_H_
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#define PAGE_SHIFT_4KB 12
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#define PAGE_SHIFT_64KB 16
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#define PAGE_SHIFT_2MB 21
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#define PAGE_SHIFT_16MB 24
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#define PAGE_SHIFT_64MB 26
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#define PAGE_SHIFT_1GB 30
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#define PAGE_SIZE_4KB _BITUL(PAGE_SHIFT_4KB)
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#define PAGE_SIZE_64KB _BITUL(PAGE_SHIFT_64KB)
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#define PAGE_SIZE_2MB _BITUL(PAGE_SHIFT_2MB)
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#define PAGE_SIZE_16MB _BITUL(PAGE_SHIFT_16MB)
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#define PAGE_SIZE_64MB _BITUL(PAGE_SHIFT_64MB)
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#define PAGE_SIZE_1GB _BITUL(PAGE_SHIFT_1GB)
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#define PAGE_PRESENT_MASK 0x0000000000001ull
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#define SWAP_OUT_MASK 0x0000000000004ull
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#define LAST_MASK 0x0000000000800ull
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#define FLAGS_MASK 0x0000000000FFFull
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#define MMU_ARCH_3_HOPS 3
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#define MMU_ARCH_4_HOPS 4
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#define MMU_ARCH_5_HOPS 5
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#define MMU_ARCH_6_HOPS 6
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#define HOP_PHYS_ADDR_MASK (~FLAGS_MASK)
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#define HL_PTE_SIZE sizeof(u64)
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/* definitions for HOP with 512 PTE entries */
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#define HOP_PTE_ENTRIES_512 512
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#define HOP_TABLE_SIZE_512_PTE (HOP_PTE_ENTRIES_512 * HL_PTE_SIZE)
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#define HOP0_512_PTE_TABLES_TOTAL_SIZE (HOP_TABLE_SIZE_512_PTE * MAX_ASID)
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#define MMU_HOP0_PA43_12_SHIFT 12
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#define MMU_HOP0_PA49_44_SHIFT (12 + 32)
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#define MMU_HOP0_PA63_44_SHIFT (12 + 32)
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#define MMU_CONFIG_TIMEOUT_USEC 2000 /* 2 ms */
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enum mmu_hop_num {
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MMU_HOP0,
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MMU_HOP1,
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MMU_HOP2,
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MMU_HOP3,
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MMU_HOP4,
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MMU_HOP5,
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MMU_HOP_MAX,
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};
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#endif /* INCLUDE_MMU_GENERAL_H_ */
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