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5d72e247e5
For multi-GPU systems it is difficult to tell which GPU a particular message is being printed for and that is undesirable because it complicates debugging efforts. Also, the new macros allow us to enable logging for particular parts of the codebase more selectively (since we no longer need to throw everything at DRM_DEBUG_KMS()). So, for the reasons outlined above we should switch to the new macros. We can accomplish this by using the existing DC_LOGGER code to pass around the relevant `struct drm_device` which will be fed to the new macros in logger_types.h. Also, we must get rid of all instances of the DC_LOG_.*() functions that are currently in amdgpu_dm since we don't use the DC logger there and we can simply refer to the macros directly there instead. Reviewed-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Hamza Mahfooz <hamza.mahfooz@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
100 lines
3.2 KiB
C
100 lines
3.2 KiB
C
/*
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* Copyright 2018 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: AMD
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*
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*/
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#include <linux/delay.h>
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#include "dcn20_vmid.h"
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#include "reg_helper.h"
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#define REG(reg)\
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vmid->regs->reg
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#define CTX \
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vmid->ctx
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#undef FN
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#define FN(reg_name, field_name) \
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vmid->shifts->field_name, vmid->masks->field_name
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#define DC_LOGGER \
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CTX->logger
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static void dcn20_wait_for_vmid_ready(struct dcn20_vmid *vmid)
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{
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/* According the hardware spec, we need to poll for the lowest
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* bit of PAGE_TABLE_BASE_ADDR_LO32 = 1 any time a GPUVM
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* context is updated. We can't use REG_WAIT here since we
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* don't have a seperate field to wait on.
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*
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* TODO: Confirm timeout / poll interval with hardware team
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*/
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int max_times = 10000;
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int delay_us = 5;
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int i;
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for (i = 0; i < max_times; ++i) {
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uint32_t entry_lo32;
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REG_GET(PAGE_TABLE_BASE_ADDR_LO32,
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VM_CONTEXT0_PAGE_DIRECTORY_ENTRY_LO32,
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&entry_lo32);
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if (entry_lo32 & 0x1)
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return;
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udelay(delay_us);
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}
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/* VM setup timed out */
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DC_LOG_WARNING("Timeout while waiting for GPUVM context update\n");
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ASSERT(0);
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}
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void dcn20_vmid_setup(struct dcn20_vmid *vmid, const struct dcn_vmid_page_table_config *config)
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{
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REG_SET(PAGE_TABLE_START_ADDR_HI32, 0,
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VM_CONTEXT0_START_LOGICAL_PAGE_NUMBER_HI4, (config->page_table_start_addr >> 32) & 0xF);
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REG_SET(PAGE_TABLE_START_ADDR_LO32, 0,
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VM_CONTEXT0_START_LOGICAL_PAGE_NUMBER_LO32, config->page_table_start_addr & 0xFFFFFFFF);
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REG_SET(PAGE_TABLE_END_ADDR_HI32, 0,
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VM_CONTEXT0_END_LOGICAL_PAGE_NUMBER_HI4, (config->page_table_end_addr >> 32) & 0xF);
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REG_SET(PAGE_TABLE_END_ADDR_LO32, 0,
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VM_CONTEXT0_END_LOGICAL_PAGE_NUMBER_LO32, config->page_table_end_addr & 0xFFFFFFFF);
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REG_SET_2(CNTL, 0,
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VM_CONTEXT0_PAGE_TABLE_DEPTH, config->depth,
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VM_CONTEXT0_PAGE_TABLE_BLOCK_SIZE, config->block_size);
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REG_SET(PAGE_TABLE_BASE_ADDR_HI32, 0,
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VM_CONTEXT0_PAGE_DIRECTORY_ENTRY_HI32, (config->page_table_base_addr >> 32) & 0xFFFFFFFF);
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/* Note: per hardware spec PAGE_TABLE_BASE_ADDR_LO32 must be programmed last in sequence */
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REG_SET(PAGE_TABLE_BASE_ADDR_LO32, 0,
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VM_CONTEXT0_PAGE_DIRECTORY_ENTRY_LO32, config->page_table_base_addr & 0xFFFFFFFF);
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dcn20_wait_for_vmid_ready(vmid);
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}
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