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995dedb7a4
[why] There are some registers for plane color that are skipped programming on resume. Need to add those as part of the sequence. [how] Add new function hook for programming plane color control. Reviewed-by: Duncan Ma <duncan.ma@amd.com> Acked-by: Hersen Wu <hersenxs.wu@amd.com> Signed-off-by: Sung Joon Kim <sungkim@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
76 lines
2.4 KiB
C
76 lines
2.4 KiB
C
/* SPDX-License-Identifier: MIT */
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/*
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* Copyright 2023 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: AMD
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*
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*/
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#ifndef __DC_HUBP_DCN35_H__
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#define __DC_HUBP_DCN35_H__
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#include "dcn31/dcn31_hubp.h"
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#include "dcn32/dcn32_hubp.h"
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#define HUBP_MASK_SH_LIST_DCN35(mask_sh)\
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HUBP_MASK_SH_LIST_DCN32(mask_sh),\
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HUBP_SF(HUBP0_HUBP_CLK_CNTL, HUBP_FGCG_REP_DIS, mask_sh)
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#define DCN35_HUBP_REG_FIELD_VARIABLE_LIST(type) \
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struct { \
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DCN32_HUBP_REG_FIELD_VARIABLE_LIST(type); \
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type HUBP_FGCG_REP_DIS; \
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}
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struct dcn35_hubp2_shift {
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DCN35_HUBP_REG_FIELD_VARIABLE_LIST(uint8_t);
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};
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struct dcn35_hubp2_mask {
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DCN35_HUBP_REG_FIELD_VARIABLE_LIST(uint32_t);
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};
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bool hubp35_construct(
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struct dcn20_hubp *hubp2,
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struct dc_context *ctx,
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uint32_t inst,
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const struct dcn_hubp2_registers *hubp_regs,
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const struct dcn35_hubp2_shift *hubp_shift,
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const struct dcn35_hubp2_mask *hubp_mask);
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void hubp35_set_fgcg(struct hubp *hubp, bool enable);
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void hubp35_program_pixel_format(
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struct hubp *hubp,
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enum surface_pixel_format format);
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void hubp35_program_surface_config(
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struct hubp *hubp,
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enum surface_pixel_format format,
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union dc_tiling_info *tiling_info,
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struct plane_size *plane_size,
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enum dc_rotation_angle rotation,
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struct dc_plane_dcc_param *dcc,
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bool horizontal_mirror,
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unsigned int compat_level);
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#endif /* __DC_HUBP_DCN35_H__ */
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