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78964fcac4
[Why & How] Fix incomplete copyright notice in DC code. Reviewed-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Stylon Wang <stylon.wang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
76 lines
2.8 KiB
C
76 lines
2.8 KiB
C
/* SPDX-License-Identifier: MIT */
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/*
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* Copyright 2023 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors: AMD
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*
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*/
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#ifndef __DCN35_MMHUBBUB_H
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#define __DCN35_MMHUBBUB_H
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#include "mcif_wb.h"
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#include "dcn32/dcn32_mmhubbub.h"
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#define MCIF_WB_REG_VARIABLE_LIST_DCN3_5 \
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MCIF_WB_REG_VARIABLE_LIST_DCN3_0; \
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uint32_t MMHUBBUB_CLOCK_CNTL
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#define MCIF_WB_COMMON_MASK_SH_LIST_DCN3_5(mask_sh) \
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MCIF_WB_COMMON_MASK_SH_LIST_DCN32(mask_sh), \
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SF(MMHUBBUB_CLOCK_CNTL, MMHUBBUB_TEST_CLK_SEL, mask_sh), \
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SF(MMHUBBUB_CLOCK_CNTL, DISPCLK_R_MMHUBBUB_GATE_DIS, mask_sh), \
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SF(MMHUBBUB_CLOCK_CNTL, DISPCLK_G_WBIF0_GATE_DIS, mask_sh), \
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SF(MMHUBBUB_CLOCK_CNTL, SOCCLK_G_WBIF0_GATE_DIS, mask_sh), \
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SF(MMHUBBUB_CLOCK_CNTL, MMHUBBUB_FGCG_REP_DIS, mask_sh)
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#define MCIF_WB_REG_FIELD_LIST_DCN3_5(type) \
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struct { \
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MCIF_WB_REG_FIELD_LIST_DCN3_0(type); \
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type MMHUBBUB_TEST_CLK_SEL; \
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type DISPCLK_R_MMHUBBUB_GATE_DIS; \
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type DISPCLK_G_WBIF0_GATE_DIS; \
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type SOCCLK_G_WBIF0_GATE_DIS; \
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type MMHUBBUB_FGCG_REP_DIS; \
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}
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struct dcn35_mmhubbub_registers {
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MCIF_WB_REG_VARIABLE_LIST_DCN3_5;
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};
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struct dcn35_mmhubbub_mask {
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MCIF_WB_REG_FIELD_LIST_DCN3_5(uint32_t);
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};
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struct dcn35_mmhubbub_shift {
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MCIF_WB_REG_FIELD_LIST_DCN3_5(uint8_t);
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};
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void dcn35_mmhubbub_construct(
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struct dcn30_mmhubbub *mcif_wb30, struct dc_context *ctx,
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const struct dcn35_mmhubbub_registers *mcif_wb_regs,
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const struct dcn35_mmhubbub_shift *mcif_wb_shift,
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const struct dcn35_mmhubbub_mask *mcif_wb_mask, int inst);
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void dcn35_mmhubbub_set_fgcg(struct dcn30_mmhubbub *mcif_wb30, bool enabled);
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#endif // __DCN35_MMHUBBUB_H
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