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6db31251bb
Enable only one CCS engine by default with all the compute sices allocated to it. While generating the list of UABI engines to be exposed to the user, exclude any additional CCS engines beyond the first instance. This change can be tested with igt i915_query. Fixes:d2eae8e98d("drm/i915/dg2: Drop force_probe requirement") Signed-off-by: Andi Shyti <andi.shyti@linux.intel.com> Cc: Chris Wilson <chris.p.wilson@linux.intel.com> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com> Cc: Matt Roper <matthew.d.roper@intel.com> Cc: <stable@vger.kernel.org> # v6.2+ Reviewed-by: Matt Roper <matthew.d.roper@intel.com> Acked-by: Michal Mrozek <michal.mrozek@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20240328073409.674098-4-andi.shyti@linux.intel.com (cherry picked from commit2bebae0112) Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
40 lines
865 B
C
40 lines
865 B
C
// SPDX-License-Identifier: MIT
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/*
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* Copyright © 2024 Intel Corporation
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*/
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#include "i915_drv.h"
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#include "intel_gt.h"
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#include "intel_gt_ccs_mode.h"
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#include "intel_gt_regs.h"
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void intel_gt_apply_ccs_mode(struct intel_gt *gt)
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{
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int cslice;
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u32 mode = 0;
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int first_ccs = __ffs(CCS_MASK(gt));
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if (!IS_DG2(gt->i915))
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return;
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/* Build the value for the fixed CCS load balancing */
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for (cslice = 0; cslice < I915_MAX_CCS; cslice++) {
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if (CCS_MASK(gt) & BIT(cslice))
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/*
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* If available, assign the cslice
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* to the first available engine...
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*/
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mode |= XEHP_CCS_MODE_CSLICE(cslice, first_ccs);
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else
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/*
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* ... otherwise, mark the cslice as
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* unavailable if no CCS dispatches here
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*/
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mode |= XEHP_CCS_MODE_CSLICE(cslice,
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XEHP_CCS_MODE_CSLICE_MASK);
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}
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intel_uncore_write(gt->uncore, XEHP_CCS_MODE, mode);
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}
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