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The GSC FW must be copied in a 4MB stolen memory allocation, whose GGTT
address is then passed as a parameter to a dedicated load instruction
submitted via the GSC engine.
Since the GSC load is relatively slow (up to 250ms), we perform it
asynchronously via a worker. This requires us to make sure that the
worker has stopped before suspending/unloading.
Note that we can't yet use xe_migrate_copy for the copy because it
doesn't work with stolen memory right now, so we do a memcpy from the
CPU side instead.
v2: add comment about timeout value, fix GSC status checking
before load (John)
Bspec: 65306, 65346
Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Cc: Alan Previn <alan.previn.teres.alexis@intel.com>
Cc: John Harrison <John.C.Harrison@Intel.com>
Reviewed-by: John Harrison <John.C.Harrison@Intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
34 lines
1.1 KiB
C
34 lines
1.1 KiB
C
/* SPDX-License-Identifier: MIT */
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/*
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* Copyright © 2023 Intel Corporation
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*/
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#ifndef _XE_INSTR_DEFS_H_
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#define _XE_INSTR_DEFS_H_
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#include "regs/xe_reg_defs.h"
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/*
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* The first dword of any GPU instruction is the "instruction header." Bits
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* 31:29 identify the general type of the command and determine how exact
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* opcodes and sub-opcodes will be encoded in the remaining bits.
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*/
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#define XE_INSTR_CMD_TYPE GENMASK(31, 29)
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#define XE_INSTR_MI REG_FIELD_PREP(XE_INSTR_CMD_TYPE, 0x0)
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#define XE_INSTR_GSC REG_FIELD_PREP(XE_INSTR_CMD_TYPE, 0x2)
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#define XE_INSTR_GFXPIPE REG_FIELD_PREP(XE_INSTR_CMD_TYPE, 0x3)
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/*
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* Most (but not all) instructions have a "length" field in the instruction
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* header. The value expected is the total number of dwords for the
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* instruction, minus two.
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*
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* Some instructions have length fields longer or shorter than 8 bits, but
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* those are rare. This definition can be used for the common case where
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* the length field is from 7:0.
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*/
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#define XE_INSTR_LEN_MASK GENMASK(7, 0)
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#define XE_INSTR_NUM_DW(x) REG_FIELD_PREP(XE_INSTR_LEN_MASK, (x) - 2)
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#endif
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