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Starting on MTL, the HuC is authenticated twice, once via GuC (same as with older integrated platforms) and once via GSC; the first authentication allows the HuC to be used for clear-media workloads, while the second one unlocks support for protected content. Ahead of adding the authentication flow via GSC, this patch adds support for differentiating the 2 auth steps and checking if they're complete. Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> Cc: Alan Previn <alan.previn.teres.alexis@intel.com> Cc: John Harrison <John.C.Harrison@Intel.com> Reviewed-by: Vivaik Balasubrawmanian <vivaik.balasubrawmanian@intel.com> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
42 lines
1.1 KiB
C
42 lines
1.1 KiB
C
/* SPDX-License-Identifier: MIT */
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/*
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* Copyright © 2023 Intel Corporation
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*/
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#ifndef _XE_GSC_REGS_H_
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#define _XE_GSC_REGS_H_
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#include <linux/compiler.h>
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#include <linux/types.h>
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#include "regs/xe_reg_defs.h"
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/* Definitions of GSC H/W registers, bits, etc */
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#define MTL_GSC_HECI1_BASE 0x00116000
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#define MTL_GSC_HECI2_BASE 0x00117000
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#define HECI_H_CSR(base) XE_REG((base) + 0x4)
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#define HECI_H_CSR_IE REG_BIT(0)
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#define HECI_H_CSR_IS REG_BIT(1)
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#define HECI_H_CSR_IG REG_BIT(2)
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#define HECI_H_CSR_RDY REG_BIT(3)
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#define HECI_H_CSR_RST REG_BIT(4)
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/*
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* The FWSTS register values are FW defined and can be different between
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* HECI1 and HECI2
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*/
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#define HECI_FWSTS1(base) XE_REG((base) + 0xc40)
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#define HECI1_FWSTS1_CURRENT_STATE REG_GENMASK(3, 0)
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#define HECI1_FWSTS1_CURRENT_STATE_RESET 0
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#define HECI1_FWSTS1_PROXY_STATE_NORMAL 5
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#define HECI1_FWSTS1_INIT_COMPLETE REG_BIT(9)
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#define HECI_FWSTS5(base) XE_REG((base) + 0xc68)
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#define HECI1_FWSTS5_HUC_AUTH_DONE REG_BIT(19)
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#define HECI_H_GS1(base) XE_REG((base) + 0xc4c)
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#define HECI_H_GS1_ER_PREP REG_BIT(0)
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#endif
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