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4446fcf220
Expose power1_max_interval, that is the tau corresponding to PL1, as a custom hwmon attribute. Some bit manipulation is needed because of the format of PKG_PWR_LIM_1_TIME in PACKAGE_RAPL_LIMIT register (1.x * power(2,y)) v2: Get rpm wake ref while accessing power1_max_interval v3: %s/hwmon/xe_hwmon/ v4: - As power1_max_interval is rw attr take lock in read function as well - Refine comment about val to fix point conversion (Andi) - Update kernel version and date in doc v5: Fix review comments (Anshuman) Acked-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Reviewed-by: Himal Prasad Ghimiray <himal.prasad.ghimiray@intel.com> Reviewed-by: Anshuman Gupta <anshuman.gupta@intel.com> Signed-off-by: Badal Nilawar <badal.nilawar@intel.com> Link: https://patchwork.freedesktop.org/patch/msgid/20231030115618.1382200-4-badal.nilawar@intel.com Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
45 lines
1.4 KiB
C
45 lines
1.4 KiB
C
/* SPDX-License-Identifier: MIT */
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/*
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* Copyright © 2023 Intel Corporation
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*/
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#ifndef _XE_MCHBAR_REGS_H_
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#define _XE_MCHBAR_REGS_H_
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#include "regs/xe_reg_defs.h"
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/*
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* MCHBAR mirror.
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*
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* This mirrors the MCHBAR MMIO space whose location is determined by
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* device 0 function 0's pci config register 0x44 or 0x48 and matches it in
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* every way.
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*/
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#define MCHBAR_MIRROR_BASE_SNB 0x140000
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#define PCU_CR_PACKAGE_POWER_SKU XE_REG(MCHBAR_MIRROR_BASE_SNB + 0x5930)
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#define PKG_TDP GENMASK_ULL(14, 0)
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#define PKG_MIN_PWR GENMASK_ULL(30, 16)
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#define PKG_MAX_PWR GENMASK_ULL(46, 32)
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#define PKG_MAX_WIN GENMASK_ULL(54, 48)
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#define PKG_MAX_WIN_X GENMASK_ULL(54, 53)
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#define PKG_MAX_WIN_Y GENMASK_ULL(52, 48)
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#define PCU_CR_PACKAGE_POWER_SKU_UNIT XE_REG(MCHBAR_MIRROR_BASE_SNB + 0x5938)
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#define PKG_PWR_UNIT REG_GENMASK(3, 0)
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#define PKG_ENERGY_UNIT REG_GENMASK(12, 8)
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#define PKG_TIME_UNIT REG_GENMASK(19, 16)
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#define PCU_CR_PACKAGE_ENERGY_STATUS XE_REG(MCHBAR_MIRROR_BASE_SNB + 0x593c)
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#define PCU_CR_PACKAGE_RAPL_LIMIT XE_REG(MCHBAR_MIRROR_BASE_SNB + 0x59a0)
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#define PKG_PWR_LIM_1 REG_GENMASK(14, 0)
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#define PKG_PWR_LIM_1_EN REG_BIT(15)
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#define PKG_PWR_LIM_1_TIME REG_GENMASK(23, 17)
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#define PKG_PWR_LIM_1_TIME_X REG_GENMASK(23, 22)
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#define PKG_PWR_LIM_1_TIME_Y REG_GENMASK(21, 17)
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#endif /* _XE_MCHBAR_REGS_H_ */
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