Files
linux/tools/perf/pmu-events/arch/riscv/sifive/u74/memory.json
Nikita Shubin c4f769d409 perf vendor events riscv: add Sifive U74 JSON file
This patch add the Sifive U74 JSON file.

Link: https://sifive.cdn.prismic.io/sifive/ad5577a0-9a00-45c9-a5d0-424a3d586060_u74_core_complex_manual_21G3.pdf
Derived-from-code-by: João Mário Domingos <joao.mario@tecnico.ulisboa.pt>
Signed-off-by: Nikita Shubin <n.shubin@yadro.com>
Tested-by: Kautuk Consul <kconsul@ventanamicro.com>
Acked-by: Palmer Dabbelt <palmer@rivosinc.com>
Cc: Albert Ou <aou@eecs.berkeley.edu>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Anup Patel <anup@brainfault.org>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: Jiri Olsa <jolsa@kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Namhyung Kim <namhyung@kernel.org>
Cc: Palmer Dabbelt <palmer@dabbelt.com>
Cc: Paul Walmsley <paul.walmsley@sifive.com>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: linux-riscv@lists.infradead.org
Cc: linux@yadro.com
Link: https://lore.kernel.org/r/20220815132251.25702-4-nikita.shubin@maquefel.me
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
2022-10-27 16:37:25 -03:00

32 lines
742 B
JSON

[
{
"EventName": "ICACHE_RETIRED",
"EventCode": "0x0000102",
"BriefDescription": "Instruction cache miss"
},
{
"EventName": "DCACHE_MISS_MMIO_ACCESSES",
"EventCode": "0x0000202",
"BriefDescription": "Data cache miss or memory-mapped I/O access"
},
{
"EventName": "DCACHE_WRITEBACK",
"EventCode": "0x0000402",
"BriefDescription": "Data cache write-back"
},
{
"EventName": "INST_TLB_MISS",
"EventCode": "0x0000802",
"BriefDescription": "Instruction TLB miss"
},
{
"EventName": "DATA_TLB_MISS",
"EventCode": "0x0001002",
"BriefDescription": "Data TLB miss"
},
{
"EventName": "UTLB_MISS",
"EventCode": "0x0002002",
"BriefDescription": "UTLB miss"
}
]