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35267cea90
In future to add support for sys events, relocate the core and uncore events to a cpu folder. Signed-off-by: John Garry <john.garry@huawei.com> Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com> Cc: Ian Rogers <irogers@google.com> Cc: Ingo Molnar <mingo@redhat.com> Cc: Jin Yao <yao.jin@linux.intel.com> Cc: Jiri Olsa <jolsa@redhat.com> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Namhyung Kim <namhyung@kernel.org> Cc: Peter Zijlstra <peterz@infradead.org> Cc: linuxarm@huawei.com Link: https //lore.kernel.org/r/1627566986-30605-3-git-send-email-john.garry@huawei.com Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
26 lines
775 B
JSON
26 lines
775 B
JSON
[
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{
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"EventCode": "0x6",
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"Counter": "0,1",
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"UMask": "0x80",
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"EventName": "SEGMENT_REG_LOADS.ANY",
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"SampleAfterValue": "200000",
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"BriefDescription": "Number of segment register loads."
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},
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{
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"EventCode": "0x9",
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"Counter": "0,1",
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"UMask": "0x20",
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"EventName": "DISPATCH_BLOCKED.ANY",
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"SampleAfterValue": "200000",
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"BriefDescription": "Memory cluster signals to block micro-op dispatch for any reason"
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},
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{
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"EventCode": "0x3A",
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"Counter": "0,1",
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"UMask": "0x0",
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"EventName": "EIST_TRANS",
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"SampleAfterValue": "200000",
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"BriefDescription": "Number of Enhanced Intel SpeedStep(R) Technology (EIST) transitions"
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}
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] |