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1e8ad07e34
Add version 1.00 of the graniterapids events from https://github.com/intel/perfmon. Signed-off-by: Ian Rogers <irogers@google.com> Cc: Adrian Hunter <adrian.hunter@intel.com> Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com> Cc: Alexandre Torgue <alexandre.torgue@foss.st.com> Cc: Andrii Nakryiko <andrii@kernel.org> Cc: Athira Rajeev <atrajeev@linux.vnet.ibm.com> Cc: Caleb Biggers <caleb.biggers@intel.com> Cc: Eduard Zingerman <eddyz87@gmail.com> Cc: Florian Fischer <florian.fischer@muhq.space> Cc: Ingo Molnar <mingo@redhat.com> Cc: James Clark <james.clark@arm.com> Cc: Jing Zhang <renyu.zj@linux.alibaba.com> Cc: Jiri Olsa <jolsa@kernel.org> Cc: John Garry <john.g.garry@oracle.com> Cc: Kajol Jain <kjain@linux.ibm.com> Cc: Kan Liang <kan.liang@linux.intel.com> Cc: Leo Yan <leo.yan@linaro.org> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Maxime Coquelin <mcoquelin.stm32@gmail.com> Cc: Namhyung Kim <namhyung@kernel.org> Cc: Perry Taylor <perry.taylor@intel.com> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Ravi Bangoria <ravi.bangoria@amd.com> Cc: Sandipan Das <sandipan.das@amd.com> Cc: Sean Christopherson <seanjc@google.com> Cc: Stephane Eranian <eranian@google.com> Cc: Suzuki Poulouse <suzuki.poulose@arm.com> Cc: Xing Zhengjun <zhengjun.xing@linux.intel.com> Cc: linux-arm-kernel@lists.infradead.org Cc: linux-stm32@st-md-mailman.stormreply.com Link: https://lore.kernel.org/r/20230219092848.639226-17-irogers@google.com Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
55 lines
2.7 KiB
JSON
55 lines
2.7 KiB
JSON
[
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{
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"BriefDescription": "L2 code requests",
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"EventCode": "0x24",
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"EventName": "L2_RQSTS.ALL_CODE_RD",
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"PublicDescription": "Counts the total number of L2 code requests.",
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"SampleAfterValue": "200003",
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"UMask": "0xe4"
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},
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{
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"BriefDescription": "Demand Data Read access L2 cache",
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"EventCode": "0x24",
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"EventName": "L2_RQSTS.ALL_DEMAND_DATA_RD",
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"PublicDescription": "Counts Demand Data Read requests accessing the L2 cache. These requests may hit or miss L2 cache. True-miss exclude misses that were merged with ongoing L2 misses. An access is counted once.",
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"SampleAfterValue": "200003",
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"UMask": "0xe1"
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},
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{
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"BriefDescription": "Core-originated cacheable requests that missed L3 (Except hardware prefetches to the L3)",
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"EventCode": "0x2e",
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"EventName": "LONGEST_LAT_CACHE.MISS",
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"PublicDescription": "Counts core-originated cacheable requests that miss the L3 cache (Longest Latency cache). Requests include data and code reads, Reads-for-Ownership (RFOs), speculative accesses and hardware prefetches to the L1 and L2. It does not include hardware prefetches to the L3, and may not count other types of requests to the L3.",
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"SampleAfterValue": "100003",
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"UMask": "0x41"
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},
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{
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"BriefDescription": "Core-originated cacheable requests that refer to L3 (Except hardware prefetches to the L3)",
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"EventCode": "0x2e",
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"EventName": "LONGEST_LAT_CACHE.REFERENCE",
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"PublicDescription": "Counts core-originated cacheable requests to the L3 cache (Longest Latency cache). Requests include data and code reads, Reads-for-Ownership (RFOs), speculative accesses and hardware prefetches to the L1 and L2. It does not include hardware prefetches to the L3, and may not count other types of requests to the L3.",
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"SampleAfterValue": "100003",
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"UMask": "0x4f"
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},
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{
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"BriefDescription": "Retired load instructions.",
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"Data_LA": "1",
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"EventCode": "0xd0",
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"EventName": "MEM_INST_RETIRED.ALL_LOADS",
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"PEBS": "1",
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"PublicDescription": "Counts all retired load instructions. This event accounts for SW prefetch instructions of PREFETCHNTA or PREFETCHT0/1/2 or PREFETCHW.",
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"SampleAfterValue": "1000003",
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"UMask": "0x81"
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},
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{
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"BriefDescription": "Retired store instructions.",
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"Data_LA": "1",
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"EventCode": "0xd0",
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"EventName": "MEM_INST_RETIRED.ALL_STORES",
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"PEBS": "1",
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"PublicDescription": "Counts all retired store instructions.",
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"SampleAfterValue": "1000003",
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"UMask": "0x82"
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}
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]
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