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Update the sandybridge events from 17 to 18. Generation was done using https://github.com/intel/perfmon. Notable changes are improved event descriptions, TMA metrics are updated to version 4.5, TMA info metrics are renamed from their node name to be lower case and prefixed by tma_info_, MetricThreshold expressions are added, and the smi_cost metric group is added replicating existing hard coded metrics in stat-shadow. Signed-off-by: Ian Rogers <irogers@google.com> Cc: Adrian Hunter <adrian.hunter@intel.com> Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com> Cc: Alexandre Torgue <alexandre.torgue@foss.st.com> Cc: Andrii Nakryiko <andrii@kernel.org> Cc: Athira Rajeev <atrajeev@linux.vnet.ibm.com> Cc: Caleb Biggers <caleb.biggers@intel.com> Cc: Eduard Zingerman <eddyz87@gmail.com> Cc: Florian Fischer <florian.fischer@muhq.space> Cc: Ingo Molnar <mingo@redhat.com> Cc: James Clark <james.clark@arm.com> Cc: Jing Zhang <renyu.zj@linux.alibaba.com> Cc: Jiri Olsa <jolsa@kernel.org> Cc: John Garry <john.g.garry@oracle.com> Cc: Kajol Jain <kjain@linux.ibm.com> Cc: Kan Liang <kan.liang@linux.intel.com> Cc: Leo Yan <leo.yan@linaro.org> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Maxime Coquelin <mcoquelin.stm32@gmail.com> Cc: Namhyung Kim <namhyung@kernel.org> Cc: Perry Taylor <perry.taylor@intel.com> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Ravi Bangoria <ravi.bangoria@amd.com> Cc: Sandipan Das <sandipan.das@amd.com> Cc: Sean Christopherson <seanjc@google.com> Cc: Stephane Eranian <eranian@google.com> Cc: Suzuki Poulouse <suzuki.poulose@arm.com> Cc: Xing Zhengjun <zhengjun.xing@linux.intel.com> Cc: linux-arm-kernel@lists.infradead.org Cc: linux-stm32@st-md-mailman.stormreply.com Link: https://lore.kernel.org/r/20230219092848.639226-26-irogers@google.com Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
109 lines
4.0 KiB
JSON
109 lines
4.0 KiB
JSON
[
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{
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"BriefDescription": "Cycles with any input/output SSE or FP assist.",
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"CounterMask": "1",
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"EventCode": "0xCA",
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"EventName": "FP_ASSIST.ANY",
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"SampleAfterValue": "100003",
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"UMask": "0x1e"
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},
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{
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"BriefDescription": "Number of SIMD FP assists due to input values.",
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"EventCode": "0xCA",
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"EventName": "FP_ASSIST.SIMD_INPUT",
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"SampleAfterValue": "100003",
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"UMask": "0x10"
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},
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{
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"BriefDescription": "Number of SIMD FP assists due to Output values.",
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"EventCode": "0xCA",
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"EventName": "FP_ASSIST.SIMD_OUTPUT",
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"SampleAfterValue": "100003",
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"UMask": "0x8"
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},
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{
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"BriefDescription": "Number of X87 assists due to input value.",
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"EventCode": "0xCA",
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"EventName": "FP_ASSIST.X87_INPUT",
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"SampleAfterValue": "100003",
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"UMask": "0x4"
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},
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{
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"BriefDescription": "Number of X87 assists due to output value.",
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"EventCode": "0xCA",
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"EventName": "FP_ASSIST.X87_OUTPUT",
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"SampleAfterValue": "100003",
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"UMask": "0x2"
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},
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{
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"BriefDescription": "Number of SSE* or AVX-128 FP Computational packed double-precision uops issued this cycle.",
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"EventCode": "0x10",
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"EventName": "FP_COMP_OPS_EXE.SSE_PACKED_DOUBLE",
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"SampleAfterValue": "2000003",
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"UMask": "0x10"
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},
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{
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"BriefDescription": "Number of SSE* or AVX-128 FP Computational packed single-precision uops issued this cycle.",
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"EventCode": "0x10",
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"EventName": "FP_COMP_OPS_EXE.SSE_PACKED_SINGLE",
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"SampleAfterValue": "2000003",
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"UMask": "0x40"
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},
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{
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"BriefDescription": "Number of SSE* or AVX-128 FP Computational scalar double-precision uops issued this cycle.",
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"EventCode": "0x10",
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"EventName": "FP_COMP_OPS_EXE.SSE_SCALAR_DOUBLE",
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"SampleAfterValue": "2000003",
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"UMask": "0x80"
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},
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{
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"BriefDescription": "Number of SSE* or AVX-128 FP Computational scalar single-precision uops issued this cycle.",
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"EventCode": "0x10",
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"EventName": "FP_COMP_OPS_EXE.SSE_SCALAR_SINGLE",
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"SampleAfterValue": "2000003",
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"UMask": "0x20"
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},
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{
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"BriefDescription": "Number of FP Computational Uops Executed this cycle. The number of FADD, FSUB, FCOM, FMULs, integer MULs and IMULs, FDIVs, FPREMs, FSQRTS, integer DIVs, and IDIVs. This event does not distinguish an FADD used in the middle of a transcendental flow from a s.",
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"EventCode": "0x10",
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"EventName": "FP_COMP_OPS_EXE.X87",
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"SampleAfterValue": "2000003",
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"UMask": "0x1"
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},
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{
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"BriefDescription": "Number of GSSE memory assist for stores. GSSE microcode assist is being invoked whenever the hardware is unable to properly handle GSSE-256b operations.",
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"EventCode": "0xC1",
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"EventName": "OTHER_ASSISTS.AVX_STORE",
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"SampleAfterValue": "100003",
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"UMask": "0x8"
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},
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{
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"BriefDescription": "Number of transitions from AVX-256 to legacy SSE when penalty applicable.",
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"EventCode": "0xC1",
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"EventName": "OTHER_ASSISTS.AVX_TO_SSE",
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"SampleAfterValue": "100003",
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"UMask": "0x10"
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},
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{
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"BriefDescription": "Number of transitions from SSE to AVX-256 when penalty applicable.",
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"EventCode": "0xC1",
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"EventName": "OTHER_ASSISTS.SSE_TO_AVX",
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"SampleAfterValue": "100003",
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"UMask": "0x20"
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},
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{
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"BriefDescription": "Number of AVX-256 Computational FP double precision uops issued this cycle.",
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"EventCode": "0x11",
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"EventName": "SIMD_FP_256.PACKED_DOUBLE",
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"SampleAfterValue": "2000003",
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"UMask": "0x2"
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},
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{
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"BriefDescription": "Number of GSSE-256 Computational FP single precision uops issued this cycle.",
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"EventCode": "0x11",
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"EventName": "SIMD_FP_256.PACKED_SINGLE",
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"SampleAfterValue": "2000003",
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"UMask": "0x1"
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}
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]
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