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28641ef5f3
Update the sandybridge metrics and events using the new tooling from: https://github.com/intel/perfmon The metrics are unchanged but the formulas differ due to parentheses, use of exponents and removal of redundant operations like "* 1". The events are unchanged but unused json values are removed. The formatting changes increase consistency across the json files. Signed-off-by: Ian Rogers <irogers@google.com> Acked-by: Kan Liang <kan.liang@linux.intel.com> Cc: Adrian Hunter <adrian.hunter@intel.com> Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com> Cc: Caleb Biggers <caleb.biggers@intel.com> Cc: Ingo Molnar <mingo@redhat.com> Cc: Jiri Olsa <jolsa@kernel.org> Cc: John Garry <john.g.garry@oracle.com> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Namhyung Kim <namhyung@kernel.org> Cc: Perry Taylor <perry.taylor@intel.com> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Stephane Eranian <eranian@google.com> Cc: Xing Zhengjun <zhengjun.xing@linux.intel.com> Link: https://lore.kernel.org/r/20221215065510.1621979-15-irogers@google.com Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
118 lines
4.4 KiB
JSON
118 lines
4.4 KiB
JSON
[
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{
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"BriefDescription": "Load misses in all DTLB levels that cause page walks.",
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"EventCode": "0x08",
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"EventName": "DTLB_LOAD_MISSES.MISS_CAUSES_A_WALK",
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"SampleAfterValue": "100003",
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"UMask": "0x1"
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},
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{
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"BriefDescription": "Load operations that miss the first DTLB level but hit the second and do not cause page walks.",
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"EventCode": "0x08",
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"EventName": "DTLB_LOAD_MISSES.STLB_HIT",
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"PublicDescription": "This event counts load operations that miss the first DTLB level but hit the second and do not cause any page walks. The penalty in this case is approximately 7 cycles.",
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"SampleAfterValue": "100003",
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"UMask": "0x10"
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},
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{
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"BriefDescription": "Load misses at all DTLB levels that cause completed page walks.",
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"EventCode": "0x08",
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"EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED",
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"SampleAfterValue": "100003",
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"UMask": "0x2"
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},
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{
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"BriefDescription": "Cycles when PMH is busy with page walks.",
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"EventCode": "0x08",
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"EventName": "DTLB_LOAD_MISSES.WALK_DURATION",
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"PublicDescription": "This event counts cycles when the page miss handler (PMH) is servicing page walks caused by DTLB load misses.",
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"SampleAfterValue": "2000003",
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"UMask": "0x4"
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},
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{
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"BriefDescription": "Store misses in all DTLB levels that cause page walks.",
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"EventCode": "0x49",
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"EventName": "DTLB_STORE_MISSES.MISS_CAUSES_A_WALK",
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"SampleAfterValue": "100003",
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"UMask": "0x1"
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},
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{
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"BriefDescription": "Store operations that miss the first TLB level but hit the second and do not cause page walks.",
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"EventCode": "0x49",
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"EventName": "DTLB_STORE_MISSES.STLB_HIT",
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"SampleAfterValue": "100003",
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"UMask": "0x10"
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},
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{
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"BriefDescription": "Store misses in all DTLB levels that cause completed page walks.",
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"EventCode": "0x49",
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"EventName": "DTLB_STORE_MISSES.WALK_COMPLETED",
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"SampleAfterValue": "100003",
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"UMask": "0x2"
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},
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{
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"BriefDescription": "Cycles when PMH is busy with page walks.",
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"EventCode": "0x49",
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"EventName": "DTLB_STORE_MISSES.WALK_DURATION",
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"SampleAfterValue": "2000003",
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"UMask": "0x4"
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},
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{
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"BriefDescription": "Cycle count for an Extended Page table walk. The Extended Page Directory cache is used by Virtual Machine operating systems while the guest operating systems use the standard TLB caches.",
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"EventCode": "0x4F",
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"EventName": "EPT.WALK_CYCLES",
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"SampleAfterValue": "2000003",
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"UMask": "0x10"
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},
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{
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"BriefDescription": "Flushing of the Instruction TLB (ITLB) pages, includes 4k/2M/4M pages.",
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"EventCode": "0xAE",
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"EventName": "ITLB.ITLB_FLUSH",
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"SampleAfterValue": "100007",
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"UMask": "0x1"
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},
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{
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"BriefDescription": "Misses at all ITLB levels that cause page walks.",
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"EventCode": "0x85",
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"EventName": "ITLB_MISSES.MISS_CAUSES_A_WALK",
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"SampleAfterValue": "100003",
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"UMask": "0x1"
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},
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{
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"BriefDescription": "Operations that miss the first ITLB level but hit the second and do not cause any page walks.",
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"EventCode": "0x85",
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"EventName": "ITLB_MISSES.STLB_HIT",
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"SampleAfterValue": "100003",
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"UMask": "0x10"
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},
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{
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"BriefDescription": "Misses in all ITLB levels that cause completed page walks.",
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"EventCode": "0x85",
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"EventName": "ITLB_MISSES.WALK_COMPLETED",
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"SampleAfterValue": "100003",
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"UMask": "0x2"
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},
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{
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"BriefDescription": "Cycles when PMH is busy with page walks.",
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"EventCode": "0x85",
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"EventName": "ITLB_MISSES.WALK_DURATION",
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"PublicDescription": "This event count cycles when Page Miss Handler (PMH) is servicing page walks caused by ITLB misses.",
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"SampleAfterValue": "2000003",
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"UMask": "0x4"
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},
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{
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"BriefDescription": "DTLB flush attempts of the thread-specific entries.",
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"EventCode": "0xBD",
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"EventName": "TLB_FLUSH.DTLB_THREAD",
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"SampleAfterValue": "100007",
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"UMask": "0x1"
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},
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{
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"BriefDescription": "STLB flush attempts.",
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"EventCode": "0xBD",
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"EventName": "TLB_FLUSH.STLB_ANY",
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"SampleAfterValue": "100007",
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"UMask": "0x20"
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}
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]
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