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The VCPU config deals with hideleg, hedeleg, henvcfg, and hstateenX CSR configuration for each VCPU. Factor-out VCPU config into separate sources so that VCPU config can do things differently for guest HS-mode and guest VS/VU-mode. Signed-off-by: Anup Patel <anup.patel@oss.qualcomm.com> Reviewed-by: Radim Krčmář <radim.krcmar@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260120080013.2153519-9-anup.patel@oss.qualcomm.com Signed-off-by: Anup Patel <anup@brainfault.org>
104 lines
2.9 KiB
C
104 lines
2.9 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (c) 2026 Qualcomm Technologies, Inc.
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*/
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#include <linux/kvm_host.h>
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#include <asm/kvm_nacl.h>
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#define KVM_HEDELEG_DEFAULT (BIT(EXC_INST_MISALIGNED) | \
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BIT(EXC_INST_ILLEGAL) | \
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BIT(EXC_BREAKPOINT) | \
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BIT(EXC_SYSCALL) | \
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BIT(EXC_INST_PAGE_FAULT) | \
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BIT(EXC_LOAD_PAGE_FAULT) | \
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BIT(EXC_STORE_PAGE_FAULT))
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#define KVM_HIDELEG_DEFAULT (BIT(IRQ_VS_SOFT) | \
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BIT(IRQ_VS_TIMER) | \
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BIT(IRQ_VS_EXT))
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void kvm_riscv_vcpu_config_init(struct kvm_vcpu *vcpu)
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{
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vcpu->arch.cfg.hedeleg = KVM_HEDELEG_DEFAULT;
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vcpu->arch.cfg.hideleg = KVM_HIDELEG_DEFAULT;
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}
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void kvm_riscv_vcpu_config_guest_debug(struct kvm_vcpu *vcpu)
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{
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struct kvm_vcpu_config *cfg = &vcpu->arch.cfg;
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if (vcpu->guest_debug)
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cfg->hedeleg &= ~BIT(EXC_BREAKPOINT);
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else
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cfg->hedeleg |= BIT(EXC_BREAKPOINT);
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vcpu->arch.csr_dirty = true;
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}
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void kvm_riscv_vcpu_config_ran_once(struct kvm_vcpu *vcpu)
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{
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const unsigned long *isa = vcpu->arch.isa;
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struct kvm_vcpu_config *cfg = &vcpu->arch.cfg;
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if (riscv_isa_extension_available(isa, SVPBMT))
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cfg->henvcfg |= ENVCFG_PBMTE;
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if (riscv_isa_extension_available(isa, SSTC))
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cfg->henvcfg |= ENVCFG_STCE;
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if (riscv_isa_extension_available(isa, ZICBOM))
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cfg->henvcfg |= (ENVCFG_CBIE | ENVCFG_CBCFE);
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if (riscv_isa_extension_available(isa, ZICBOZ))
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cfg->henvcfg |= ENVCFG_CBZE;
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if (riscv_isa_extension_available(isa, SVADU) &&
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!riscv_isa_extension_available(isa, SVADE))
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cfg->henvcfg |= ENVCFG_ADUE;
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if (riscv_has_extension_unlikely(RISCV_ISA_EXT_SMSTATEEN)) {
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cfg->hstateen0 |= SMSTATEEN0_HSENVCFG;
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if (riscv_isa_extension_available(isa, SSAIA))
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cfg->hstateen0 |= SMSTATEEN0_AIA_IMSIC |
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SMSTATEEN0_AIA |
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SMSTATEEN0_AIA_ISEL;
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if (riscv_isa_extension_available(isa, SMSTATEEN))
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cfg->hstateen0 |= SMSTATEEN0_SSTATEEN0;
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}
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if (vcpu->guest_debug)
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cfg->hedeleg &= ~BIT(EXC_BREAKPOINT);
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}
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void kvm_riscv_vcpu_config_load(struct kvm_vcpu *vcpu)
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{
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struct kvm_vcpu_config *cfg = &vcpu->arch.cfg;
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void *nsh;
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if (kvm_riscv_nacl_sync_csr_available()) {
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nsh = nacl_shmem();
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nacl_csr_write(nsh, CSR_HEDELEG, cfg->hedeleg);
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nacl_csr_write(nsh, CSR_HIDELEG, cfg->hideleg);
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nacl_csr_write(nsh, CSR_HENVCFG, cfg->henvcfg);
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if (IS_ENABLED(CONFIG_32BIT))
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nacl_csr_write(nsh, CSR_HENVCFGH, cfg->henvcfg >> 32);
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if (riscv_has_extension_unlikely(RISCV_ISA_EXT_SMSTATEEN)) {
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nacl_csr_write(nsh, CSR_HSTATEEN0, cfg->hstateen0);
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if (IS_ENABLED(CONFIG_32BIT))
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nacl_csr_write(nsh, CSR_HSTATEEN0H, cfg->hstateen0 >> 32);
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}
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} else {
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csr_write(CSR_HEDELEG, cfg->hedeleg);
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csr_write(CSR_HIDELEG, cfg->hideleg);
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csr_write(CSR_HENVCFG, cfg->henvcfg);
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if (IS_ENABLED(CONFIG_32BIT))
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csr_write(CSR_HENVCFGH, cfg->henvcfg >> 32);
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if (riscv_has_extension_unlikely(RISCV_ISA_EXT_SMSTATEEN)) {
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csr_write(CSR_HSTATEEN0, cfg->hstateen0);
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if (IS_ENABLED(CONFIG_32BIT))
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csr_write(CSR_HSTATEEN0H, cfg->hstateen0 >> 32);
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}
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}
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}
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