Thor Thayer abd56b3c84 Documentation: dt: socfpga: Add Altera Arria10 OCRAM binding ...

Add the device tree bindings needed to support the Altera On-Chip
RAM ECC on the Arria10 chip.

Signed-off-by: Thor Thayer <tthayer@opensource.altera.com>
Acked-by: Rob Herring <robh@kernel.org>
Cc: devicetree@vger.kernel.org
Cc: dinguyen@opensource.altera.com
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux@arm.linux.org.uk
Cc: linux-edac <linux-edac@vger.kernel.org>
Link: http://lkml.kernel.org/r/1459450087-24792-5-git-send-email-tthayer@opensource.altera.com
Signed-off-by: Borislav Petkov <bp@suse.de>

2016-04-02 13:49:07 +02:00

..

socfpga-clk-manager.txt

ARM: socfpga: Add clock entries into device tree

2013-04-14 20:17:59 -07:00

socfpga-eccmgr.txt

Documentation: dt: socfpga: Add Altera Arria10 OCRAM binding

2016-04-02 13:49:07 +02:00

socfpga-sdram-controller.txt

ARM: socfpga: dts: add sdram controller dt binding doc

2015-06-02 14:19:27 -05:00

socfpga-sdram-edac.txt

arm: socfpga: dts: Add Arria10 SDRAM EDAC DTS support

2015-06-24 18:16:10 +02:00

socfpga-system.txt

arm: socfpga: Add SMP support for actual socfpga harware

2013-02-11 19:37:26 -08:00