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a145abf12c
Even though a tlb_flush() does a flush with invalidate all cache,
we can end up doing an RCU page table free before calling tlb_flush().
That means we can have page walk cache entries even after we free the
page table pages. This can result in us doing wrong page table walk.
Avoid this by doing pwc flush on every page table free. We can't batch
the pwc flush, because the rcu call back function where we free the
page table pages doesn't have information of the mmu gather. Thus we
have to do a pwc on every page table page freed.
Note: I also removed the dummy tlb_flush_pgtable call functions for
hash 32.
Fixes: 1a472c9dba ("powerpc/mm/radix: Add tlbflush routines")
Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
91 lines
2.3 KiB
C
91 lines
2.3 KiB
C
#ifndef _ASM_POWERPC_BOOK3S_64_TLBFLUSH_H
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#define _ASM_POWERPC_BOOK3S_64_TLBFLUSH_H
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#define MMU_NO_CONTEXT ~0UL
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#include <asm/book3s/64/tlbflush-hash.h>
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#include <asm/book3s/64/tlbflush-radix.h>
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static inline void flush_tlb_range(struct vm_area_struct *vma,
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unsigned long start, unsigned long end)
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{
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if (radix_enabled())
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return radix__flush_tlb_range(vma, start, end);
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return hash__flush_tlb_range(vma, start, end);
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}
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static inline void flush_tlb_kernel_range(unsigned long start,
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unsigned long end)
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{
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if (radix_enabled())
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return radix__flush_tlb_kernel_range(start, end);
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return hash__flush_tlb_kernel_range(start, end);
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}
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static inline void local_flush_tlb_mm(struct mm_struct *mm)
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{
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if (radix_enabled())
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return radix__local_flush_tlb_mm(mm);
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return hash__local_flush_tlb_mm(mm);
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}
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static inline void local_flush_tlb_page(struct vm_area_struct *vma,
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unsigned long vmaddr)
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{
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if (radix_enabled())
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return radix__local_flush_tlb_page(vma, vmaddr);
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return hash__local_flush_tlb_page(vma, vmaddr);
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}
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static inline void flush_tlb_page_nohash(struct vm_area_struct *vma,
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unsigned long vmaddr)
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{
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if (radix_enabled())
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return radix__flush_tlb_page(vma, vmaddr);
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return hash__flush_tlb_page_nohash(vma, vmaddr);
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}
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static inline void tlb_flush(struct mmu_gather *tlb)
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{
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if (radix_enabled())
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return radix__tlb_flush(tlb);
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return hash__tlb_flush(tlb);
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}
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#ifdef CONFIG_SMP
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static inline void flush_tlb_mm(struct mm_struct *mm)
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{
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if (radix_enabled())
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return radix__flush_tlb_mm(mm);
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return hash__flush_tlb_mm(mm);
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}
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static inline void flush_tlb_page(struct vm_area_struct *vma,
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unsigned long vmaddr)
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{
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if (radix_enabled())
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return radix__flush_tlb_page(vma, vmaddr);
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return hash__flush_tlb_page(vma, vmaddr);
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}
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#else
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#define flush_tlb_mm(mm) local_flush_tlb_mm(mm)
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#define flush_tlb_page(vma, addr) local_flush_tlb_page(vma, addr)
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#endif /* CONFIG_SMP */
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/*
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* flush the page walk cache for the address
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*/
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static inline void flush_tlb_pgtable(struct mmu_gather *tlb, unsigned long address)
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{
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/*
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* Flush the page table walk cache on freeing a page table. We already
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* have marked the upper/higher level page table entry none by now.
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* So it is safe to flush PWC here.
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*/
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if (!radix_enabled())
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return;
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radix__flush_tlb_pwc(tlb, address);
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}
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#endif /* _ASM_POWERPC_BOOK3S_64_TLBFLUSH_H */
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