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923f1bd27b
Add secure boot support for the GM20B chip found in Tegra X1. Secure boot on Tegra works slightly differently from desktop, notably in the way the WPR region is set up. In addition, the firmware bootloaders use a slightly different header format. Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
60 lines
2.2 KiB
C
60 lines
2.2 KiB
C
/*
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* Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#ifndef __NVKM_SECURE_BOOT_H__
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#define __NVKM_SECURE_BOOT_H__
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#include <core/subdev.h>
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enum nvkm_secboot_falcon {
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NVKM_SECBOOT_FALCON_PMU = 0,
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NVKM_SECBOOT_FALCON_RESERVED = 1,
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NVKM_SECBOOT_FALCON_FECS = 2,
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NVKM_SECBOOT_FALCON_GPCCS = 3,
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NVKM_SECBOOT_FALCON_END = 4,
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NVKM_SECBOOT_FALCON_INVALID = 0xffffffff,
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};
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/**
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* @base: base IO address of the falcon performing secure boot
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* @irq_mask: IRQ mask of the falcon performing secure boot
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* @enable_mask: enable mask of the falcon performing secure boot
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*/
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struct nvkm_secboot {
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const struct nvkm_secboot_func *func;
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struct nvkm_subdev subdev;
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u32 base;
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u32 irq_mask;
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u32 enable_mask;
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};
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#define nvkm_secboot(p) container_of((p), struct nvkm_secboot, subdev)
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bool nvkm_secboot_is_managed(struct nvkm_secboot *, enum nvkm_secboot_falcon);
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int nvkm_secboot_reset(struct nvkm_secboot *, u32 falcon);
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int nvkm_secboot_start(struct nvkm_secboot *, u32 falcon);
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int gm200_secboot_new(struct nvkm_device *, int, struct nvkm_secboot **);
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int gm20b_secboot_new(struct nvkm_device *, int, struct nvkm_secboot **);
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#endif
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