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The Devicetree bindings document does not have to say in the title that
it is a "Devicetree binding", but instead just describe the hardware.
Drop beginning "Devicetree bindings" in various forms:
find Documentation/devicetree/bindings/ -type f -name '*.yaml' \
-exec sed -i -e 's/^title: [dD]evice[ -]\?[tT]ree [bB]indings\? for \([tT]he \)\?\(.*\)$/title: \u\2/' {} \;
find Documentation/devicetree/bindings/ -type f -name '*.yaml' \
-exec sed -i -e 's/^title: [bB]indings\? for \([tT]he \)\?\(.*\)$/title: \u\2/' {} \;
find Documentation/devicetree/bindings/ -type f -name '*.yaml' \
-exec sed -i -e 's/^title: [dD][tT] [bB]indings\? for \([tT]he \)\?\(.*\)$/title: \u\2/' {} \;
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Acked-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Acked-by: Ulf Hansson <ulf.hansson@linaro.org> # MMC
Acked-by: Stephen Boyd <sboyd@kernel.org> # clk
Acked-by: Dmitry Torokhov <dmitry.torokhov@gmail.com> # input
Acked-by: Mark Brown <broonie@kernel.org>
Acked-by: Sebastian Reichel <sre@kernel.org> # power
Link: https://lore.kernel.org/r/20221216163815.522628-8-krzysztof.kozlowski@linaro.org
Signed-off-by: Rob Herring <robh@kernel.org>
136 lines
3.1 KiB
YAML
136 lines
3.1 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: "http://devicetree.org/schemas/gpu/host1x/nvidia,tegra210-nvenc.yaml#"
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$schema: "http://devicetree.org/meta-schemas/core.yaml#"
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title: NVIDIA Tegra NVENC
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description: |
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NVENC is the hardware video encoder present on NVIDIA Tegra210
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and newer chips. It is located on the Host1x bus and typically
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programmed through Host1x channels.
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maintainers:
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- Thierry Reding <treding@gmail.com>
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- Mikko Perttunen <mperttunen@nvidia.com>
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properties:
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$nodename:
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pattern: "^nvenc@[0-9a-f]*$"
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compatible:
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enum:
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- nvidia,tegra210-nvenc
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- nvidia,tegra186-nvenc
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- nvidia,tegra194-nvenc
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reg:
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maxItems: 1
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clocks:
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maxItems: 1
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clock-names:
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items:
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- const: nvenc
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resets:
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maxItems: 1
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reset-names:
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items:
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- const: nvenc
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power-domains:
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maxItems: 1
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iommus:
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maxItems: 1
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dma-coherent: true
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interconnects:
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minItems: 2
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maxItems: 3
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interconnect-names:
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minItems: 2
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maxItems: 3
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nvidia,host1x-class:
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description: |
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Host1x class of the engine, used to specify the targeted engine
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when programming the engine through Host1x channels or when
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configuring engine-specific behavior in Host1x.
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default: 0x21
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$ref: /schemas/types.yaml#/definitions/uint32
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required:
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- compatible
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- reg
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- clocks
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- clock-names
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- resets
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- reset-names
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- power-domains
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allOf:
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- if:
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properties:
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compatible:
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enum:
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- nvidia,tegra210-nvenc
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- nvidia,tegra186-nvenc
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then:
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properties:
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interconnects:
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items:
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- description: DMA read memory client
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- description: DMA write memory client
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interconnect-names:
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items:
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- const: dma-mem
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- const: write
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- if:
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properties:
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compatible:
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enum:
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- nvidia,tegra194-nvenc
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then:
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properties:
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interconnects:
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items:
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- description: DMA read memory client
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- description: DMA read 2 memory client
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- description: DMA write memory client
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interconnect-names:
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items:
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- const: dma-mem
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- const: read-1
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- const: write
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/clock/tegra186-clock.h>
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#include <dt-bindings/memory/tegra186-mc.h>
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#include <dt-bindings/power/tegra186-powergate.h>
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#include <dt-bindings/reset/tegra186-reset.h>
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nvenc@154c0000 {
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compatible = "nvidia,tegra186-nvenc";
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reg = <0x154c0000 0x40000>;
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clocks = <&bpmp TEGRA186_CLK_NVENC>;
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clock-names = "nvenc";
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resets = <&bpmp TEGRA186_RESET_NVENC>;
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reset-names = "nvenc";
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power-domains = <&bpmp TEGRA186_POWER_DOMAIN_MPE>;
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interconnects = <&mc TEGRA186_MEMORY_CLIENT_NVENCSRD &emc>,
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<&mc TEGRA186_MEMORY_CLIENT_NVENCSWR &emc>;
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interconnect-names = "dma-mem", "write";
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iommus = <&smmu TEGRA186_SID_NVENC>;
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};
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