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cc40b04c08
The QAT HW supports an hardware mechanism to detect an accelerator hang.
The reporting of a hang occurs after a watchdog timer (WDT) expires.
The value of the WDT set previously was too small and was causing false
positives.
Change the default value of the WDT to 0x7000000ULL to avoid this.
Fixes: 1c4d9d5bbb ("crypto: qat - enable detection of accelerators hang")
Reviewed-by: Giovanni Cabiddu <giovanni.cabiddu@intel.com>
Signed-off-by: Lucas Segarra Fernandez <lucas.segarra.fernandez@intel.com>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
143 lines
5.5 KiB
C
143 lines
5.5 KiB
C
/* SPDX-License-Identifier: (BSD-3-Clause OR GPL-2.0-only) */
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/* Copyright(c) 2020 Intel Corporation */
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#ifndef ADF_GEN4_HW_CSR_DATA_H_
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#define ADF_GEN4_HW_CSR_DATA_H_
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#include "adf_accel_devices.h"
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#include "adf_cfg_common.h"
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/* Transport access */
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#define ADF_BANK_INT_SRC_SEL_MASK 0x44UL
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#define ADF_RING_CSR_RING_CONFIG 0x1000
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#define ADF_RING_CSR_RING_LBASE 0x1040
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#define ADF_RING_CSR_RING_UBASE 0x1080
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#define ADF_RING_CSR_RING_HEAD 0x0C0
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#define ADF_RING_CSR_RING_TAIL 0x100
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#define ADF_RING_CSR_E_STAT 0x14C
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#define ADF_RING_CSR_INT_FLAG 0x170
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#define ADF_RING_CSR_INT_SRCSEL 0x174
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#define ADF_RING_CSR_INT_COL_CTL 0x180
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#define ADF_RING_CSR_INT_FLAG_AND_COL 0x184
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#define ADF_RING_CSR_INT_COL_CTL_ENABLE 0x80000000
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#define ADF_RING_CSR_INT_COL_EN 0x17C
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#define ADF_RING_CSR_ADDR_OFFSET 0x100000
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#define ADF_RING_BUNDLE_SIZE 0x2000
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#define BUILD_RING_BASE_ADDR(addr, size) \
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((((addr) >> 6) & (GENMASK_ULL(63, 0) << (size))) << 6)
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#define READ_CSR_RING_HEAD(csr_base_addr, bank, ring) \
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ADF_CSR_RD((csr_base_addr) + ADF_RING_CSR_ADDR_OFFSET, \
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ADF_RING_BUNDLE_SIZE * (bank) + \
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ADF_RING_CSR_RING_HEAD + ((ring) << 2))
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#define READ_CSR_RING_TAIL(csr_base_addr, bank, ring) \
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ADF_CSR_RD((csr_base_addr) + ADF_RING_CSR_ADDR_OFFSET, \
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ADF_RING_BUNDLE_SIZE * (bank) + \
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ADF_RING_CSR_RING_TAIL + ((ring) << 2))
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#define READ_CSR_E_STAT(csr_base_addr, bank) \
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ADF_CSR_RD((csr_base_addr) + ADF_RING_CSR_ADDR_OFFSET, \
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ADF_RING_BUNDLE_SIZE * (bank) + ADF_RING_CSR_E_STAT)
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#define WRITE_CSR_RING_CONFIG(csr_base_addr, bank, ring, value) \
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ADF_CSR_WR((csr_base_addr) + ADF_RING_CSR_ADDR_OFFSET, \
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ADF_RING_BUNDLE_SIZE * (bank) + \
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ADF_RING_CSR_RING_CONFIG + ((ring) << 2), value)
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#define WRITE_CSR_RING_BASE(csr_base_addr, bank, ring, value) \
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do { \
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void __iomem *_csr_base_addr = csr_base_addr; \
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u32 _bank = bank; \
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u32 _ring = ring; \
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dma_addr_t _value = value; \
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u32 l_base = 0, u_base = 0; \
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l_base = lower_32_bits(_value); \
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u_base = upper_32_bits(_value); \
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ADF_CSR_WR((_csr_base_addr) + ADF_RING_CSR_ADDR_OFFSET, \
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ADF_RING_BUNDLE_SIZE * (_bank) + \
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ADF_RING_CSR_RING_LBASE + ((_ring) << 2), l_base); \
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ADF_CSR_WR((_csr_base_addr) + ADF_RING_CSR_ADDR_OFFSET, \
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ADF_RING_BUNDLE_SIZE * (_bank) + \
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ADF_RING_CSR_RING_UBASE + ((_ring) << 2), u_base); \
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} while (0)
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#define WRITE_CSR_RING_HEAD(csr_base_addr, bank, ring, value) \
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ADF_CSR_WR((csr_base_addr) + ADF_RING_CSR_ADDR_OFFSET, \
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ADF_RING_BUNDLE_SIZE * (bank) + \
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ADF_RING_CSR_RING_HEAD + ((ring) << 2), value)
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#define WRITE_CSR_RING_TAIL(csr_base_addr, bank, ring, value) \
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ADF_CSR_WR((csr_base_addr) + ADF_RING_CSR_ADDR_OFFSET, \
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ADF_RING_BUNDLE_SIZE * (bank) + \
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ADF_RING_CSR_RING_TAIL + ((ring) << 2), value)
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#define WRITE_CSR_INT_FLAG(csr_base_addr, bank, value) \
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ADF_CSR_WR((csr_base_addr) + ADF_RING_CSR_ADDR_OFFSET, \
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ADF_RING_BUNDLE_SIZE * (bank) + \
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ADF_RING_CSR_INT_FLAG, (value))
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#define WRITE_CSR_INT_SRCSEL(csr_base_addr, bank) \
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ADF_CSR_WR((csr_base_addr) + ADF_RING_CSR_ADDR_OFFSET, \
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ADF_RING_BUNDLE_SIZE * (bank) + \
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ADF_RING_CSR_INT_SRCSEL, ADF_BANK_INT_SRC_SEL_MASK)
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#define WRITE_CSR_INT_COL_EN(csr_base_addr, bank, value) \
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ADF_CSR_WR((csr_base_addr) + ADF_RING_CSR_ADDR_OFFSET, \
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ADF_RING_BUNDLE_SIZE * (bank) + \
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ADF_RING_CSR_INT_COL_EN, (value))
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#define WRITE_CSR_INT_COL_CTL(csr_base_addr, bank, value) \
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ADF_CSR_WR((csr_base_addr) + ADF_RING_CSR_ADDR_OFFSET, \
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ADF_RING_BUNDLE_SIZE * (bank) + \
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ADF_RING_CSR_INT_COL_CTL, \
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ADF_RING_CSR_INT_COL_CTL_ENABLE | (value))
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#define WRITE_CSR_INT_FLAG_AND_COL(csr_base_addr, bank, value) \
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ADF_CSR_WR((csr_base_addr) + ADF_RING_CSR_ADDR_OFFSET, \
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ADF_RING_BUNDLE_SIZE * (bank) + \
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ADF_RING_CSR_INT_FLAG_AND_COL, (value))
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/* Arbiter configuration */
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#define ADF_RING_CSR_RING_SRV_ARB_EN 0x19C
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#define WRITE_CSR_RING_SRV_ARB_EN(csr_base_addr, bank, value) \
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ADF_CSR_WR((csr_base_addr) + ADF_RING_CSR_ADDR_OFFSET, \
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ADF_RING_BUNDLE_SIZE * (bank) + \
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ADF_RING_CSR_RING_SRV_ARB_EN, (value))
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/* Default ring mapping */
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#define ADF_GEN4_DEFAULT_RING_TO_SRV_MAP \
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(ASYM << ADF_CFG_SERV_RING_PAIR_0_SHIFT | \
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SYM << ADF_CFG_SERV_RING_PAIR_1_SHIFT | \
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ASYM << ADF_CFG_SERV_RING_PAIR_2_SHIFT | \
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SYM << ADF_CFG_SERV_RING_PAIR_3_SHIFT)
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/* WDT timers
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*
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* Timeout is in cycles. Clock speed may vary across products but this
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* value should be a few milli-seconds.
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*/
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#define ADF_SSM_WDT_DEFAULT_VALUE 0x7000000ULL
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#define ADF_SSM_WDT_PKE_DEFAULT_VALUE 0x8000000
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#define ADF_SSMWDTL_OFFSET 0x54
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#define ADF_SSMWDTH_OFFSET 0x5C
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#define ADF_SSMWDTPKEL_OFFSET 0x58
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#define ADF_SSMWDTPKEH_OFFSET 0x60
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/* Ring reset */
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#define ADF_RPRESET_POLL_TIMEOUT_US (5 * USEC_PER_SEC)
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#define ADF_RPRESET_POLL_DELAY_US 20
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#define ADF_WQM_CSR_RPRESETCTL_RESET BIT(0)
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#define ADF_WQM_CSR_RPRESETCTL(bank) (0x6000 + ((bank) << 3))
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#define ADF_WQM_CSR_RPRESETSTS_STATUS BIT(0)
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#define ADF_WQM_CSR_RPRESETSTS(bank) (ADF_WQM_CSR_RPRESETCTL(bank) + 4)
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/* Error source registers */
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#define ADF_GEN4_ERRSOU0 (0x41A200)
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#define ADF_GEN4_ERRSOU1 (0x41A204)
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#define ADF_GEN4_ERRSOU2 (0x41A208)
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#define ADF_GEN4_ERRSOU3 (0x41A20C)
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/* Error source mask registers */
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#define ADF_GEN4_ERRMSK0 (0x41A210)
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#define ADF_GEN4_ERRMSK1 (0x41A214)
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#define ADF_GEN4_ERRMSK2 (0x41A218)
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#define ADF_GEN4_ERRMSK3 (0x41A21C)
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#define ADF_GEN4_VFLNOTIFY BIT(7)
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void adf_gen4_set_ssm_wdtimer(struct adf_accel_dev *accel_dev);
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void adf_gen4_init_hw_csr_ops(struct adf_hw_csr_ops *csr_ops);
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int adf_gen4_ring_pair_reset(struct adf_accel_dev *accel_dev, u32 bank_number);
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#endif
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