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There are different types of PHY from one chipset to another, while the DSI host controller is relatively consistent across platforms. Also, the PLL inside PHY is providing the source of DSI byte and pixel clocks, which are used by DSI host controller. Separated devices for clock provider and clock consumer make DSI driver better fit into common clock framework. Signed-off-by: Hai Li <hali@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
121 lines
3.6 KiB
Plaintext
121 lines
3.6 KiB
Plaintext
Qualcomm Technologies Inc. adreno/snapdragon DSI output
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DSI Controller:
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Required properties:
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- compatible:
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* "qcom,mdss-dsi-ctrl"
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- reg: Physical base address and length of the registers of controller
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- reg-names: The names of register regions. The following regions are required:
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* "dsi_ctrl"
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- qcom,dsi-host-index: The ID of DSI controller hardware instance. This should
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be 0 or 1, since we have 2 DSI controllers at most for now.
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- interrupts: The interrupt signal from the DSI block.
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- power-domains: Should be <&mmcc MDSS_GDSC>.
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- clocks: device clocks
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See Documentation/devicetree/bindings/clocks/clock-bindings.txt for details.
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- clock-names: the following clocks are required:
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* "bus_clk"
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* "byte_clk"
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* "core_clk"
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* "core_mmss_clk"
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* "iface_clk"
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* "mdp_core_clk"
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* "pixel_clk"
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- vdd-supply: phandle to vdd regulator device node
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- vddio-supply: phandle to vdd-io regulator device node
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- vdda-supply: phandle to vdda regulator device node
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- qcom,dsi-phy: phandle to DSI PHY device node
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Optional properties:
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- panel@0: Node of panel connected to this DSI controller.
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See files in Documentation/devicetree/bindings/panel/ for each supported
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panel.
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- qcom,dual-panel-mode: Boolean value indicating if the DSI controller is
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driving a panel which needs 2 DSI links.
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- qcom,master-panel: Boolean value indicating if the DSI controller is driving
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the master link of the 2-DSI panel.
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- qcom,sync-dual-panel: Boolean value indicating if the DSI controller is
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driving a 2-DSI panel whose 2 links need receive command simultaneously.
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- interrupt-parent: phandle to the MDP block if the interrupt signal is routed
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through MDP block
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DSI PHY:
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Required properties:
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- compatible: Could be the following
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* "qcom,dsi-phy-28nm-hpm"
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* "qcom,dsi-phy-28nm-lp"
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- reg: Physical base address and length of the registers of PLL, PHY and PHY
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regulator
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- reg-names: The names of register regions. The following regions are required:
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* "dsi_pll"
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* "dsi_phy"
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* "dsi_phy_regulator"
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- qcom,dsi-phy-index: The ID of DSI PHY hardware instance. This should
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be 0 or 1, since we have 2 DSI PHYs at most for now.
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- power-domains: Should be <&mmcc MDSS_GDSC>.
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- clocks: device clocks
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See Documentation/devicetree/bindings/clocks/clock-bindings.txt for details.
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- clock-names: the following clocks are required:
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* "iface_clk"
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- vddio-supply: phandle to vdd-io regulator device node
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Example:
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mdss_dsi0: qcom,mdss_dsi@fd922800 {
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compatible = "qcom,mdss-dsi-ctrl";
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qcom,dsi-host-index = <0>;
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interrupt-parent = <&mdss_mdp>;
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interrupts = <4 0>;
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reg-names = "dsi_ctrl";
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reg = <0xfd922800 0x200>;
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power-domains = <&mmcc MDSS_GDSC>;
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clock-names =
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"bus_clk",
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"byte_clk",
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"core_clk",
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"core_mmss_clk",
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"iface_clk",
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"mdp_core_clk",
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"pixel_clk";
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clocks =
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<&mmcc MDSS_AXI_CLK>,
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<&mmcc MDSS_BYTE0_CLK>,
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<&mmcc MDSS_ESC0_CLK>,
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<&mmcc MMSS_MISC_AHB_CLK>,
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<&mmcc MDSS_AHB_CLK>,
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<&mmcc MDSS_MDP_CLK>,
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<&mmcc MDSS_PCLK0_CLK>;
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vdda-supply = <&pma8084_l2>;
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vdd-supply = <&pma8084_l22>;
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vddio-supply = <&pma8084_l12>;
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qcom,dsi-phy = <&mdss_dsi_phy0>;
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qcom,dual-panel-mode;
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qcom,master-panel;
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qcom,sync-dual-panel;
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panel: panel@0 {
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compatible = "sharp,lq101r1sx01";
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reg = <0>;
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link2 = <&secondary>;
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power-supply = <...>;
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backlight = <...>;
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};
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};
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mdss_dsi_phy0: qcom,mdss_dsi_phy@fd922a00 {
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compatible = "qcom,dsi-phy-28nm-hpm";
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qcom,dsi-phy-index = <0>;
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reg-names =
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"dsi_pll",
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"dsi_phy",
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"dsi_phy_regulator";
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reg = <0xfd922a00 0xd4>,
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<0xfd922b00 0x2b0>,
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<0xfd922d80 0x7b>;
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clock-names = "iface_clk";
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clocks = <&mmcc MDSS_AHB_CLK>;
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vddio-supply = <&pma8084_l12>;
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};
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