mirror of
https://github.com/torvalds/linux.git
synced 2026-04-18 23:03:57 -04:00
c17ccefb61
The CPU core in ipq5424 is clocked by a huayra PLL with RCG support. The RCG and PLL have a separate register space from the GCC. Also the L3 cache has a separate pll and needs to be scaled along with the CPU. Co-developed-by: Md Sadre Alam <quic_mdalam@quicinc.com> Signed-off-by: Md Sadre Alam <quic_mdalam@quicinc.com> Signed-off-by: Sricharan Ramabadhran <quic_srichara@quicinc.com> [ Added interconnect related changes ] Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com> Link: https://lore.kernel.org/r/20250811090954.2854440-2-quic_varada@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
56 lines
1.1 KiB
YAML
56 lines
1.1 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
|
%YAML 1.2
|
|
---
|
|
$id: http://devicetree.org/schemas/clock/qcom,ipq5424-apss-clk.yaml#
|
|
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
|
|
|
title: Qualcomm APSS IPQ5424 Clock Controller
|
|
|
|
maintainers:
|
|
- Varadarajan Narayanan <quic_varada@quicinc.com>
|
|
|
|
description:
|
|
The CPU core in ipq5424 is clocked by a huayra PLL with RCG support.
|
|
The RCG and PLL have a separate register space from the GCC.
|
|
|
|
properties:
|
|
compatible:
|
|
enum:
|
|
- qcom,ipq5424-apss-clk
|
|
|
|
reg:
|
|
maxItems: 1
|
|
|
|
clocks:
|
|
items:
|
|
- description: Reference to the XO clock.
|
|
- description: Reference to the GPLL0 clock.
|
|
|
|
'#clock-cells':
|
|
const: 1
|
|
|
|
'#interconnect-cells':
|
|
const: 1
|
|
|
|
required:
|
|
- compatible
|
|
- reg
|
|
- clocks
|
|
- '#clock-cells'
|
|
- '#interconnect-cells'
|
|
|
|
additionalProperties: false
|
|
|
|
examples:
|
|
- |
|
|
#include <dt-bindings/clock/qcom,ipq5424-gcc.h>
|
|
|
|
apss_clk: clock-controller@fa80000 {
|
|
compatible = "qcom,ipq5424-apss-clk";
|
|
reg = <0x0fa80000 0x20000>;
|
|
clocks = <&xo_board>,
|
|
<&gcc GPLL0>;
|
|
#clock-cells = <1>;
|
|
#interconnect-cells = <1>;
|
|
};
|