mirror of
https://github.com/torvalds/linux.git
synced 2026-04-18 23:03:57 -04:00
0d069bb381
The QUICC Engine provides interrupts for a few I/O ports. This is handled via a separate interrupt ID and managed via a triplet of dedicated registers hosted by the SoC. Implement an interrupt driver for it so that those IRQs can then be linked to the related GPIOs. Acked-by: Conor Dooley <conor.dooley@microchip.com> Link: https://lore.kernel.org/r/7708243d6cca21004de8b3da87369c06dbee3848.1767804922.git.chleroy@kernel.org Signed-off-by: Christophe Leroy (CS GROUP) <chleroy@kernel.org> [moved from bindings/soc/fsl/cpm_qe/ to bindings/interrupt-controller/ while applying]
52 lines
981 B
YAML
52 lines
981 B
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
|
%YAML 1.2
|
|
---
|
|
$id: http://devicetree.org/schemas/interrupt-controller/fsl,qe-ports-ic.yaml#
|
|
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
|
|
|
title: Freescale QUICC Engine I/O Ports Interrupt Controller
|
|
|
|
maintainers:
|
|
- Christophe Leroy (CS GROUP) <chleroy@kernel.org>
|
|
|
|
properties:
|
|
compatible:
|
|
enum:
|
|
- fsl,mpc8323-qe-ports-ic
|
|
|
|
reg:
|
|
maxItems: 1
|
|
|
|
interrupt-controller: true
|
|
|
|
'#address-cells':
|
|
const: 0
|
|
|
|
'#interrupt-cells':
|
|
const: 1
|
|
|
|
interrupts:
|
|
maxItems: 1
|
|
|
|
required:
|
|
- compatible
|
|
- reg
|
|
- interrupt-controller
|
|
- '#address-cells'
|
|
- '#interrupt-cells'
|
|
- interrupts
|
|
|
|
additionalProperties: false
|
|
|
|
examples:
|
|
- |
|
|
interrupt-controller@c00 {
|
|
compatible = "fsl,mpc8323-qe-ports-ic";
|
|
reg = <0xc00 0x18>;
|
|
interrupt-controller;
|
|
#address-cells = <0>;
|
|
#interrupt-cells = <1>;
|
|
interrupts = <74 0x8>;
|
|
interrupt-parent = <&ipic>;
|
|
};
|