mirror of
https://github.com/torvalds/linux.git
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e1cbc3b96a
Pull iommu updates from Joerg Roedel:
- Intel VT-d driver updates:
- Domain force snooping improvement.
- Cleanups, no intentional functional changes.
- ARM SMMU driver updates:
- Add new Qualcomm device-tree compatible strings
- Add new Nvidia device-tree compatible string for Tegra234
- Fix UAF in SMMUv3 shared virtual addressing code
- Force identity-mapped domains for users of ye olde SMMU legacy
binding
- Minor cleanups
- Fix a BUG_ON in the vfio_iommu_group_notifier:
- Groundwork for upcoming iommufd framework
- Introduction of DMA ownership so that an entire IOMMU group is
either controlled by the kernel or by user-space
- MT8195 and MT8186 support in the Mediatek IOMMU driver
- Make forcing of cache-coherent DMA more coherent between IOMMU
drivers
- Fixes for thunderbolt device DMA protection
- Various smaller fixes and cleanups
* tag 'iommu-updates-v5.19' of git://git.kernel.org/pub/scm/linux/kernel/git/joro/iommu: (88 commits)
iommu/amd: Increase timeout waiting for GA log enablement
iommu/s390: Tolerate repeat attach_dev calls
iommu/vt-d: Remove hard coding PGSNP bit in PASID entries
iommu/vt-d: Remove domain_update_iommu_snooping()
iommu/vt-d: Check domain force_snooping against attached devices
iommu/vt-d: Block force-snoop domain attaching if no SC support
iommu/vt-d: Size Page Request Queue to avoid overflow condition
iommu/vt-d: Fold dmar_insert_one_dev_info() into its caller
iommu/vt-d: Change return type of dmar_insert_one_dev_info()
iommu/vt-d: Remove unneeded validity check on dev
iommu/dma: Explicitly sort PCI DMA windows
iommu/dma: Fix iova map result check bug
iommu/mediatek: Fix NULL pointer dereference when printing dev_name
iommu: iommu_group_claim_dma_owner() must always assign a domain
iommu/arm-smmu: Force identity domains for legacy binding
iommu/arm-smmu: Support Tegra234 SMMU
dt-bindings: arm-smmu: Add compatible for Tegra234 SOC
dt-bindings: arm-smmu: Document nvidia,memory-controller property
iommu/arm-smmu-qcom: Add SC8280XP support
dt-bindings: arm-smmu: Add compatible for Qualcomm SC8280XP
...
100 lines
2.8 KiB
YAML
100 lines
2.8 KiB
YAML
# SPDX-License-Identifier: GPL-2.0
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/iommu/samsung,sysmmu.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Samsung Exynos IOMMU H/W, System MMU (System Memory Management Unit)
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maintainers:
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- Marek Szyprowski <m.szyprowski@samsung.com>
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description: |+
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Samsung's Exynos architecture contains System MMUs that enables scattered
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physical memory chunks visible as a contiguous region to DMA-capable peripheral
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devices like MFC, FIMC, FIMD, GScaler, FIMC-IS and so forth.
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System MMU is an IOMMU and supports identical translation table format to
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ARMv7 translation tables with minimum set of page properties including access
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permissions, shareability and security protection. In addition, System MMU has
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another capabilities like L2 TLB or block-fetch buffers to minimize translation
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latency.
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System MMUs are in many to one relation with peripheral devices, i.e. single
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peripheral device might have multiple System MMUs (usually one for each bus
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master), but one System MMU can handle transactions from only one peripheral
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device. The relation between a System MMU and the peripheral device needs to be
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defined in device node of the peripheral device.
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MFC in all Exynos SoCs and FIMD, M2M Scalers and G2D in Exynos5420 has 2 System
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MMUs.
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* MFC has one System MMU on its left and right bus.
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* FIMD in Exynos5420 has one System MMU for window 0 and 4, the other system MMU
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for window 1, 2 and 3.
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* M2M Scalers and G2D in Exynos5420 has one System MMU on the read channel and
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the other System MMU on the write channel.
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For information on assigning System MMU controller to its peripheral devices,
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see generic IOMMU bindings.
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properties:
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compatible:
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const: samsung,exynos-sysmmu
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reg:
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maxItems: 1
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interrupts:
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maxItems: 1
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clocks:
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minItems: 1
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maxItems: 2
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clock-names:
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oneOf:
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- items:
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- const: sysmmu
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- items:
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- const: sysmmu
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- const: master
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- items:
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- const: aclk
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- const: pclk
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"#iommu-cells":
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const: 0
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power-domains:
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description: |
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Required if the System MMU is needed to gate its power.
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Please refer to the following document:
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Documentation/devicetree/bindings/power/pd-samsung.yaml
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maxItems: 1
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required:
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- compatible
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- reg
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- interrupts
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- clocks
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- clock-names
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- "#iommu-cells"
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/clock/exynos5250.h>
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sysmmu_gsc0: iommu@13e80000 {
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compatible = "samsung,exynos-sysmmu";
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reg = <0x13E80000 0x1000>;
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interrupt-parent = <&combiner>;
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interrupts = <2 0>;
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clock-names = "sysmmu", "master";
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clocks = <&clock CLK_SMMU_GSCL0>,
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<&clock CLK_GSCL0>;
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power-domains = <&pd_gsc>;
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#iommu-cells = <0>;
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};
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