mirror of
https://github.com/torvalds/linux.git
synced 2026-04-30 20:42:33 -04:00
88fe301896
Document optional phandle to mmio-sram, which can describe an SRAM region used for descriptor storage instead of regular DRAM region. Use of SRAM instead of DRAM for descriptor storage may improve bus access pattern and performance. Reviewed-by: Frank Li <Frank.Li@nxp.com> Signed-off-by: Marek Vasut <marek.vasut@mailbox.org> Signed-off-by: Nicolas Dufresne <nicolas.dufresne@collabora.com> Signed-off-by: Hans Verkuil <hverkuil+cisco@kernel.org>
128 lines
3.9 KiB
YAML
128 lines
3.9 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
|
|
%YAML 1.2
|
|
---
|
|
$id: http://devicetree.org/schemas/media/nxp,imx8-jpeg.yaml#
|
|
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
|
|
|
title: i.MX8QXP/QM JPEG decoder/encoder
|
|
|
|
maintainers:
|
|
- Mirela Rabulea <mirela.rabulea@nxp.com>
|
|
|
|
description: |-
|
|
The JPEG decoder/encoder present in iMX8QXP and iMX8QM SoCs is an
|
|
ISO/IEC 10918-1 JPEG standard compliant decoder/encoder, for Baseline
|
|
and Extended Sequential DCT modes.
|
|
|
|
properties:
|
|
compatible:
|
|
oneOf:
|
|
- items:
|
|
enum:
|
|
- nxp,imx8qxp-jpgdec
|
|
- nxp,imx8qxp-jpgenc
|
|
- items:
|
|
- enum:
|
|
- nxp,imx8qm-jpgdec
|
|
- nxp,imx95-jpgdec
|
|
- const: nxp,imx8qxp-jpgdec
|
|
- items:
|
|
- enum:
|
|
- nxp,imx8qm-jpgenc
|
|
- nxp,imx95-jpgenc
|
|
- const: nxp,imx8qxp-jpgenc
|
|
|
|
reg:
|
|
maxItems: 1
|
|
|
|
clocks:
|
|
items:
|
|
- description: AXI DMA engine clock for fetching JPEG bitstream from memory (per)
|
|
- description: IP bus clock for register access (ipg)
|
|
|
|
interrupts:
|
|
description: |
|
|
There are 4 slots available in the IP, which the driver may use
|
|
If a certain slot is used, it should have an associated interrupt
|
|
The interrupt with index i is assumed to be for slot i
|
|
minItems: 1 # At least one slot is needed by the driver
|
|
maxItems: 4 # The IP has 4 slots available for use
|
|
|
|
power-domains:
|
|
description:
|
|
List of phandle and PM domain specifier as documented in
|
|
Documentation/devicetree/bindings/power/power_domain.txt
|
|
minItems: 1 # Wrapper and all slots
|
|
maxItems: 5 # Wrapper and 4 slots
|
|
|
|
sram:
|
|
$ref: /schemas/types.yaml#/definitions/phandle
|
|
description:
|
|
Optional phandle to a reserved on-chip SRAM regions. The SRAM can
|
|
be used for descriptor storage, which may improve bus utilization.
|
|
|
|
required:
|
|
- compatible
|
|
- reg
|
|
- clocks
|
|
- interrupts
|
|
- power-domains
|
|
|
|
allOf:
|
|
- if:
|
|
properties:
|
|
compatible:
|
|
contains:
|
|
enum:
|
|
- nxp,imx95-jpgenc
|
|
- nxp,imx95-jpgdec
|
|
then:
|
|
properties:
|
|
power-domains:
|
|
maxItems: 1
|
|
else:
|
|
properties:
|
|
power-domains:
|
|
minItems: 2 # Wrapper and 1 slot
|
|
|
|
additionalProperties: false
|
|
|
|
examples:
|
|
- |
|
|
#include <dt-bindings/clock/imx8-lpcg.h>
|
|
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
|
#include <dt-bindings/firmware/imx/rsrc.h>
|
|
|
|
jpegdec: jpegdec@58400000 {
|
|
compatible = "nxp,imx8qxp-jpgdec";
|
|
reg = <0x58400000 0x00050000 >;
|
|
clocks = <&img_jpeg_dec_lpcg IMX_LPCG_CLK_0>,
|
|
<&img_jpeg_dec_lpcg IMX_LPCG_CLK_4>;
|
|
interrupts = <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>;
|
|
power-domains = <&pd IMX_SC_R_MJPEG_DEC_MP>,
|
|
<&pd IMX_SC_R_MJPEG_DEC_S0>,
|
|
<&pd IMX_SC_R_MJPEG_DEC_S1>,
|
|
<&pd IMX_SC_R_MJPEG_DEC_S2>,
|
|
<&pd IMX_SC_R_MJPEG_DEC_S3>;
|
|
};
|
|
|
|
jpegenc: jpegenc@58450000 {
|
|
compatible = "nxp,imx8qm-jpgenc", "nxp,imx8qxp-jpgenc";
|
|
reg = <0x58450000 0x00050000 >;
|
|
clocks = <&img_jpeg_enc_lpcg IMX_LPCG_CLK_0>,
|
|
<&img_jpeg__lpcg IMX_LPCG_CLK_4>;
|
|
interrupts = <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>;
|
|
power-domains = <&pd IMX_SC_R_MJPEG_ENC_MP>,
|
|
<&pd IMX_SC_R_MJPEG_ENC_S0>,
|
|
<&pd IMX_SC_R_MJPEG_ENC_S1>,
|
|
<&pd IMX_SC_R_MJPEG_ENC_S2>,
|
|
<&pd IMX_SC_R_MJPEG_ENC_S3>;
|
|
};
|
|
...
|