linux/Documentation/devicetree/bindings/net/dsa/maxlinear,mxl862xx.yaml

# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/net/dsa/maxlinear,mxl862xx.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: MaxLinear MxL862xx Ethernet Switch Family

maintainers:
  - Daniel Golle <daniel@makrotopia.org>

description:
  The MaxLinear MxL862xx switch family are multi-port Ethernet switches with
  integrated 2.5GE PHYs. The MxL86252 has five PHY ports and the MxL86282
  has eight PHY ports. Both models come with two 10 Gigabit/s SerDes
  interfaces to be used to connect external PHYs or SFP cages, or as CPU
  port.

allOf:
  - $ref: dsa.yaml#/$defs/ethernet-ports

properties:
  compatible:
    enum:
      - maxlinear,mxl86252
      - maxlinear,mxl86282

  reg:
    maxItems: 1
    description: MDIO address of the switch

  mdio:
    $ref: /schemas/net/mdio.yaml#
    unevaluatedProperties: false

required:
  - compatible
  - mdio
  - reg

unevaluatedProperties: false

examples:
  - |
    mdio {
        #address-cells = <1>;
        #size-cells = <0>;

        switch@0 {
            compatible = "maxlinear,mxl86282";
            reg = <0>;

            ethernet-ports {
                #address-cells = <1>;
                #size-cells = <0>;

                /* Microcontroller port */
                port@0 {
                    reg = <0>;
                    status = "disabled";
                };

                port@1 {
                    reg = <1>;
                    phy-handle = <&phy0>;
                    phy-mode = "internal";
                };

                port@2 {
                    reg = <2>;
                    phy-handle = <&phy1>;
                    phy-mode = "internal";
                };

                port@3 {
                    reg = <3>;
                    phy-handle = <&phy2>;
                    phy-mode = "internal";
                };

                port@4 {
                    reg = <4>;
                    phy-handle = <&phy3>;
                    phy-mode = "internal";
                };

                port@5 {
                    reg = <5>;
                    phy-handle = <&phy4>;
                    phy-mode = "internal";
                };

                port@6 {
                    reg = <6>;
                    phy-handle = <&phy5>;
                    phy-mode = "internal";
                };

                port@7 {
                    reg = <7>;
                    phy-handle = <&phy6>;
                    phy-mode = "internal";
                };

                port@8 {
                    reg = <8>;
                    phy-handle = <&phy7>;
                    phy-mode = "internal";
                };

                port@9 {
                    reg = <9>;
                    label = "cpu";
                    ethernet = <&gmac0>;
                    phy-mode = "usxgmii";

                    fixed-link {
                        speed = <10000>;
                        full-duplex;
                    };
                };
            };

            mdio {
                #address-cells = <1>;
                #size-cells = <0>;

                phy0: ethernet-phy@0 {
                    reg = <0>;
                };

                phy1: ethernet-phy@1 {
                    reg = <1>;
                };

                phy2: ethernet-phy@2 {
                    reg = <2>;
                };

                phy3: ethernet-phy@3 {
                    reg = <3>;
                };

                phy4: ethernet-phy@4 {
                    reg = <4>;
                };

                phy5: ethernet-phy@5 {
                    reg = <5>;
                };

                phy6: ethernet-phy@6 {
                    reg = <6>;
                };

                phy7: ethernet-phy@7 {
                    reg = <7>;
                };
            };
        };
    };