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SM6125 is identical to SM6375 including the throttle clock that is also provided to the MDP node downstream. Note that any SoC other than SM6375 (currently SC7180 and SM6350) has an unconstrained maximum number of clocks and could either pass or leave out this "throttle" clock. Signed-off-by: Marijn Suijten <marijn.suijten@somainline.org> Patchwork: https://patchwork.freedesktop.org/patch/548972/ Link: https://lore.kernel.org/r/20230723-sm6125-dpu-v4-8-a3f287dd6c07@somainline.org Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
126 lines
2.8 KiB
YAML
126 lines
2.8 KiB
YAML
# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/display/msm/qcom,sc7180-dpu.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Qualcomm Display DPU on SC7180
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maintainers:
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- Krishna Manikandan <quic_mkrishn@quicinc.com>
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$ref: /schemas/display/msm/dpu-common.yaml#
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properties:
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compatible:
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enum:
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- qcom,sc7180-dpu
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- qcom,sm6125-dpu
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- qcom,sm6350-dpu
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- qcom,sm6375-dpu
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reg:
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items:
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- description: Address offset and size for mdp register set
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- description: Address offset and size for vbif register set
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reg-names:
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items:
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- const: mdp
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- const: vbif
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clocks:
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minItems: 6
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items:
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- description: Display hf axi clock
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- description: Display ahb clock
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- description: Display rotator clock
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- description: Display lut clock
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- description: Display core clock
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- description: Display vsync clock
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- description: Display core throttle clock
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clock-names:
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minItems: 6
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items:
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- const: bus
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- const: iface
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- const: rot
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- const: lut
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- const: core
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- const: vsync
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- const: throttle
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required:
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- compatible
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- reg
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- reg-names
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- clocks
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- clock-names
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unevaluatedProperties: false
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allOf:
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- if:
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properties:
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compatible:
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enum:
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- qcom,sm6375-dpu
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- qcom,sm6125-dpu
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then:
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properties:
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clocks:
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minItems: 7
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clock-names:
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minItems: 7
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examples:
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- |
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#include <dt-bindings/clock/qcom,dispcc-sc7180.h>
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#include <dt-bindings/clock/qcom,gcc-sc7180.h>
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#include <dt-bindings/power/qcom-rpmpd.h>
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display-controller@ae01000 {
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compatible = "qcom,sc7180-dpu";
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reg = <0x0ae01000 0x8f000>,
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<0x0aeb0000 0x2008>;
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reg-names = "mdp", "vbif";
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clocks = <&gcc GCC_DISP_HF_AXI_CLK>,
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<&dispcc DISP_CC_MDSS_AHB_CLK>,
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<&dispcc DISP_CC_MDSS_ROT_CLK>,
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<&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
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<&dispcc DISP_CC_MDSS_MDP_CLK>,
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<&dispcc DISP_CC_MDSS_VSYNC_CLK>;
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clock-names = "bus", "iface", "rot", "lut", "core",
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"vsync";
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interrupt-parent = <&mdss>;
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interrupts = <0>;
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power-domains = <&rpmhpd SC7180_CX>;
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operating-points-v2 = <&mdp_opp_table>;
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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endpoint {
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remote-endpoint = <&dsi0_in>;
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};
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};
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port@2 {
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reg = <2>;
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endpoint {
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remote-endpoint = <&dp_in>;
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};
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};
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};
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};
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...
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