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Currently we do not differentiate between the various users of the qcom,mdss-dsi-ctrl. The driver is flexible enough to operate from one compatible string but, the hardware does have some significant differences in the number of clocks. To facilitate documenting the clocks add the following compatible strings - qcom,apq8064-dsi-ctrl - qcom,msm8916-dsi-ctrl - qcom,msm8953-dsi-ctrl - qcom,msm8974-dsi-ctrl - qcom,msm8996-dsi-ctrl - qcom,msm8998-dsi-ctrl - qcom,sc7180-dsi-ctrl - qcom,sc7280-dsi-ctrl - qcom,sdm660-dsi-ctrl - qcom,sdm845-dsi-ctrl - qcom,sm8150-dsi-ctrl - qcom,sm8250-dsi-ctrl - qcom,sm8350-dsi-ctrl - qcom,sm8450-dsi-ctrl - qcom,sm8550-dsi-ctrl - qcom,qcm2290-dsi-ctrl Deprecate qcom,dsi-ctrl-6g-qcm2290 in favour of the desired format while we do so. Several MDSS yaml files exist which document the dsi sub-node. For each existing SoC MDSS yaml, provide the right dsi compat string. Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Patchwork: https://patchwork.freedesktop.org/patch/519078/ Link: https://lore.kernel.org/r/20230118171621.102694-2-bryan.odonoghue@linaro.org Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
281 lines
7.9 KiB
YAML
281 lines
7.9 KiB
YAML
# SPDX-License-Identifier: GPL-2.0-only or BSD-2-Clause
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/display/msm/qcom,sdm845-mdss.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Qualcomm SDM845 Display MDSS
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maintainers:
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- Krishna Manikandan <quic_mkrishn@quicinc.com>
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description:
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Device tree bindings for MSM Mobile Display Subsystem(MDSS) that encapsulates
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sub-blocks like DPU display controller, DSI and DP interfaces etc. Device tree
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bindings of MDSS are mentioned for SDM845 target.
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$ref: /schemas/display/msm/mdss-common.yaml#
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properties:
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compatible:
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const: qcom,sdm845-mdss
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clocks:
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items:
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- description: Display AHB clock from gcc
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- description: Display core clock
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clock-names:
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items:
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- const: iface
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- const: core
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iommus:
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maxItems: 2
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interconnects:
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maxItems: 2
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interconnect-names:
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maxItems: 2
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patternProperties:
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"^display-controller@[0-9a-f]+$":
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type: object
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properties:
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compatible:
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const: qcom,sdm845-dpu
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"^displayport-controller@[0-9a-f]+$":
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type: object
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properties:
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compatible:
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const: qcom,sdm845-dp
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"^dsi@[0-9a-f]+$":
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type: object
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properties:
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compatible:
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items:
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- const: qcom,sdm845-dsi-ctrl
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- const: qcom,mdss-dsi-ctrl
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"^phy@[0-9a-f]+$":
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type: object
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properties:
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compatible:
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const: qcom,dsi-phy-10nm
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required:
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- compatible
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unevaluatedProperties: false
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examples:
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- |
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#include <dt-bindings/clock/qcom,dispcc-sdm845.h>
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#include <dt-bindings/clock/qcom,gcc-sdm845.h>
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#include <dt-bindings/clock/qcom,rpmh.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/power/qcom-rpmpd.h>
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display-subsystem@ae00000 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "qcom,sdm845-mdss";
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reg = <0x0ae00000 0x1000>;
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reg-names = "mdss";
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power-domains = <&dispcc MDSS_GDSC>;
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clocks = <&gcc GCC_DISP_AHB_CLK>,
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<&dispcc DISP_CC_MDSS_MDP_CLK>;
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clock-names = "iface", "core";
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interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-controller;
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#interrupt-cells = <1>;
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iommus = <&apps_smmu 0x880 0x8>,
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<&apps_smmu 0xc80 0x8>;
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ranges;
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display-controller@ae01000 {
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compatible = "qcom,sdm845-dpu";
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reg = <0x0ae01000 0x8f000>,
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<0x0aeb0000 0x2008>;
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reg-names = "mdp", "vbif";
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clocks = <&gcc GCC_DISP_AXI_CLK>,
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<&dispcc DISP_CC_MDSS_AHB_CLK>,
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<&dispcc DISP_CC_MDSS_AXI_CLK>,
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<&dispcc DISP_CC_MDSS_MDP_CLK>,
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<&dispcc DISP_CC_MDSS_VSYNC_CLK>;
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clock-names = "gcc-bus", "iface", "bus", "core", "vsync";
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interrupt-parent = <&mdss>;
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interrupts = <0>;
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power-domains = <&rpmhpd SDM845_CX>;
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operating-points-v2 = <&mdp_opp_table>;
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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dpu_intf1_out: endpoint {
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remote-endpoint = <&dsi0_in>;
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};
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};
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port@1 {
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reg = <1>;
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dpu_intf2_out: endpoint {
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remote-endpoint = <&dsi1_in>;
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};
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};
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};
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};
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dsi@ae94000 {
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compatible = "qcom,sdm845-dsi-ctrl", "qcom,mdss-dsi-ctrl";
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reg = <0x0ae94000 0x400>;
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reg-names = "dsi_ctrl";
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interrupt-parent = <&mdss>;
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interrupts = <4>;
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clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
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<&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
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<&dispcc DISP_CC_MDSS_PCLK0_CLK>,
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<&dispcc DISP_CC_MDSS_ESC0_CLK>,
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<&dispcc DISP_CC_MDSS_AHB_CLK>,
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<&dispcc DISP_CC_MDSS_AXI_CLK>;
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clock-names = "byte",
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"byte_intf",
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"pixel",
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"core",
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"iface",
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"bus";
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assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>,
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<&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
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assigned-clock-parents = <&dsi0_phy 0>, <&dsi0_phy 1>;
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operating-points-v2 = <&dsi_opp_table>;
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power-domains = <&rpmhpd SDM845_CX>;
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phys = <&dsi0_phy>;
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phy-names = "dsi";
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#address-cells = <1>;
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#size-cells = <0>;
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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dsi0_in: endpoint {
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remote-endpoint = <&dpu_intf1_out>;
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};
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};
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port@1 {
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reg = <1>;
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dsi0_out: endpoint {
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};
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};
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};
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};
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dsi0_phy: phy@ae94400 {
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compatible = "qcom,dsi-phy-10nm";
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reg = <0x0ae94400 0x200>,
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<0x0ae94600 0x280>,
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<0x0ae94a00 0x1e0>;
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reg-names = "dsi_phy",
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"dsi_phy_lane",
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"dsi_pll";
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#clock-cells = <1>;
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#phy-cells = <0>;
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clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
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<&rpmhcc RPMH_CXO_CLK>;
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clock-names = "iface", "ref";
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vdds-supply = <&vreg_dsi_phy>;
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};
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dsi@ae96000 {
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compatible = "qcom,sdm845-dsi-ctrl", "qcom,mdss-dsi-ctrl";
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reg = <0x0ae96000 0x400>;
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reg-names = "dsi_ctrl";
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interrupt-parent = <&mdss>;
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interrupts = <5>;
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clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>,
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<&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>,
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<&dispcc DISP_CC_MDSS_PCLK1_CLK>,
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<&dispcc DISP_CC_MDSS_ESC1_CLK>,
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<&dispcc DISP_CC_MDSS_AHB_CLK>,
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<&dispcc DISP_CC_MDSS_AXI_CLK>;
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clock-names = "byte",
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"byte_intf",
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"pixel",
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"core",
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"iface",
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"bus";
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assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>,
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<&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>;
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assigned-clock-parents = <&dsi1_phy 0>, <&dsi1_phy 1>;
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operating-points-v2 = <&dsi_opp_table>;
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power-domains = <&rpmhpd SDM845_CX>;
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phys = <&dsi1_phy>;
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phy-names = "dsi";
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#address-cells = <1>;
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#size-cells = <0>;
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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dsi1_in: endpoint {
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remote-endpoint = <&dpu_intf2_out>;
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};
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};
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port@1 {
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reg = <1>;
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dsi1_out: endpoint {
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};
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};
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};
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};
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dsi1_phy: phy@ae96400 {
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compatible = "qcom,dsi-phy-10nm";
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reg = <0x0ae96400 0x200>,
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<0x0ae96600 0x280>,
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<0x0ae96a00 0x10e>;
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reg-names = "dsi_phy",
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"dsi_phy_lane",
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"dsi_pll";
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#clock-cells = <1>;
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#phy-cells = <0>;
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clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
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<&rpmhcc RPMH_CXO_CLK>;
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clock-names = "iface", "ref";
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vdds-supply = <&vreg_dsi_phy>;
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};
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};
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...
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