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Document the cadence qspi controller compatible for AMD Pensando Elba SoC boards. The Elba qspi fifo size is 1024. Signed-off-by: Brad Larson <blarson@amd.com Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org Link: https://lore.kernel.org/r/20230515181606.65953-3-blarson@amd.com Signed-off-by: Mark Brown <broonie@kernel.org
167 lines
3.5 KiB
YAML
167 lines
3.5 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/spi/cdns,qspi-nor.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Cadence Quad SPI controller
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maintainers:
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- Vaishnav Achath <vaishnav.a@ti.com>
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allOf:
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- $ref: spi-controller.yaml#
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- if:
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properties:
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compatible:
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contains:
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const: xlnx,versal-ospi-1.0
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then:
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required:
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- power-domains
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- if:
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properties:
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compatible:
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contains:
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const: starfive,jh7110-qspi
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then:
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properties:
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resets:
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minItems: 2
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maxItems: 3
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reset-names:
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minItems: 2
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maxItems: 3
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items:
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enum: [ qspi, qspi-ocp, rstc_ref ]
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else:
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properties:
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resets:
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maxItems: 2
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reset-names:
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minItems: 1
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maxItems: 2
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items:
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enum: [ qspi, qspi-ocp ]
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- if:
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properties:
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compatible:
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contains:
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const: amd,pensando-elba-qspi
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then:
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properties:
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cdns,fifo-depth:
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enum: [ 128, 256, 1024 ]
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default: 1024
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else:
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properties:
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cdns,fifo-depth:
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enum: [ 128, 256 ]
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default: 128
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properties:
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compatible:
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oneOf:
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- items:
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- enum:
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- amd,pensando-elba-qspi
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- ti,k2g-qspi
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- ti,am654-ospi
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- intel,lgm-qspi
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- xlnx,versal-ospi-1.0
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- intel,socfpga-qspi
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- starfive,jh7110-qspi
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- const: cdns,qspi-nor
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- const: cdns,qspi-nor
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reg:
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items:
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- description: the controller register set
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- description: the controller data area
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interrupts:
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maxItems: 1
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clocks:
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maxItems: 1
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cdns,fifo-depth:
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description:
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Size of the data FIFO in words.
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$ref: /schemas/types.yaml#/definitions/uint32
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cdns,fifo-width:
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$ref: /schemas/types.yaml#/definitions/uint32
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description:
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Bus width of the data FIFO in bytes.
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default: 4
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cdns,trigger-address:
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$ref: /schemas/types.yaml#/definitions/uint32
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description:
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32-bit indirect AHB trigger address.
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cdns,is-decoded-cs:
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type: boolean
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description:
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Flag to indicate whether decoder is used to select different chip select
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for different memory regions.
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cdns,rclk-en:
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type: boolean
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description:
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Flag to indicate that QSPI return clock is used to latch the read
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data rather than the QSPI clock. Make sure that QSPI return clock
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is populated on the board before using this property.
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power-domains:
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maxItems: 1
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resets:
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minItems: 2
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maxItems: 3
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reset-names:
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minItems: 2
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maxItems: 3
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items:
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enum: [ qspi, qspi-ocp, rstc_ref ]
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required:
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- compatible
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- reg
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- interrupts
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- clocks
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- cdns,fifo-depth
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- cdns,fifo-width
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- cdns,trigger-address
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- '#address-cells'
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- '#size-cells'
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unevaluatedProperties: false
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examples:
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- |
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qspi: spi@ff705000 {
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compatible = "cdns,qspi-nor";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0xff705000 0x1000>,
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<0xffa00000 0x1000>;
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interrupts = <0 151 4>;
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clocks = <&qspi_clk>;
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cdns,fifo-depth = <128>;
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cdns,fifo-width = <4>;
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cdns,trigger-address = <0x00000000>;
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resets = <&rst 0x1>, <&rst 0x2>;
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reset-names = "qspi", "qspi-ocp";
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flash@0 {
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compatible = "jedec,spi-nor";
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reg = <0x0>;
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};
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};
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