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df41742343
Add timer test case based on common arch_timer code, timer interrupt with one-shot and period mode is tested. Signed-off-by: Bibo Mao <maobibo@loongson.cn> Signed-off-by: Huacai Chen <chenhuacai@loongson.cn>
86 lines
1.7 KiB
C
86 lines
1.7 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* LoongArch Constant Timer specific interface
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*/
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#ifndef SELFTEST_KVM_ARCH_TIMER_H
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#define SELFTEST_KVM_ARCH_TIMER_H
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#include "processor.h"
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/* LoongArch timer frequency is constant 100MHZ */
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#define TIMER_FREQ (100UL << 20)
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#define msec_to_cycles(msec) (TIMER_FREQ * (unsigned long)(msec) / 1000)
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#define usec_to_cycles(usec) (TIMER_FREQ * (unsigned long)(usec) / 1000000)
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#define cycles_to_usec(cycles) ((unsigned long)(cycles) * 1000000 / TIMER_FREQ)
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static inline unsigned long timer_get_cycles(void)
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{
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unsigned long val = 0;
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__asm__ __volatile__(
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"rdtime.d %0, $zero\n\t"
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: "=r"(val)
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:
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);
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return val;
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}
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static inline unsigned long timer_get_cfg(void)
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{
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return csr_read(LOONGARCH_CSR_TCFG);
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}
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static inline unsigned long timer_get_val(void)
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{
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return csr_read(LOONGARCH_CSR_TVAL);
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}
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static inline void disable_timer(void)
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{
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csr_write(0, LOONGARCH_CSR_TCFG);
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}
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static inline void timer_irq_enable(void)
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{
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unsigned long val;
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val = csr_read(LOONGARCH_CSR_ECFG);
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val |= ECFGF_TIMER;
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csr_write(val, LOONGARCH_CSR_ECFG);
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}
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static inline void timer_irq_disable(void)
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{
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unsigned long val;
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val = csr_read(LOONGARCH_CSR_ECFG);
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val &= ~ECFGF_TIMER;
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csr_write(val, LOONGARCH_CSR_ECFG);
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}
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static inline void timer_set_next_cmp_ms(unsigned int msec, bool period)
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{
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unsigned long val;
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val = msec_to_cycles(msec) & CSR_TCFG_VAL;
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val |= CSR_TCFG_EN;
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if (period)
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val |= CSR_TCFG_PERIOD;
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csr_write(val, LOONGARCH_CSR_TCFG);
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}
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static inline void __delay(uint64_t cycles)
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{
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uint64_t start = timer_get_cycles();
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while ((timer_get_cycles() - start) < cycles)
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cpu_relax();
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}
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static inline void udelay(unsigned long usec)
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{
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__delay(usec_to_cycles(usec));
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}
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#endif /* SELFTEST_KVM_ARCH_TIMER_H */
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