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MMIO_REMAP (HDP flush page) exposes a hardware MMIO register window via a PCI BAR; there are no struct pages backing it (not normal RAM). But when one device shares memory with another through dma-buf, the receiver still expects a delivery route—a list of DMA-able chunks—called an sg_table. For the BAR window, we can’t (no pages!), so we instead create a one-entry list that points directly to the BAR’s physical bus address and tell DMA: “use this I/O span.” - A single, contiguous byte range on the PCI bus (start DMA address + length)). That’s why we map it with dma_map_resource() and set sg_set_page(..., NULL, ...). Perform DMA reads/writes directly to that range so we build an sg_table from a BAR physical span and map it with dma_map_resource(). This patch centralizes the BAR-I/O mapping in TTM and wires dma-buf to it: Add amdgpu_ttm_mmio_remap_alloc_sgt() / amdgpu_ttm_mmio_remap_free_sgt(). They walk the TTM resource via amdgpu_res_cursor, add the byte offset to adev->rmmio_remap.bus_addr, build a one-entry sg_table with sg_set_page(NULL, …), and map/unmap it with dma_map_resource(). In dma-buf map/unmap, if the BO is in AMDGPU_PL_MMIO_REMAP, call the new helpers. Single place for BAR-I/O handling: amdgpu_ttm.c in amdgpu_ttm_mmio_remap_alloc_sgt() and ..._free_sgt(). No struct pages: sg_set_page(sg, NULL, cur.size, 0); inside amdgpu_ttm_mmio_remap_alloc_sgt(). Minimal sg_table: sg_alloc_table(*sgt, 1, GFP_KERNEL); inside amdgpu_ttm_mmio_remap_alloc_sgt(). Hooked into dma-buf: amdgpu_dma_buf_map()/unmap() in amdgpu_dma_buf.c call these helpers for AMDGPU_PL_MMIO_REMAP. v2: squash in fix for set/get tiling Suggested-by: Christian König <christian.koenig@amd.com> Cc: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Srinivasan Shanmugam <srinivasan.shanmugam@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
226 lines
8.1 KiB
C
226 lines
8.1 KiB
C
/*
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* Copyright 2016 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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#ifndef __AMDGPU_TTM_H__
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#define __AMDGPU_TTM_H__
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#include <linux/dma-direction.h>
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#include <drm/gpu_scheduler.h>
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#include <drm/ttm/ttm_placement.h>
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#include "amdgpu_vram_mgr.h"
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#include "amdgpu_hmm.h"
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#define AMDGPU_PL_GDS (TTM_PL_PRIV + 0)
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#define AMDGPU_PL_GWS (TTM_PL_PRIV + 1)
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#define AMDGPU_PL_OA (TTM_PL_PRIV + 2)
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#define AMDGPU_PL_PREEMPT (TTM_PL_PRIV + 3)
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#define AMDGPU_PL_DOORBELL (TTM_PL_PRIV + 4)
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#define AMDGPU_PL_MMIO_REMAP (TTM_PL_PRIV + 5)
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#define __AMDGPU_PL_NUM (TTM_PL_PRIV + 6)
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#define AMDGPU_GTT_MAX_TRANSFER_SIZE 512
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#define AMDGPU_GTT_NUM_TRANSFER_WINDOWS 2
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extern const struct attribute_group amdgpu_vram_mgr_attr_group;
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extern const struct attribute_group amdgpu_gtt_mgr_attr_group;
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struct hmm_range;
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struct amdgpu_gtt_mgr {
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struct ttm_resource_manager manager;
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struct drm_mm mm;
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spinlock_t lock;
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};
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struct amdgpu_mman {
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struct ttm_device bdev;
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struct ttm_pool *ttm_pools;
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bool initialized;
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void __iomem *aper_base_kaddr;
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/* buffer handling */
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const struct amdgpu_buffer_funcs *buffer_funcs;
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struct amdgpu_ring *buffer_funcs_ring;
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bool buffer_funcs_enabled;
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struct mutex gtt_window_lock;
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/* High priority scheduler entity for buffer moves */
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struct drm_sched_entity high_pr;
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/* Low priority scheduler entity for VRAM clearing */
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struct drm_sched_entity low_pr;
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struct amdgpu_vram_mgr vram_mgr;
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struct amdgpu_gtt_mgr gtt_mgr;
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struct ttm_resource_manager preempt_mgr;
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uint64_t stolen_vga_size;
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struct amdgpu_bo *stolen_vga_memory;
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uint64_t stolen_extended_size;
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struct amdgpu_bo *stolen_extended_memory;
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bool keep_stolen_vga_memory;
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struct amdgpu_bo *stolen_reserved_memory;
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uint64_t stolen_reserved_offset;
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uint64_t stolen_reserved_size;
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/* fw reserved memory */
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struct amdgpu_bo *fw_reserved_memory;
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struct amdgpu_bo *fw_reserved_memory_extend;
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/* firmware VRAM reservation */
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u64 fw_vram_usage_start_offset;
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u64 fw_vram_usage_size;
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struct amdgpu_bo *fw_vram_usage_reserved_bo;
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void *fw_vram_usage_va;
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/* driver VRAM reservation */
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u64 drv_vram_usage_start_offset;
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u64 drv_vram_usage_size;
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struct amdgpu_bo *drv_vram_usage_reserved_bo;
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void *drv_vram_usage_va;
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/* PAGE_SIZE'd BO for process memory r/w over SDMA. */
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struct amdgpu_bo *sdma_access_bo;
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void *sdma_access_ptr;
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};
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struct amdgpu_copy_mem {
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struct ttm_buffer_object *bo;
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struct ttm_resource *mem;
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unsigned long offset;
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};
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#define AMDGPU_COPY_FLAGS_TMZ (1 << 0)
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#define AMDGPU_COPY_FLAGS_READ_DECOMPRESSED (1 << 1)
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#define AMDGPU_COPY_FLAGS_WRITE_COMPRESSED (1 << 2)
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#define AMDGPU_COPY_FLAGS_MAX_COMPRESSED_SHIFT 3
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#define AMDGPU_COPY_FLAGS_MAX_COMPRESSED_MASK 0x03
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#define AMDGPU_COPY_FLAGS_NUMBER_TYPE_SHIFT 5
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#define AMDGPU_COPY_FLAGS_NUMBER_TYPE_MASK 0x07
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#define AMDGPU_COPY_FLAGS_DATA_FORMAT_SHIFT 8
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#define AMDGPU_COPY_FLAGS_DATA_FORMAT_MASK 0x3f
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#define AMDGPU_COPY_FLAGS_WRITE_COMPRESS_DISABLE_SHIFT 14
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#define AMDGPU_COPY_FLAGS_WRITE_COMPRESS_DISABLE_MASK 0x1
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#define AMDGPU_COPY_FLAGS_SET(field, value) \
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(((__u32)(value) & AMDGPU_COPY_FLAGS_##field##_MASK) << AMDGPU_COPY_FLAGS_##field##_SHIFT)
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#define AMDGPU_COPY_FLAGS_GET(value, field) \
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(((__u32)(value) >> AMDGPU_COPY_FLAGS_##field##_SHIFT) & AMDGPU_COPY_FLAGS_##field##_MASK)
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int amdgpu_gtt_mgr_init(struct amdgpu_device *adev, uint64_t gtt_size);
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void amdgpu_gtt_mgr_fini(struct amdgpu_device *adev);
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int amdgpu_preempt_mgr_init(struct amdgpu_device *adev);
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void amdgpu_preempt_mgr_fini(struct amdgpu_device *adev);
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int amdgpu_vram_mgr_init(struct amdgpu_device *adev);
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void amdgpu_vram_mgr_fini(struct amdgpu_device *adev);
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bool amdgpu_gtt_mgr_has_gart_addr(struct ttm_resource *mem);
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void amdgpu_gtt_mgr_recover(struct amdgpu_gtt_mgr *mgr);
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uint64_t amdgpu_preempt_mgr_usage(struct ttm_resource_manager *man);
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u64 amdgpu_vram_mgr_bo_visible_size(struct amdgpu_bo *bo);
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int amdgpu_vram_mgr_alloc_sgt(struct amdgpu_device *adev,
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struct ttm_resource *mem,
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u64 offset, u64 size,
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struct device *dev,
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enum dma_data_direction dir,
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struct sg_table **sgt);
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void amdgpu_vram_mgr_free_sgt(struct device *dev,
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enum dma_data_direction dir,
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struct sg_table *sgt);
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uint64_t amdgpu_vram_mgr_vis_usage(struct amdgpu_vram_mgr *mgr);
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int amdgpu_vram_mgr_reserve_range(struct amdgpu_vram_mgr *mgr,
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uint64_t start, uint64_t size);
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int amdgpu_vram_mgr_query_page_status(struct amdgpu_vram_mgr *mgr,
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uint64_t start);
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void amdgpu_vram_mgr_clear_reset_blocks(struct amdgpu_device *adev);
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bool amdgpu_res_cpu_visible(struct amdgpu_device *adev,
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struct ttm_resource *res);
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int amdgpu_ttm_init(struct amdgpu_device *adev);
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void amdgpu_ttm_fini(struct amdgpu_device *adev);
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void amdgpu_ttm_set_buffer_funcs_status(struct amdgpu_device *adev,
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bool enable);
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int amdgpu_copy_buffer(struct amdgpu_ring *ring, uint64_t src_offset,
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uint64_t dst_offset, uint32_t byte_count,
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struct dma_resv *resv,
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struct dma_fence **fence, bool direct_submit,
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bool vm_needs_flush, uint32_t copy_flags);
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int amdgpu_ttm_clear_buffer(struct amdgpu_bo *bo,
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struct dma_resv *resv,
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struct dma_fence **fence);
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int amdgpu_fill_buffer(struct amdgpu_bo *bo,
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uint32_t src_data,
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struct dma_resv *resv,
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struct dma_fence **fence,
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bool delayed,
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u64 k_job_id);
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int amdgpu_ttm_alloc_gart(struct ttm_buffer_object *bo);
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void amdgpu_ttm_recover_gart(struct ttm_buffer_object *tbo);
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uint64_t amdgpu_ttm_domain_start(struct amdgpu_device *adev, uint32_t type);
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#if IS_ENABLED(CONFIG_DRM_AMDGPU_USERPTR)
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int amdgpu_ttm_tt_get_user_pages(struct amdgpu_bo *bo,
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struct amdgpu_hmm_range *range);
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#else
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static inline int amdgpu_ttm_tt_get_user_pages(struct amdgpu_bo *bo,
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struct amdgpu_hmm_range *range)
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{
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return -EPERM;
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}
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#endif
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void amdgpu_ttm_tt_set_user_pages(struct ttm_tt *ttm, struct amdgpu_hmm_range *range);
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int amdgpu_ttm_tt_get_userptr(const struct ttm_buffer_object *tbo,
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uint64_t *user_addr);
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int amdgpu_ttm_tt_set_userptr(struct ttm_buffer_object *bo,
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uint64_t addr, uint32_t flags);
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bool amdgpu_ttm_tt_has_userptr(struct ttm_tt *ttm);
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struct mm_struct *amdgpu_ttm_tt_get_usermm(struct ttm_tt *ttm);
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bool amdgpu_ttm_tt_affect_userptr(struct ttm_tt *ttm, unsigned long start,
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unsigned long end, unsigned long *userptr);
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bool amdgpu_ttm_tt_userptr_invalidated(struct ttm_tt *ttm,
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int *last_invalidated);
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bool amdgpu_ttm_tt_is_userptr(struct ttm_tt *ttm);
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bool amdgpu_ttm_tt_is_readonly(struct ttm_tt *ttm);
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uint64_t amdgpu_ttm_tt_pde_flags(struct ttm_tt *ttm, struct ttm_resource *mem);
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uint64_t amdgpu_ttm_tt_pte_flags(struct amdgpu_device *adev, struct ttm_tt *ttm,
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struct ttm_resource *mem);
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int amdgpu_ttm_evict_resources(struct amdgpu_device *adev, int mem_type);
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void amdgpu_ttm_debugfs_init(struct amdgpu_device *adev);
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int amdgpu_ttm_mmio_remap_alloc_sgt(struct amdgpu_device *adev,
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struct ttm_resource *res,
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struct device *dev,
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enum dma_data_direction dir,
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struct sg_table **sgt);
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void amdgpu_ttm_mmio_remap_free_sgt(struct device *dev,
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enum dma_data_direction dir,
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struct sg_table *sgt);
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#endif
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