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The A31's display pipeline has 2 frontends, 2 backends, and 2 TCONs. It also has new display enhancement blocks, such as the DRC (Dynamic Range Controller), the DEU (Display Enhancement Unit), and the CMU (Color Management Unit). It supports HDMI, MIPI DSI, and 2 LCD/LVDS channels. The A31s display pipeline is almost the same, just without MIPI DSI. Only the TCON seems to be different, due to the missing mux for MIPI DSI. Add compatible strings for both of them. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
306 lines
8.1 KiB
Plaintext
306 lines
8.1 KiB
Plaintext
Allwinner A10 Display Pipeline
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==============================
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The Allwinner A10 Display pipeline is composed of several components
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that are going to be documented below:
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TV Encoder
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----------
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The TV Encoder supports the composite and VGA output. It is one end of
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the pipeline.
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Required properties:
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- compatible: value should be "allwinner,sun4i-a10-tv-encoder".
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- reg: base address and size of memory-mapped region
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- clocks: the clocks driving the TV encoder
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- resets: phandle to the reset controller driving the encoder
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- ports: A ports node with endpoint definitions as defined in
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Documentation/devicetree/bindings/media/video-interfaces.txt. The
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first port should be the input endpoint.
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TCON
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----
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The TCON acts as a timing controller for RGB, LVDS and TV interfaces.
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Required properties:
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- compatible: value must be either:
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* allwinner,sun5i-a13-tcon
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* allwinner,sun6i-a31-tcon
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* allwinner,sun6i-a31s-tcon
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* allwinner,sun8i-a33-tcon
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- reg: base address and size of memory-mapped region
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- interrupts: interrupt associated to this IP
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- clocks: phandles to the clocks feeding the TCON. Three are needed:
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- 'ahb': the interface clocks
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- 'tcon-ch0': The clock driving the TCON channel 0
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- resets: phandles to the reset controllers driving the encoder
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- "lcd": the reset line for the TCON channel 0
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- clock-names: the clock names mentioned above
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- reset-names: the reset names mentioned above
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- clock-output-names: Name of the pixel clock created
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- ports: A ports node with endpoint definitions as defined in
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Documentation/devicetree/bindings/media/video-interfaces.txt. The
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first port should be the input endpoint, the second one the output
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The output should have two endpoints. The first is the block
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connected to the TCON channel 0 (usually a panel or a bridge), the
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second the block connected to the TCON channel 1 (usually the TV
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encoder)
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On SoCs other than the A33, there is one more clock required:
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- 'tcon-ch1': The clock driving the TCON channel 1
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DRC
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---
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The DRC (Dynamic Range Controller), found in the latest Allwinner SoCs
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(A31, A23, A33), allows to dynamically adjust pixel
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brightness/contrast based on histogram measurements for LCD content
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adaptive backlight control.
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Required properties:
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- compatible: value must be one of:
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* allwinner,sun6i-a31-drc
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* allwinner,sun6i-a31s-drc
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* allwinner,sun8i-a33-drc
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- reg: base address and size of the memory-mapped region.
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- interrupts: interrupt associated to this IP
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- clocks: phandles to the clocks feeding the DRC
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* ahb: the DRC interface clock
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* mod: the DRC module clock
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* ram: the DRC DRAM clock
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- clock-names: the clock names mentioned above
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- resets: phandles to the reset line driving the DRC
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- ports: A ports node with endpoint definitions as defined in
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Documentation/devicetree/bindings/media/video-interfaces.txt. The
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first port should be the input endpoints, the second one the outputs
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Display Engine Backend
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----------------------
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The display engine backend exposes layers and sprites to the
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system.
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Required properties:
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- compatible: value must be one of:
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* allwinner,sun5i-a13-display-backend
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* allwinner,sun6i-a31-display-backend
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* allwinner,sun8i-a33-display-backend
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- reg: base address and size of the memory-mapped region.
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- clocks: phandles to the clocks feeding the frontend and backend
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* ahb: the backend interface clock
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* mod: the backend module clock
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* ram: the backend DRAM clock
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- clock-names: the clock names mentioned above
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- resets: phandles to the reset controllers driving the backend
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- ports: A ports node with endpoint definitions as defined in
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Documentation/devicetree/bindings/media/video-interfaces.txt. The
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first port should be the input endpoints, the second one the output
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On the A33, some additional properties are required:
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- reg needs to have an additional region corresponding to the SAT
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- reg-names need to be set, with "be" and "sat"
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- clocks and clock-names need to have a phandle to the SAT bus
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clocks, whose name will be "sat"
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- resets and reset-names need to have a phandle to the SAT bus
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resets, whose name will be "sat"
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Display Engine Frontend
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-----------------------
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The display engine frontend does formats conversion, scaling,
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deinterlacing and color space conversion.
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Required properties:
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- compatible: value must be one of:
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* allwinner,sun5i-a13-display-frontend
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* allwinner,sun6i-a31-display-frontend
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* allwinner,sun8i-a33-display-frontend
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- reg: base address and size of the memory-mapped region.
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- interrupts: interrupt associated to this IP
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- clocks: phandles to the clocks feeding the frontend and backend
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* ahb: the backend interface clock
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* mod: the backend module clock
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* ram: the backend DRAM clock
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- clock-names: the clock names mentioned above
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- resets: phandles to the reset controllers driving the backend
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- ports: A ports node with endpoint definitions as defined in
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Documentation/devicetree/bindings/media/video-interfaces.txt. The
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first port should be the input endpoints, the second one the outputs
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Display Engine Pipeline
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-----------------------
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The display engine pipeline (and its entry point, since it can be
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either directly the backend or the frontend) is represented as an
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extra node.
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Required properties:
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- compatible: value must be one of:
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* allwinner,sun5i-a13-display-engine
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* allwinner,sun6i-a31-display-engine
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* allwinner,sun6i-a31s-display-engine
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* allwinner,sun8i-a33-display-engine
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- allwinner,pipelines: list of phandle to the display engine
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frontends available.
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Example:
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panel: panel {
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compatible = "olimex,lcd-olinuxino-43-ts";
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#address-cells = <1>;
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#size-cells = <0>;
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port {
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#address-cells = <1>;
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#size-cells = <0>;
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panel_input: endpoint {
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remote-endpoint = <&tcon0_out_panel>;
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};
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};
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};
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tve0: tv-encoder@01c0a000 {
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compatible = "allwinner,sun4i-a10-tv-encoder";
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reg = <0x01c0a000 0x1000>;
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clocks = <&ahb_gates 34>;
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resets = <&tcon_ch0_clk 0>;
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port {
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#address-cells = <1>;
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#size-cells = <0>;
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tve0_in_tcon0: endpoint@0 {
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reg = <0>;
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remote-endpoint = <&tcon0_out_tve0>;
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};
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};
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};
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tcon0: lcd-controller@1c0c000 {
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compatible = "allwinner,sun5i-a13-tcon";
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reg = <0x01c0c000 0x1000>;
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interrupts = <44>;
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resets = <&tcon_ch0_clk 1>;
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reset-names = "lcd";
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clocks = <&ahb_gates 36>,
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<&tcon_ch0_clk>,
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<&tcon_ch1_clk>;
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clock-names = "ahb",
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"tcon-ch0",
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"tcon-ch1";
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clock-output-names = "tcon-pixel-clock";
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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tcon0_in: port@0 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0>;
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tcon0_in_be0: endpoint@0 {
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reg = <0>;
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remote-endpoint = <&be0_out_tcon0>;
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};
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};
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tcon0_out: port@1 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <1>;
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tcon0_out_panel: endpoint@0 {
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reg = <0>;
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remote-endpoint = <&panel_input>;
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};
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tcon0_out_tve0: endpoint@1 {
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reg = <1>;
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remote-endpoint = <&tve0_in_tcon0>;
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};
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};
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};
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};
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fe0: display-frontend@1e00000 {
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compatible = "allwinner,sun5i-a13-display-frontend";
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reg = <0x01e00000 0x20000>;
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interrupts = <47>;
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clocks = <&ahb_gates 46>, <&de_fe_clk>,
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<&dram_gates 25>;
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clock-names = "ahb", "mod",
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"ram";
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resets = <&de_fe_clk>;
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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fe0_out: port@1 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <1>;
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fe0_out_be0: endpoint {
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remote-endpoint = <&be0_in_fe0>;
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};
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};
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};
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};
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be0: display-backend@1e60000 {
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compatible = "allwinner,sun5i-a13-display-backend";
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reg = <0x01e60000 0x10000>;
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clocks = <&ahb_gates 44>, <&de_be_clk>,
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<&dram_gates 26>;
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clock-names = "ahb", "mod",
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"ram";
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resets = <&de_be_clk>;
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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be0_in: port@0 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0>;
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be0_in_fe0: endpoint@0 {
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reg = <0>;
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remote-endpoint = <&fe0_out_be0>;
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};
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};
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be0_out: port@1 {
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <1>;
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be0_out_tcon0: endpoint@0 {
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reg = <0>;
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remote-endpoint = <&tcon0_in_be0>;
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};
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};
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};
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};
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display-engine {
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compatible = "allwinner,sun5i-a13-display-engine";
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allwinner,pipelines = <&fe0>;
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};
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