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7f5ff740ce
Towards the end goal of making all CXL RAS capability handling uniform across host bridge ports, upstream switch ports, and endpoint ports, move dport RAS setup. Move it to cxl_switch_port_probe() context for switch / VH dports (via cxl_port_add_dport()) and cxl_endpoint_port_probe() context for an RCH dport. Rename the RAS setup helper to devm_cxl_dport_ras_setup() for symmetry with devm_cxl_switch_port_decoders_setup(). Only the RCH version needs to be exported and the cxl_test mocking can be deleted with a dev_is_pci() check on the dport_dev. Reviewed-by: Dave Jiang <dave.jiang@intel.com> Reviewed-by: Jonathan Cameron <jonathan.cameron@huawei.com> Tested-by: Terry Bowman <terry.bowman@amd.com> Signed-off-by: Dan Williams <dan.j.williams@intel.com> Link: https://patch.msgid.link/20260131000403.2135324-7-dan.j.williams@intel.com Signed-off-by: Dave Jiang <dave.jiang@intel.com>
75 lines
2.3 KiB
Makefile
75 lines
2.3 KiB
Makefile
# SPDX-License-Identifier: GPL-2.0
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ldflags-y += --wrap=acpi_table_parse_cedt
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ldflags-y += --wrap=is_acpi_device_node
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ldflags-y += --wrap=acpi_evaluate_integer
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ldflags-y += --wrap=acpi_pci_find_root
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ldflags-y += --wrap=nvdimm_bus_register
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ldflags-y += --wrap=cxl_await_media_ready
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ldflags-y += --wrap=devm_cxl_add_rch_dport
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ldflags-y += --wrap=cxl_endpoint_parse_cdat
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ldflags-y += --wrap=devm_cxl_endpoint_decoders_setup
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ldflags-y += --wrap=hmat_get_extended_linear_cache_size
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ldflags-y += --wrap=devm_cxl_add_dport_by_dev
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ldflags-y += --wrap=devm_cxl_switch_port_decoders_setup
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DRIVERS := ../../../drivers
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CXL_SRC := $(DRIVERS)/cxl
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CXL_CORE_SRC := $(DRIVERS)/cxl/core
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ccflags-y := -I$(srctree)/drivers/cxl/
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ccflags-y += -D__mock=__weak
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ccflags-y += -DCXL_TEST_ENABLE=1
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ccflags-y += -DTRACE_INCLUDE_PATH=$(CXL_CORE_SRC) -I$(srctree)/drivers/cxl/core/
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obj-m += cxl_acpi.o
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cxl_acpi-y := $(CXL_SRC)/acpi.o
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cxl_acpi-y += mock_acpi.o
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cxl_acpi-y += config_check.o
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cxl_acpi-y += cxl_acpi_test.o
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obj-m += cxl_pmem.o
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cxl_pmem-y := $(CXL_SRC)/pmem.o
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cxl_pmem-y += $(CXL_SRC)/security.o
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cxl_pmem-y += config_check.o
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cxl_pmem-y += cxl_pmem_test.o
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obj-m += cxl_port.o
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cxl_port-y := $(CXL_SRC)/port.o
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cxl_port-y += config_check.o
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cxl_port-y += cxl_port_test.o
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obj-m += cxl_mem.o
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cxl_mem-y := $(CXL_SRC)/mem.o
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cxl_mem-y += config_check.o
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cxl_mem-y += cxl_mem_test.o
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obj-m += cxl_core.o
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cxl_core-y := $(CXL_CORE_SRC)/port.o
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cxl_core-y += $(CXL_CORE_SRC)/pmem.o
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cxl_core-y += $(CXL_CORE_SRC)/regs.o
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cxl_core-y += $(CXL_CORE_SRC)/memdev.o
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cxl_core-y += $(CXL_CORE_SRC)/mbox.o
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cxl_core-y += $(CXL_CORE_SRC)/pci.o
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cxl_core-y += $(CXL_CORE_SRC)/hdm.o
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cxl_core-y += $(CXL_CORE_SRC)/pmu.o
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cxl_core-y += $(CXL_CORE_SRC)/cdat.o
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cxl_core-$(CONFIG_TRACING) += $(CXL_CORE_SRC)/trace.o
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cxl_core-$(CONFIG_CXL_REGION) += $(CXL_CORE_SRC)/region.o
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cxl_core-$(CONFIG_CXL_MCE) += $(CXL_CORE_SRC)/mce.o
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cxl_core-$(CONFIG_CXL_FEATURES) += $(CXL_CORE_SRC)/features.o
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cxl_core-$(CONFIG_CXL_EDAC_MEM_FEATURES) += $(CXL_CORE_SRC)/edac.o
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cxl_core-$(CONFIG_CXL_RAS) += $(CXL_CORE_SRC)/ras.o
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cxl_core-$(CONFIG_CXL_RAS) += $(CXL_CORE_SRC)/ras_rch.o
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cxl_core-y += config_check.o
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cxl_core-y += cxl_core_test.o
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cxl_core-y += cxl_core_exports.o
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KBUILD_CFLAGS := $(filter-out -Wmissing-prototypes -Wmissing-declarations, $(KBUILD_CFLAGS))
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obj-m += test/
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