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Document the RZ/G2H (a.k.a. R8A774E1) SoC in the R-Car PCIe bingings. [shimoda: minor change the subject and description] Link: https://lore.kernel.org/r/1604455096-13923-4-git-send-email-yoshihiro.shimoda.uh@renesas.com Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Reviewed-by: Marian-Cristian Rotariu <marian-cristian.rotariu.rb@bp.renesas.com> Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Acked-by: Rob Herring <robh@kernel.org>
116 lines
3.4 KiB
YAML
116 lines
3.4 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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# Copyright (C) 2020 Renesas Electronics Corp.
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/pci/rcar-pci-host.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Renesas R-Car PCIe Host
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maintainers:
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- Marek Vasut <marek.vasut+renesas@gmail.com>
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- Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
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allOf:
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- $ref: pci-bus.yaml#
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properties:
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compatible:
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oneOf:
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- items:
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- enum:
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- renesas,pcie-r8a7742 # RZ/G1H
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- renesas,pcie-r8a7743 # RZ/G1M
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- renesas,pcie-r8a7744 # RZ/G1N
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- renesas,pcie-r8a7790 # R-Car H2
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- renesas,pcie-r8a7791 # R-Car M2-W
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- renesas,pcie-r8a7793 # R-Car M2-N
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- const: renesas,pcie-rcar-gen2 # R-Car Gen2 and RZ/G1
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- items:
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- enum:
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- renesas,pcie-r8a774a1 # RZ/G2M
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- renesas,pcie-r8a774b1 # RZ/G2N
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- renesas,pcie-r8a774c0 # RZ/G2E
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- renesas,pcie-r8a774e1 # RZ/G2H
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- renesas,pcie-r8a7795 # R-Car H3
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- renesas,pcie-r8a7796 # R-Car M3-W
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- renesas,pcie-r8a77961 # R-Car M3-W+
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- renesas,pcie-r8a77965 # R-Car M3-N
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- renesas,pcie-r8a77980 # R-Car V3H
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- renesas,pcie-r8a77990 # R-Car E3
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- const: renesas,pcie-rcar-gen3 # R-Car Gen3 and RZ/G2
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reg:
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maxItems: 1
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interrupts:
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minItems: 3
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maxItems: 3
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clocks:
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maxItems: 2
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clock-names:
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items:
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- const: pcie
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- const: pcie_bus
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power-domains:
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maxItems: 1
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resets:
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maxItems: 1
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phys:
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maxItems: 1
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phy-names:
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const: pcie
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required:
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- compatible
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- reg
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- interrupts
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- clocks
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- clock-names
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- power-domains
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- resets
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unevaluatedProperties: false
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examples:
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- |
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#include <dt-bindings/clock/r8a7791-cpg-mssr.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/power/r8a7791-sysc.h>
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soc {
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#address-cells = <2>;
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#size-cells = <2>;
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pcie: pcie@fe000000 {
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compatible = "renesas,pcie-r8a7791", "renesas,pcie-rcar-gen2";
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reg = <0 0xfe000000 0 0x80000>;
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#address-cells = <3>;
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#size-cells = <2>;
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bus-range = <0x00 0xff>;
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device_type = "pci";
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ranges = <0x01000000 0 0x00000000 0 0xfe100000 0 0x00100000>,
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<0x02000000 0 0xfe200000 0 0xfe200000 0 0x00200000>,
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<0x02000000 0 0x30000000 0 0x30000000 0 0x08000000>,
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<0x42000000 0 0x38000000 0 0x38000000 0 0x08000000>;
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dma-ranges = <0x42000000 0 0x40000000 0 0x40000000 0 0x40000000>,
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<0x42000000 2 0x00000000 2 0x00000000 0 0x40000000>;
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interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 0 0>;
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interrupt-map = <0 0 0 0 &gic GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&cpg CPG_MOD 319>, <&pcie_bus_clk>;
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clock-names = "pcie", "pcie_bus";
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power-domains = <&sysc R8A7791_PD_ALWAYS_ON>;
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resets = <&cpg 319>;
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};
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};
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