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80dcf0a783
Currently the high-level xor code chunks up all operations into small units for only up to 1 + 4 vectors, and passes it to four different methods. This means the FPU/vector context is entered and left a lot for wide stripes, and a lot of indirect expensive indirect calls are performed. Switch to passing the entire gen_xor request to the low-level ops, and provide a macro to dispatch it to the existing helper. This reduce the number of indirect calls and FPU/vector context switches by a factor approaching nr_stripes / 4, and also reduces source and binary code size. Link: https://lkml.kernel.org/r/20260327061704.3707577-27-hch@lst.de Signed-off-by: Christoph Hellwig <hch@lst.de> Reviewed-by: Eric Biggers <ebiggers@kernel.org> Tested-by: Eric Biggers <ebiggers@kernel.org> Cc: Albert Ou <aou@eecs.berkeley.edu> Cc: Alexander Gordeev <agordeev@linux.ibm.com> Cc: Alexandre Ghiti <alex@ghiti.fr> Cc: Andreas Larsson <andreas@gaisler.com> Cc: Anton Ivanov <anton.ivanov@cambridgegreys.com> Cc: Ard Biesheuvel <ardb@kernel.org> Cc: Arnd Bergmann <arnd@arndb.de> Cc: "Borislav Petkov (AMD)" <bp@alien8.de> Cc: Catalin Marinas <catalin.marinas@arm.com> Cc: Chris Mason <clm@fb.com> Cc: Christian Borntraeger <borntraeger@linux.ibm.com> Cc: Dan Williams <dan.j.williams@intel.com> Cc: David S. Miller <davem@davemloft.net> Cc: David Sterba <dsterba@suse.com> Cc: Heiko Carstens <hca@linux.ibm.com> Cc: Herbert Xu <herbert@gondor.apana.org.au> Cc: "H. Peter Anvin" <hpa@zytor.com> Cc: Huacai Chen <chenhuacai@kernel.org> Cc: Ingo Molnar <mingo@redhat.com> Cc: Jason A. Donenfeld <jason@zx2c4.com> Cc: Johannes Berg <johannes@sipsolutions.net> Cc: Li Nan <linan122@huawei.com> Cc: Madhavan Srinivasan <maddy@linux.ibm.com> Cc: Magnus Lindholm <linmag7@gmail.com> Cc: Matt Turner <mattst88@gmail.com> Cc: Michael Ellerman <mpe@ellerman.id.au> Cc: Nicholas Piggin <npiggin@gmail.com> Cc: Palmer Dabbelt <palmer@dabbelt.com> Cc: Richard Henderson <richard.henderson@linaro.org> Cc: Richard Weinberger <richard@nod.at> Cc: Russell King <linux@armlinux.org.uk> Cc: Song Liu <song@kernel.org> Cc: Sven Schnelle <svens@linux.ibm.com> Cc: Ted Ts'o <tytso@mit.edu> Cc: Vasily Gorbik <gor@linux.ibm.com> Cc: WANG Xuerui <kernel@xen0n.name> Cc: Will Deacon <will@kernel.org> Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
134 lines
2.9 KiB
C
134 lines
2.9 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Optimized xor_block operation for RAID4/5
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*
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* Copyright IBM Corp. 2016
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* Author(s): Martin Schwidefsky <schwidefsky@de.ibm.com>
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*/
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#include <linux/types.h>
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#include "xor_impl.h"
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#include "xor_arch.h"
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static void xor_xc_2(unsigned long bytes, unsigned long * __restrict p1,
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const unsigned long * __restrict p2)
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{
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asm volatile(
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" aghi %0,-1\n"
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" jm 3f\n"
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" srlg 0,%0,8\n"
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" ltgr 0,0\n"
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" jz 1f\n"
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"0: xc 0(256,%1),0(%2)\n"
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" la %1,256(%1)\n"
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" la %2,256(%2)\n"
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" brctg 0,0b\n"
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"1: exrl %0,2f\n"
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" j 3f\n"
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"2: xc 0(1,%1),0(%2)\n"
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"3:"
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: "+a" (bytes), "+a" (p1), "+a" (p2)
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: : "0", "cc", "memory");
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}
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static void xor_xc_3(unsigned long bytes, unsigned long * __restrict p1,
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const unsigned long * __restrict p2,
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const unsigned long * __restrict p3)
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{
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asm volatile(
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" aghi %0,-1\n"
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" jm 4f\n"
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" srlg 0,%0,8\n"
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" ltgr 0,0\n"
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" jz 1f\n"
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"0: xc 0(256,%1),0(%2)\n"
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" xc 0(256,%1),0(%3)\n"
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" la %1,256(%1)\n"
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" la %2,256(%2)\n"
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" la %3,256(%3)\n"
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" brctg 0,0b\n"
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"1: exrl %0,2f\n"
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" exrl %0,3f\n"
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" j 4f\n"
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"2: xc 0(1,%1),0(%2)\n"
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"3: xc 0(1,%1),0(%3)\n"
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"4:"
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: "+a" (bytes), "+a" (p1), "+a" (p2), "+a" (p3)
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: : "0", "cc", "memory");
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}
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static void xor_xc_4(unsigned long bytes, unsigned long * __restrict p1,
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const unsigned long * __restrict p2,
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const unsigned long * __restrict p3,
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const unsigned long * __restrict p4)
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{
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asm volatile(
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" aghi %0,-1\n"
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" jm 5f\n"
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" srlg 0,%0,8\n"
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" ltgr 0,0\n"
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" jz 1f\n"
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"0: xc 0(256,%1),0(%2)\n"
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" xc 0(256,%1),0(%3)\n"
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" xc 0(256,%1),0(%4)\n"
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" la %1,256(%1)\n"
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" la %2,256(%2)\n"
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" la %3,256(%3)\n"
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" la %4,256(%4)\n"
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" brctg 0,0b\n"
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"1: exrl %0,2f\n"
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" exrl %0,3f\n"
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" exrl %0,4f\n"
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" j 5f\n"
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"2: xc 0(1,%1),0(%2)\n"
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"3: xc 0(1,%1),0(%3)\n"
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"4: xc 0(1,%1),0(%4)\n"
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"5:"
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: "+a" (bytes), "+a" (p1), "+a" (p2), "+a" (p3), "+a" (p4)
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: : "0", "cc", "memory");
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}
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static void xor_xc_5(unsigned long bytes, unsigned long * __restrict p1,
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const unsigned long * __restrict p2,
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const unsigned long * __restrict p3,
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const unsigned long * __restrict p4,
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const unsigned long * __restrict p5)
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{
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asm volatile(
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" aghi %0,-1\n"
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" jm 6f\n"
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" srlg 0,%0,8\n"
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" ltgr 0,0\n"
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" jz 1f\n"
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"0: xc 0(256,%1),0(%2)\n"
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" xc 0(256,%1),0(%3)\n"
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" xc 0(256,%1),0(%4)\n"
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" xc 0(256,%1),0(%5)\n"
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" la %1,256(%1)\n"
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" la %2,256(%2)\n"
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" la %3,256(%3)\n"
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" la %4,256(%4)\n"
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" la %5,256(%5)\n"
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" brctg 0,0b\n"
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"1: exrl %0,2f\n"
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" exrl %0,3f\n"
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" exrl %0,4f\n"
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" exrl %0,5f\n"
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" j 6f\n"
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"2: xc 0(1,%1),0(%2)\n"
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"3: xc 0(1,%1),0(%3)\n"
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"4: xc 0(1,%1),0(%4)\n"
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"5: xc 0(1,%1),0(%5)\n"
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"6:"
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: "+a" (bytes), "+a" (p1), "+a" (p2), "+a" (p3), "+a" (p4),
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"+a" (p5)
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: : "0", "cc", "memory");
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}
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DO_XOR_BLOCKS(xc, xor_xc_2, xor_xc_3, xor_xc_4, xor_xc_5);
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struct xor_block_template xor_block_xc = {
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.name = "xc",
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.xor_gen = xor_gen_xc,
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};
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