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The modern NAND controller binding requires NAND chips to be described as
child nodes of the controller, for example:
nand-controller {
...
nand@0 {
/* raw NAND chip properties */
};
};
However, many existing device trees place NAND chip properties directly
within the controller node because those controllers support only a single
chip. This layout is still widely used by older platforms and by other DT
consumers such as U-Boot. Migrating all existing users to the new layout
will take time.
Several kernel drivers, such as ams-delta.c, davinci_nand.c and
fsmc_nand.c, still expect the legacy layout where raw NAND properties are
defined in the controller node.
To support both layouts during the transition:
- Extract NAND chip-related properties into separate schemas
(nand-property.yaml and raw-nand-property.yaml) from
nand-chip.yaml and raw-nand-chip.yaml.
- Introduce nand-controller-legacy.yaml to allow both the
legacy and modern layouts.
- Add a select condition in nand-controller.yaml to prevent
node name pattern matching for fsl,* NAND controllers.
Keep compatibility with existing device trees while allowing gradual
migration to the modern binding structure.
Signed-off-by: Frank Li <Frank.Li@nxp.com>
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
65 lines
2.0 KiB
YAML
65 lines
2.0 KiB
YAML
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/mtd/nand-property.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: NAND Chip Common Properties
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maintainers:
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- Miquel Raynal <miquel.raynal@bootlin.com>
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description: |
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This file covers the generic properties of a NAND chip. It implies that the
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bus interface should not be taken into account: both raw NAND devices and
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SPI-NAND devices are concerned by this description.
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properties:
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nand-ecc-engine:
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description: |
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A phandle on the hardware ECC engine if any. There are
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basically three possibilities:
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1/ The ECC engine is part of the NAND controller, in this
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case the phandle should reference the parent node.
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2/ The ECC engine is part of the NAND part (on-die), in this
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case the phandle should reference the node itself.
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3/ The ECC engine is external, in this case the phandle should
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reference the specific ECC engine node.
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$ref: /schemas/types.yaml#/definitions/phandle
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nand-use-soft-ecc-engine:
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description: Use a software ECC engine.
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type: boolean
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nand-no-ecc-engine:
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description: Do not use any ECC correction.
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type: boolean
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nand-ecc-algo:
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description:
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Desired ECC algorithm.
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$ref: /schemas/types.yaml#/definitions/string
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enum: [hamming, bch, rs]
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nand-ecc-strength:
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description:
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Maximum number of bits that can be corrected per ECC step.
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$ref: /schemas/types.yaml#/definitions/uint32
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minimum: 1
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nand-ecc-step-size:
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description:
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Number of data bytes covered by a single ECC step.
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$ref: /schemas/types.yaml#/definitions/uint32
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minimum: 1
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secure-regions:
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description:
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Regions in the NAND chip which are protected using a secure element
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like Trustzone. This property contains the start address and size of
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the secure regions present.
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$ref: /schemas/types.yaml#/definitions/uint64-matrix
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# This file can be referenced by more specific devices (like spi-nands)
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additionalProperties: true
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